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81. 发明授权

US06574147B2 Electrically erasable and programmable nonvolatile semiconductor memory with automatic write-verify controller 失效
标题翻译：具有自动写入验证控制器的电可擦除和可编程的非易失性半导体存储器
公开(公告)号：US06574147B2
公开(公告)日：2003-06-03
申请号：US10101213
申请日：2002-03-20
申请人： Tomoharu Tanaka , Yoshiyuki Tanaka , Hiroshi Nakamura , Hideko Odaira
发明人： Tomoharu Tanaka , Yoshiyuki Tanaka , Hiroshi Nakamura , Hideko Odaira
IPC分类号： G11C1610
CPC分类号： G11C16/3459 , G11C16/10 , G11C16/12 , G11C16/26 , G11C16/3454
摘要： A method for controlling programming of an electrically erasable and programmable nonvolatile memory having a plurality of memory cells, row and column decoders, an address buffer, and a bit line controller including a sense/latch circuit and a data I/O buffer, including supplying address signals to the address buffer to define at least one selected memory cell in the plurality of memory cells; supplying to the bit line controller programming data which corresponds to write data to be written in the selected memory cell; latching the programming data in the sense/latch circuit; writing the write data into the selected memory cell; reading the written data of the selected memory cell and verifying whether or not the data is successfully written; performing a logic operation with respect to the read data and the programming data latched in the sense/latch circuit to determine if the written memory cell is insufficiently written or successfully written; and if an insufficiently written memory cell is found, maintaining the programming data and rewriting the write data into the insufficiently written memory cell.
摘要翻译：一种用于控制具有多个存储器单元，行和列解码器，地址缓冲器和包括感测/锁存电路和数据I / O缓冲器的位线控制器的电可擦除和可编程非易失性存储器的编程的方法，包括：将地址信号发送到地址缓冲器以限定多个存储器单元中的至少一个选择的存储单元; 向位线控制器提供对应于要写入所选存储单元的写入数据的编程数据; 将编程数据锁存在感测/锁存电路中; 将写数据写入所选存储单元; 读取所选存储单元的写入数据并验证数据是否被成功写入; 对读取的数据和锁存在感测/锁存电路中的编程数据执行逻辑运算，以确定写入的存储器单元是否写入不足或成功写入; 并且如果找到写入不足的存储单元，则保持编程数据并将写入数据重写为写入不足的存储单元。

82. 发明授权

US06422165B1 Apparatus for preventing raveling of seam 失效
标题翻译：用于防止接缝开裂的装置
公开(公告)号：US06422165B1
公开(公告)日：2002-07-23
申请号：US09694162
申请日：2000-10-23
申请人： Yoshiyuki Tanaka , Takayuki Hayashida
发明人： Yoshiyuki Tanaka , Takayuki Hayashida
IPC分类号： D05B110
CPC分类号： D05B61/00
摘要： An apparatus for preventing the raveling of a seam wherein a looper thread hanging hook for catching a looper thread which is allowed to pass through a loop of a needle thread immediately before the completion of a sewing operation and a driving mechanism of the hook together with a mechanism for cutting the looper thread and the needle thread are arranged on the right side of a needle drop point of a sewing machine.
摘要翻译：一种用于防止接缝的剥离的装置，其中用于捕捉弯针线的弯针螺纹钩在紧接缝纫操作完成之前允许穿过针线的环路，并且钩子的驱动机构与用于切割弯针线和针线的机构布置在缝纫机的针落点的右侧。

83. 发明授权

US06207336B1 Liquid developing method 失效
标题翻译：液体显影法
公开(公告)号：US06207336B1
公开(公告)日：2001-03-27
申请号：US09065437
申请日：1998-04-24
申请人： Masahiko Itaya , Hiroyuki Nakagoshi , Tsutomu Sasaki , Tai Hasegawa , Toshihiro Saito , Yoshiyuki Tanaka
发明人： Masahiko Itaya , Hiroyuki Nakagoshi , Tsutomu Sasaki , Tai Hasegawa , Toshihiro Saito , Yoshiyuki Tanaka
IPC分类号： G03G1310
CPC分类号： G03G15/101 , G03G9/12 , G03G9/18 , G03G13/10
摘要： A liquid developing method that uses a highly-concentrated liquid developing agent to develop an electrostatic latent image. A highly-concentrated liquid developing agent with a viscosity of 100 to 1,000 mPa.s can be used. Therefore, a film of developing agent from 5 to 40 &mgr;m thick can be formed on the surface of the developing roller or developing belt and this provides a soft contact with the photosensitive member surface where the electrostatic latent image has been formed. If the surface of the photosensitive member does not have good release properties, a film of pre-wet liquid can be formed on the surface of the photosensitive member. A gap which is larger than the thickness of the liquid developing agent film and smaller than the sum of the thicknesses of the liquid developing agent film and the pre-wet liquid film is maintained between the surfaces of the photosensitive member and the developing roller or other developing agent bearing member such that the pre-wet liquid is always interposed between the two surfaces. Extremely good copies can be obtained if a 5 to 40 &mgr;m thin film of liquid developing agent with a viscosity of 100 to 10,000 mPa.s and containing toner with an average particle size of 1 to 5.0 &mgr;m at a concentration of 5 to 40% is used with a 30 &mgr;m or less thin film of pre-wet liquid with a viscosity of 0.5 to 5.0 mPa.s and the gap between the photosensitive member and the developing agent roller or other developing agent bearing member is set at 5 to 60 &mgr;m.
摘要翻译：使用高浓度液体显影剂显影静电潜像的液体显影方法。可以使用粘度为100至1,000mPa.s的高浓度液体显影剂。因此，可以在显影辊或显影带的表面上形成5至40μm厚的显影剂的膜，并且与形成静电潜像的感光构件表面形成软接触。如果感光构件的表面不具有良好的剥离性能，则可以在感光构件的表面上形成预湿液体膜。在感光构件和显影辊等的表面之间保持大于液体显影剂膜的厚度的间隙，并且小于液体显影剂膜和预湿液膜的厚度之和的间隙显影剂承载构件，使得预湿液体总是插入在两个表面之间。如果粘度为100〜10,000mPa·s且含有平均粒径为1〜5.0μm的调色剂浓度为5〜40％的5〜40μm的液体显影剂薄膜，则可以得到非常好的份数与30μm或更薄的预湿液体薄膜一起使用，粘度为0.5至5.0mPa.s，感光构件和显影剂辊或其它显影剂承载构件之间的间隙设定为5至60μm。

84. 发明授权

US5969988A Voltage multiplier circuit and nonvolatile semiconductor memory device having voltage multiplier 失效
标题翻译：具有电压倍增器电路的电压倍增器电路和非易失性半导体存储器件
公开(公告)号：US5969988A
公开(公告)日：1999-10-19
申请号：US598071
申请日：1996-02-07
申请人： Toru Tanzawa , Tomoharu Tanaka , Hiroshi Nakamura , Yoshiyuki Tanaka
发明人： Toru Tanzawa , Tomoharu Tanaka , Hiroshi Nakamura , Yoshiyuki Tanaka
IPC分类号： G11C17/00 , G05F1/00 , G11C5/14 , G11C16/06 , G11C16/30 , H02M3/07
CPC分类号： G11C5/145 , G11C16/30 , H02M3/073
摘要： A voltage multiplier circuit for raising an input voltage to a predetermined voltage is characterized in that a plurality of multiplier cells for raising an input voltage to be outputted, and a connection switching circuit for switching a connection state of these multiplier cells are provided, and the connection switching circuit connects multiplier cell groups formed by connecting one or a plurality of the multiplier cells, in parallel to an output, and varies the number of the multiplier cells of the multiplier cell groups and that of the multiplier cell groups.
摘要翻译：用于将输入电压升高到预定电压的电压倍增器电路的特征在于，提供用于提高要输出的输入电压的多个乘法器单元和用于切换这些乘法器单元的连接状态的连接切换电路，连接切换电路并联连接一个或多个乘法器单元形成的乘法单元组，并且改变乘法单元组和乘法单元组的乘法单元的数量。

85. 发明授权

US5821465A Joint section between flat cable and lead wires 失效
标题翻译：扁平电缆和导线之间的接头部分
公开(公告)号：US5821465A
公开(公告)日：1998-10-13
申请号：US653274
申请日：1996-05-23
申请人： Yoshiyuki Tanaka , Masataka Suzuki , Hiroyuki Ashiya , Nobuyuki Tsujino , Hidehiro Ichikawa
发明人： Yoshiyuki Tanaka , Masataka Suzuki , Hiroyuki Ashiya , Nobuyuki Tsujino , Hidehiro Ichikawa
IPC分类号： H01R43/02 , H01R4/02
CPC分类号： H01R12/61 , H01R4/029
摘要： A joint section is provided which connects a flat cable having a plurality of conductive lines with a plurality of lead wires to a plurality of joint terminals. A first end of each of the joint terminals is formed in compliance with a pitch between the two adjacent conductive lines and the second end of the joint terminals is formed in compliance with a pitch between two adjacent lead wires. Each conductive line is held between the first end of the corresponding one of the joint terminals and an auxiliary terminal placed on the conductive line and connected by a welding operation. The second end of the joint terminal is connected with a conductor of the corresponding one of the lead wires.
摘要翻译：提供一种接合部，其将具有多根导线的扁平电缆与多根引线连接到多个接合端子。每个接合端子的第一端根据两个相邻导线之间的间距形成，并且接合端子的第二端根据两个相邻引线之间的间距形成。每个导线保持在相应的一个接头端子的第一端和放置在导线上的辅助端子之间，并通过焊接操作连接。接头端子的第二端与相应的一根引线的导体连接。

86. 发明授权

US5793696A Non-volatile semiconductor memory device and memory system using the same 失效
公开(公告)号：US5793696A
公开(公告)日：1998-08-11
申请号：US826820
申请日：1997-04-08
申请人： Tomoharu Tanaka , Masaki Momodomi , Hideo Kato , Hiroto Nakai , Yoshiyuki Tanaka , Riichiro Shirota , Seiichi Aritome , Yasuo Itoh , Yoshihisa Iwata , Hiroshi Nakamura , Hideko Odaira , Yutaka Okamoto , Masamichi Asano , Kaoru Tokushige
发明人： Tomoharu Tanaka , Masaki Momodomi , Hideo Kato , Hiroto Nakai , Yoshiyuki Tanaka , Riichiro Shirota , Seiichi Aritome , Yasuo Itoh , Yoshihisa Iwata , Hiroshi Nakamura , Hideko Odaira , Yutaka Okamoto , Masamichi Asano , Kaoru Tokushige
IPC分类号： G06F11/10 , G11C16/10 , G11C16/12 , G11C16/24 , G11C16/34 , G11C29/00 , G11C29/34 , G11C29/52 , G11C13/00
CPC分类号： G11C29/785 , G06F11/1008 , G11C16/10 , G11C16/12 , G11C16/24 , G11C16/3436 , G11C16/344 , G11C16/3454 , G11C29/34 , G11C29/52 , G06F11/1068 , G06F2201/81 , G06F2212/2022
摘要： The time required for the program verify and erase verify operations can be shortened. The change of threshold values of memory cells can be suppressed even if the write and erase operations are executed repetitively. After the program and erase operations, whether the operations were properly executed can be judged simultaneously for all bit lines basing upon a change, after the pre-charge, of the potential at each bit line, without changing the column address. In the data rewrite oepration, the rewrite operation is not effected for a memory cell with the data once properly written, by changing the data in the data register.

87. 发明授权

US5780147A Laminate having improved dimensional stability and heat resistance 失效
标题翻译：层压板具有改善的尺寸稳定性和耐热性
公开(公告)号：US5780147A
公开(公告)日：1998-07-14
申请号：US614548
申请日：1996-03-13
申请人： Mikio Sugahara , Mitsutoshi Yoshinobu , Yoshiyuki Tanaka
发明人： Mikio Sugahara , Mitsutoshi Yoshinobu , Yoshiyuki Tanaka
IPC分类号： A47B13/08 , A47B96/18 , B32B7/12 , B32B27/04 , B32B15/04 , B32B15/06 , B32B15/08
CPC分类号： A47B13/086 , A47B96/18 , B32B27/04 , B32B7/12 , Y10T428/26 , Y10T428/2804 , Y10T428/31678 , Y10T428/31692 , Y10T442/3382 , Y10T442/658
摘要： Disclosed is a laminate comprising a thermosetting resin-impregnated prepreg layer (A) constituting a surface layer, a rubber or thermoplastic resin layer (B) having a flexibility and a hot melt resin adhesive layer (C), the thermosetting resin-impregnated prepreg layer and rubber or thermoplastic resin layer being heat bonded through the hot melt resin adhesive layer. The layer (A) is a prepreg impregnated with a thermosetting resin selected from a diallyl phthalate resin, an unsaturated polyester, a phenol resin, an aminoalkyd resin, an epoxy resin, an acrylurethane resin and a melamine resin. The rubber or resin of the layer (B) is a rubber or a thermoplastic resin selected from chlorinated polyethylene, polybutene, ethylene-vinyl acetate copolymer, an ethylene-propylene-diene copolymer, a chloroprene polymer, chlorosulfonated polyethylene, a styrene-butadiene copolymer and polyvinyl chloride. In addition, the hot melt resin of the layer (C) is a hot melt resin having a melting point of 60.degree. to 165.degree. C. and a solubility parameter (SP value) of 7.4 to 10.9, selected from an ethylene-vinyl acetate copolymer an ethylene-acrylic acid copolymer, carboxylated polyethylene, polyurethane, polybutylene terephthalate and a modified ethylene-vinyl acetate copolymer.
摘要翻译：公开了包含热固性树脂浸渍的预浸料层（A），构成表层的层压体，具有柔软性的橡胶或热塑性树脂层（B）和热熔树脂粘合剂层（C）的热固性树脂浸渍预浸料层并且通过热熔树脂粘合剂层热粘合橡胶或热塑性树脂层。层（A）是浸渍有选自邻苯二甲酸二烯丙酯树脂，不饱和聚酯，酚醛树脂，氨基醇酸树脂，环氧树脂，丙烯酸聚氨酯树脂和三聚氰胺树脂的热固性树脂的预浸料。层（B）的橡胶或树脂是选自氯化聚乙烯，聚丁烯，乙烯 - 乙酸乙烯酯共聚物，乙烯 - 丙烯 - 二烯共聚物，氯丁二烯聚合物，氯磺化聚乙烯，苯乙烯 - 丁二烯共聚物中的橡胶或热塑性树脂和聚氯乙烯。此外，层（C）的热熔树脂是熔点为60〜165℃的热熔树脂，溶解度参数（SP值）为7.4〜10.9，选自乙烯 - 醋酸乙烯酯共聚物，乙烯 - 丙烯酸共聚物，羧化聚乙烯，聚氨酯，聚对苯二甲酸丁二醇酯和改性的乙烯 - 乙酸乙烯酯共聚物。

88. 发明授权

US5770818A Connector for establishing connection between electric wires and flat cable and manufacturing method thereof 失效
标题翻译：用于建立电线和扁平电缆之间的连接的连接器及其制造方法
公开(公告)号：US5770818A
公开(公告)日：1998-06-23
申请号：US636557
申请日：1996-04-23
申请人： Yoshiyuki Tanaka , Kouji Koike , Masataka Suzuki , Hiroyuki Ashiya
发明人： Yoshiyuki Tanaka , Kouji Koike , Masataka Suzuki , Hiroyuki Ashiya
IPC分类号： B60R16/027 , B60R16/02 , H01R4/70 , H01R35/02 , H01R35/04 , H01R43/00 , H01R43/24 , H01R4/00 , H01R4/02
CPC分类号： B60R16/027 , H01R12/61 , H01R35/025 , H01R43/24
摘要： A cover plate for covering exposed conductive wires of a flat cable is attached to a surface of an attaching plate for holding the flat cable, and insert molding is performed in such a manner that the cover plate is included. Therefore, direct contact of a portion of flows of synthetic resin for use in performing insert molding that flows along a surface of the attaching plate for holding the flat cable with conductive wires of the flat cable can be prevented. Moreover, if the synthetic resin introduced into another surface of the attaching plate for holding the electric wires flows in joint portions between the conductive wires, the conduction wires of the flat cable are pushed against the cover plate due to the flow of the synthetic resin so that the conductive wires of the flat cable are supported. Thus, the conductive wires of the flat cable can be protected from excess stress when the insert molding operation is performed. Thus, breakage of the conductive wires of the flat cable can be prevented.
摘要翻译：用于覆盖扁平电缆的暴露的导电线的盖板被附接到用于保持扁平电缆的安装板的表面，并且以包括盖板的方式进行插入成型。因此，可以防止用于进行插入成型的一部分合成树脂流的直接接触，所述插入成型沿着用于保持扁平电缆的连接板的表面流过扁平电缆的导线。此外，如果引入到用于保持电线的连接板的另一表面中的合成树脂在导线之间的接合部分中流动，则由于合成树脂的流动，扁平电缆的导线被推到盖板上扁平电缆的导线被支撑。因此，当进行插入成型操作时，可以保护扁平电缆的导线免受过度应力。因此，可以防止扁平电缆的导线断裂。

89. 发明授权

US5615165A Non-volatile semiconductor memory device and memory system using the same 失效
标题翻译：非易失性半导体存储器件和使用其的存储器系统
公开(公告)号：US5615165A
公开(公告)日：1997-03-25
申请号：US576564
申请日：1995-12-21
申请人： Tomoharu Tanaka , Masaki Momodomi , Hideo Kato , Hiroto Nakai , Yoshiyuki Tanaka , Riichiro Shirota , Seiichi Aritome , Yasuo Itoh , Yoshihisa Iwata , Hiroshi Nakamura , Hideko Odaira , Yutaka Okamoto , Masamichi Asano , Kaoru Tokushige
发明人： Tomoharu Tanaka , Masaki Momodomi , Hideo Kato , Hiroto Nakai , Yoshiyuki Tanaka , Riichiro Shirota , Seiichi Aritome , Yasuo Itoh , Yoshihisa Iwata , Hiroshi Nakamura , Hideko Odaira , Yutaka Okamoto , Masamichi Asano , Kaoru Tokushige
IPC分类号： G06F11/10 , G11C16/10 , G11C16/12 , G11C16/24 , G11C16/34 , G11C29/00 , G11C29/34 , G11C29/52 , G11C13/00
CPC分类号： G11C29/785 , G06F11/1008 , G11C16/10 , G11C16/12 , G11C16/24 , G11C16/3436 , G11C16/344 , G11C16/3454 , G11C29/34 , G11C29/52 , G06F11/1068 , G06F2201/81 , G06F2212/2022
摘要： The time required for the program verify and erase verify operations can be shortened. The change of threshold values of memory cells can be suppressed even if the write and erase operations are executed repetitively. After the program and erase operations, whether the operations were properly executed can be judged simultaneously for all bit lines basing upon a change, after the pre-charge, of the potential at each bit line, without changing the column address. In the data rewrite operation, the rewrite operation is not effected for a memory cell with the data once properly written, by changing the data in the data register.
摘要翻译：可以缩短程序验证和擦除验证操作所需的时间。即使重复执行写入和擦除操作，也可以抑制存储单元的阈值变化。在编程和擦除操作之后，可以根据每个位线上的电位的预充电之后的所有位线同时判断操作，而不改变列地址。在数据重写操作中，通过改变数据寄存器中的数据，对具有一次适当写入的数据的存储单元不进行重写操作。

90. 发明授权

US5602789A Electrically erasable and programmable non-volatile and multi-level memory systemn with write-verify controller 失效
标题翻译：具有写入验证控制器的电可擦除和可编程的非易失性和多级存储器系统
公开(公告)号：US5602789A
公开(公告)日：1997-02-11
申请号：US518024
申请日：1995-08-22
申请人： Tetsuo Endoh , Riichiro Shirota , Kazunori Ohuchi , Ryouhei Kirisawa , Seiichi Aritome , Tomoharu Tanaka , Yoshiyuki Tanaka
发明人： Tetsuo Endoh , Riichiro Shirota , Kazunori Ohuchi , Ryouhei Kirisawa , Seiichi Aritome , Tomoharu Tanaka , Yoshiyuki Tanaka
IPC分类号： G11C11/56 , G11C16/34 , G11C29/50 , G01R31/28
CPC分类号： G11C16/3418 , G11C11/5621 , G11C11/5628 , G11C11/5635 , G11C11/5642 , G11C16/0483 , G11C16/3404 , G11C16/3413 , G11C16/3431 , G11C16/3459 , G11C29/50 , G06F2201/81 , G11C16/04 , G11C2029/0403 , G11C2211/5621
摘要： An EEPROM for storing multi-level data includes a memory cell array in which electrically erasable and programmable memory cells are arranged in matrix and each of the memory cells has at least three storage states, a write circuit for writing data to the memory cells, first and second write verify means each constituted of a sense amplifier, a data latch circuit and a detection circuit, for verifying an insufficient-written state of a memory cell and an excess-written state of a memory cell, respectively, an additional write circuit for additionally writing data to the memory cell in the insufficient-written state, and an additional erase circuit for additionally erasing data from the memory cell in the excess-written state.
摘要翻译：用于存储多级数据的EEPROM包括存储单元阵列，其中电可擦除可编程存储器单元被排列成矩阵，并且每个存储单元具有至少三个存储状态，第一存储单元写入数据的写入电路以及分别由读出放大器，数据锁存电路和检测电路构成的第二写入验证装置，用于分别验证存储器单元的写入不足状态和存储单元的过量写入状态，附加写入电路在写入状态不足的情况下向存储器单元写入数据，以及附加擦除电路，用于在超量写入状态下从存储单元附加擦除数据。

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