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81. 发明授权

US06825692B1 Input buffer for multiple differential I/O standards 有权
标题翻译：用于多个差分I / O标准的输入缓冲器
公开(公告)号：US06825692B1
公开(公告)日：2004-11-30
申请号：US10056367
申请日：2002-01-25
申请人： Jonathan Chung , In Whan Kim , Philip Pan , Chiakang Sung , Bonnie Wang , Xiaobao Wang , Yan Chong , Gopinath Rangan , Khai Nguyen , Tzung-Chin Chang , Joseph Huang
发明人： Jonathan Chung , In Whan Kim , Philip Pan , Chiakang Sung , Bonnie Wang , Xiaobao Wang , Yan Chong , Gopinath Rangan , Khai Nguyen , Tzung-Chin Chang , Joseph Huang
IPC分类号： H03K190175
CPC分类号： H03K19/018585
摘要： An input buffer circuit has a plurality of selectively enabled differential amplifier circuits, where each differential amplifier is configured for compatibility with a particular differential I/O standard and its corresponding input operating range. For example, the input buffer may have two differential amplifiers suitable for receiving LVDS differential input signals over a wide input operating range, and another differential amplifier suitable for receiving the PCML differential input signals. One or more control signals are provided to the input buffer, e.g., programmably, to selectively enable the required differential amplifier(s) for a given I/O standard.
摘要翻译：输入缓冲器电路具有多个选择性启用的差分放大器电路，其中每个差分放大器被配置为与特定差分I / O标准及其对应的输入工作范围兼容。例如，输入缓冲器可以具有适合于在宽输入工作范围内接收LVDS差分输入信号的两个差分放大器，以及适合于接收PCML差分输入信号的另一差分放大器。一个或多个控制信号例如可编程地提供给输入缓冲器，以选择性地启用给定的I / O标准所需的差分放大器。

82. 发明授权

US06747903B1 Configurable decoder for addressing a memory 有权
标题翻译：用于寻址存储器的可配置解码器
公开(公告)号：US06747903B1
公开(公告)日：2004-06-08
申请号：US10046939
申请日：2002-01-14
申请人： Philip Y. Pan , Chiakang Sung , Joseph Huang , Bonnie Wang , Khai Nguyen , Xiaobao Wang , Gopinath Rangan , In Whan Kim , Yan Chong , Tzung-Chin Chang
发明人： Philip Y. Pan , Chiakang Sung , Joseph Huang , Bonnie Wang , Khai Nguyen , Xiaobao Wang , Gopinath Rangan , In Whan Kim , Yan Chong , Tzung-Chin Chang
IPC分类号： G11C700
CPC分类号： H03K19/1776 , G11C8/16
摘要： Methods and apparatus for decoding addresses in a memory to provide mixed input and output data widths. A method includes receiving an address portion comprising a first number of bits. A second number of bits of the address portion are blocked, where the second number is less than the first number. A third number of bits are not blocked, and the third number plus the second number equal the first number. The third number of bits are decoded and a fourth number of memory cells are selected. The fourth number is equal to two to the power of the second number. A fourth number of data bits are received and multiplexed to the selected memory cells. The data bits are written to the selected memory cells.
摘要翻译：用于解码存储器中的地址以提供混合的输入和输出数据宽度的方法和装置。一种方法包括接收包括第一位数的地址部分。地址部分的第二位数被阻塞，其中第二个数字小于第一个数字。第三个位数不被阻塞，第三个数字加上第二个数字等于第一个数字。第三位数被解码，并且选择第四数量的存储单元。第四个数字等于第二个数字的两倍。接收第四数量的数据位并将其多路复用到选择的存储单元。数据位被写入选定的存储单元。

83. 发明授权

US06433579B1 Programmable logic integrated circuit devices with differential signaling capabilities 有权
标题翻译：具有差分信号功能的可编程逻辑集成电路器件
公开(公告)号：US06433579B1
公开(公告)日：2002-08-13
申请号：US09863143
申请日：2001-05-22
申请人： Bonnie I. Wang , Chiakang Sung , Yan Chong , Philip Pan , Khai Nguyen , Joseph Huang , Xiaobao Wang , In Whan Kim , Gopinath Rangan
发明人： Bonnie I. Wang , Chiakang Sung , Yan Chong , Philip Pan , Khai Nguyen , Joseph Huang , Xiaobao Wang , In Whan Kim , Gopinath Rangan
IPC分类号： H03K19177
CPC分类号： H03K19/17744 , H03K19/018521 , H03K19/1778 , H03K19/17784 , H03K19/17792
摘要： A programmable logic device is equipped for various differential signaling schemes by providing a differential output buffer on the device that can be configured according to the needs of the particular differential signaling schemes that may be used. The buffer includes a differential output driver, an adjustable current limiting circuit between the supply voltage and the differential output driver, and an adjustable current limiting circuit between the differential output driver and ground. By selectively adjusting the two current limiting circuits, the output impedance and current, as well as the common mode output voltage and the differential output voltage can be controlled.
摘要翻译：通过在设备上提供可根据可能使用的特定差分信令方案的需要进行配置的差分输出缓冲器，为各种差分信令方案配备了可编程逻辑器件。缓冲器包括差分输出驱动器，电源电压和差分输出驱动器之间的可调节限流电路，以及差分输出驱动器和地之间的可调电流限制电路。通过选择性地调节两个限流电路，可以控制输出阻抗和电流，以及共模输出电压和差分输出电压。

84. 发明授权

US09208109B2 Memory controllers with dynamic port priority assignment capabilities 有权
标题翻译：具有动态端口优先级分配功能的内存控制器
公开(公告)号：US09208109B2
公开(公告)日：2015-12-08
申请号：US13151101
申请日：2011-06-01
申请人： Michael H. M. Chu , Jeffrey Schulz , Chiakang Sung , Ravish Kapasi
发明人： Michael H. M. Chu , Jeffrey Schulz , Chiakang Sung , Ravish Kapasi
IPC分类号： G06F12/08 , G06F13/16 , G06F13/18
CPC分类号： G06F13/1626 , G06F13/16 , G06F13/1605 , G06F13/18
摘要： A programmable integrated circuit may have a memory controller that interfaces between master modules and system memory. The memory controller may receive memory access requests from the masters via ports that have associated priority values and fulfill the memory access requests by configuring system memory to respond to the memory access requests. To dynamically modify the associated priority values while the memory controller receives and fulfills the memory access requests, a priority value update module may be provided that dynamically updates priority values for the memory controller ports. The priority value update module may provide the updated priority values with update registers that are updated based on an update signal and a system clock. The priority values may be provided by shift registers, memory mapped registers, or provided by masters along with each memory access request.
摘要翻译：可编程集成电路可以具有在主模块和系统存储器之间进行接口的存储器控制器。存储器控制器可以通过具有相关优先级值的端口从主设备接收存储器访问请求，并通过配置系统存储器来响应存储器访问请求来满足存储器访问请求。为了在存储器控制器接收并满足存储器访问请求的同时动态地修改相关联的优先级值，可以提供动态地更新存储器控制器端口的优先级值的优先级值更新模块。优先级值更新模块可以根据更新信号和系统时钟向更新的优先级值提供更新的更新寄存器。优先级值可以由移位寄存器，存储器映射寄存器提供，或由主器件与每个存储器访问请求一起提供。

85. 发明授权

US09558131B1 Integrated circuit with bonding circuits for bonding memory controllers 有权
标题翻译：具有用于连接存储器控制器的接合电路的集成电路
公开(公告)号：US09558131B1
公开(公告)日：2017-01-31
申请号：US13164426
申请日：2011-06-20
申请人： Jeffrey Schulz , Chiakang Sung , Michael H. M. Chu
发明人： Jeffrey Schulz , Chiakang Sung , Michael H. M. Chu
IPC分类号： G06F13/00
CPC分类号： G06F13/00 , G06F13/1678 , G06F13/1684 , G06F13/4022
摘要： An IC that includes a first memory controller, a second memory controller, and a first bonding circuit coupled to the first memory controller, where the first bonding circuit is a hard logic bonding circuit and is operable to coordinate memory control functions of the first memory controller and the second memory controller. In one implementation, the first memory controller is an N bits wide memory controller, the second memory controller is an M bits wide memory controller, and the first bonding circuit is operable to coordinate the memory control functions of the first memory controller and the second memory controller such that the first and second memory controllers together function as an N+M bits wide memory controller, where N and M are positive integers.
摘要翻译：一种IC，包括第一存储器控制器，第二存储器控制器和耦合到第一存储器控制器的第一接合电路，其中第一接合电路是硬逻辑接合电路，并且可操作以协调第一存储器控制器的存储器控制功能和第二存储器控制器。在一个实现中，第一存储器控制器是N位宽存储器控制器，第二存储器控制器是M位宽存储器控制器，并且第一接合电路可操作以协调第一存储器控制器和第二存储器的存储器控制功能控制器，使得第一和第二存储器控制器一起用作N + M位宽存储器控制器，其中N和M是正整数。

86. 发明授权

US09032162B1 Systems and methods for providing memory controllers with memory access request merging capabilities 有权
标题翻译：为存储器控制器提供存储器访问请求合并功能的系统和方法
公开(公告)号：US09032162B1
公开(公告)日：2015-05-12
申请号：US13209137
申请日：2011-08-12
申请人： Ching-Chi Chang , Ravish Kapasi , Jeffrey Schulz , Michael H. M. Chu , Caroline Ssu-Min Chen , Chiakang Sung
发明人： Ching-Chi Chang , Ravish Kapasi , Jeffrey Schulz , Michael H. M. Chu , Caroline Ssu-Min Chen , Chiakang Sung
IPC分类号： G11C7/10
CPC分类号： G11C7/1075 , G06F13/161
摘要： An integrated circuit may include a memory controller serving as an interface between master processing modules and system memory. The master processing modules may provide memory access requests to the memory controller along with respective tag identifications. The memory controller may place the memory access requests in a queue for fulfillment. The memory controller may include a merging module that generates a memory access request to replace two or more memory access requests previously received from the master processing modules. The merging module may store information associated with the memory access requests that were merged and use the stored information to assign appropriate tag identifications to portions of data obtained from system memory when fulfilling the generated memory access request. The memory controller may include a verification module that can be used with test equipment to optimize the design of the master processing modules for improved memory access performance.
摘要翻译：集成电路可以包括用作主处理模块和系统存储器之间的接口的存储器控制器。主处理模块可以向存储器控制器提供存储器访问请求以及相应的标签标识。存储器控制器可以将存储器访问请求放置在队列中以实现。存储器控制器可以包括合并模块，其生成存储器访问请求以替换先前从主处理模块接收的两个或多个存储器访问请求。合并模块可以存储与被合并的存储器访问请求相关联的信息，并使用所存储的信息，以在满足生成的存储器访问请求时从系统存储器获得的数据部分分配适当的标签标识。存储器控制器可以包括可与测试设备一起使用的验证模块，以优化主处理模块的设计以改善存储器访问性能。

87. 发明授权

US07309906B1 Apparatus and methods for providing highly effective and area efficient decoupling capacitance in programmable logic devices 有权
标题翻译：用于在可编程逻辑器件中提供高效和区域有效的去耦电容的装置和方法
公开(公告)号：US07309906B1
公开(公告)日：2007-12-18
申请号：US11097503
申请日：2005-04-01
申请人： Jeffrey Tyhach , Bonnie I Wang , Yan Chong , Chiakang Sung
发明人： Jeffrey Tyhach , Bonnie I Wang , Yan Chong , Chiakang Sung
IPC分类号： H01L29/00 , H01L21/8242
CPC分类号： H01L29/94 , H01L27/0203
摘要： Improved decoupling capacitor designs and layout schemes are provided that generate high effective capacitance and high area efficiency at higher frequencies than that of previously known decoupling capacitor designs. The improved decoupling capacitor designs utilize transistor gates with shorter channel lengths to reduce the total parasitic resistance of the channel, thereby providing higher effective capacitance at higher frequencies. To enable higher area efficiency of this decoupling capacitor design, excess contacts are replaced with polysilicon in a grid or waffle pattern.
摘要翻译：提供了改进的去耦电容器设计和布局方案，其在比先前已知的去耦电容器设计更高的频率下产生高有效电容和高的面积效率。改进的去耦电容器设计利用具有较短沟道长度的晶体管栅极来减小沟道的总寄生电阻，从而在较高频率下提供更高的有效电容。为了实现该去耦电容器设计的更高的面积效率，多余的触点被以栅格或华夫饼形式的多晶硅替代。

88. 发明申请

US20060220703A1 Programmable high speed interface 有权
标题翻译：可编程高速接口
公开(公告)号：US20060220703A1
公开(公告)日：2006-10-05
申请号：US11446483
申请日：2006-06-02
申请人： Bonnie Wang , Chiakang Sung , Joseph Huang , Khai Nguyen , Philip Pan
发明人： Bonnie Wang , Chiakang Sung , Joseph Huang , Khai Nguyen , Philip Pan
IPC分类号： H03B1/00
CPC分类号： H03K19/17744 , H03K19/0175 , H03K19/017509 , H03K19/017581 , H03K19/1774 , H03K19/17788
摘要： Methods and apparatus for providing either high-speed, or lower-speed, flexible inputs and outputs. An input and output structure having a high-speed input, a high-speed output, a low or moderate speed input, and an low or moderate speed output is provided. One of the input and output circuits are selected and the others are deselected. The high-speed input and output circuits are comparatively simple, in one example having only a clear signal for a control line input, and are able to interface to lower speed circuitry inside the core of an integrated circuit. The low or moderate speed input and output circuits are more flexible, for example, having preset, enable, and clear as control line inputs, and are able to support JTAG boundary testing. These parallel high and lower speed circuits are user selectable such that the input output structure is optimized between speed and functionality depending on the requirements of the application.
摘要翻译：提供高速或低速灵活的输入和输出的方法和设备。提供具有高速输入，高速输出，低速或中速输入以及低速或中速输出的输入和输出结构。选择其中一个输入和输出电路，并取消选择其他电路。高速输入和输出电路相对简单，在一个示例中，仅具有用于控制线输入的清除信号，并且能够与集成电路的核心内的低速电路接口。低速或中速输入和输出电路比较灵活，例如具有预置，使能和清除作为控制线路输入，并且能够支持JTAG边界测试。这些并行高速和低速电路是用户可选择的，使得输入输出结构根据应用的要求在速度和功能之间进行优化。

89. 发明申请

US20050134332A1 Programmable high speed I/O interface 有权
标题翻译：可编程高速I / O接口
公开(公告)号：US20050134332A1
公开(公告)日：2005-06-23
申请号：US10886015
申请日：2004-07-06
申请人： Bonnie Wang , Chiakang Sung , Joseph Huang , Khai Nguyen , Philip Pan
发明人： Bonnie Wang , Chiakang Sung , Joseph Huang , Khai Nguyen , Philip Pan
IPC分类号： G06F3/00 , G06F13/38 , H03K19/0175 , H03K19/173 , H03K19/177 , H03K17/16
CPC分类号： H03K19/17744 , H03K19/0175 , H03K19/017509 , H03K19/017581 , H03K19/1774 , H03K19/17788
摘要： Methods and apparatus for providing either high-speed, or lower-speed, flexible inputs and outputs. An input and output structure having a high-speed input, a high-speed output, a low or moderate speed input, and an low or moderate speed output is provided. One of the input and output circuits are selected and the others are deselected. The high-speed input and output circuits are comparatively simple, in one example having only a clear signal for a control line input, and are able to interface to lower speed circuitry inside the core of an integrated circuit. The low or moderate speed input and output circuits are more flexible, for example, having preset, enable, and clear as control line inputs, and are able to support JTAG boundary testing. These parallel high and lower speed circuits are user selectable such that the input output structure is optimized between speed and functionality depending on the requirements of the application.
摘要翻译：提供高速或低速灵活的输入和输出的方法和设备。提供具有高速输入，高速输出，低速或中速输入以及低速或中速输出的输入和输出结构。选择其中一个输入和输出电路，并取消选择其他电路。高速输入和输出电路相对简单，在一个示例中，仅具有用于控制线输入的清除信号，并且能够与集成电路的核心内的低速电路接口。低速或中速输入和输出电路比较灵活，例如具有预置，使能和清除作为控制线路输入，并且能够支持JTAG边界测试。这些并行高速和低速电路是用户可选择的，使得输入输出结构根据应用的要求在速度和功能之间进行优化。

90. 再颁专利

USRE38651E1 Variable depth and width memory device 失效
标题翻译：可变深度和宽度的存储设备
公开(公告)号：USRE38651E1
公开(公告)日：2004-11-09
申请号：US09096917
申请日：1998-06-12
申请人： Chiakang Sung , Wanli Chang , Joseph Huang , Richard G. Cliff , L. Todd Cope , Cameron R. McClintock , William Leong , James A. Watson , Bahram Ahanin
发明人： Chiakang Sung , Wanli Chang , Joseph Huang , Richard G. Cliff , L. Todd Cope , Cameron R. McClintock , William Leong , James A. Watson , Bahram Ahanin
IPC分类号： G06F1200
CPC分类号： G11C8/12 , G01R31/318516
摘要： A programmable variable depth and width random-access memory circuit is provided. The memory circuit contains rows and columns of memory cells for storing data. A row decoder is used to address individual rows of the memory cells. Column address circuitry receives a column address signal and a width and depth selection signal. A column decoder within the column address circuitry addresses one or more columns of memory cells of the RAM array based on the selected width of the array. The output of the column decoder is routed to the appropriate column or columns of memory cells by a pattern of fixed connections and a group of programmable multiplexers. The number of data output lines to which data signals are provided is determined by the selected width of the RAM array. The output circuitry contains a group of programmable demultiplexers and a routing array having a pattern of fixed connections suitable for passing data signals from the RAM array to the selected number of data output lines.

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