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1. 发明授权

US07309906B1 Apparatus and methods for providing highly effective and area efficient decoupling capacitance in programmable logic devices 有权
标题翻译：用于在可编程逻辑器件中提供高效和区域有效的去耦电容的装置和方法
公开(公告)号：US07309906B1
公开(公告)日：2007-12-18
申请号：US11097503
申请日：2005-04-01
申请人： Jeffrey Tyhach , Bonnie I Wang , Yan Chong , Chiakang Sung
发明人： Jeffrey Tyhach , Bonnie I Wang , Yan Chong , Chiakang Sung
IPC分类号： H01L29/00 , H01L21/8242
CPC分类号： H01L29/94 , H01L27/0203
摘要： Improved decoupling capacitor designs and layout schemes are provided that generate high effective capacitance and high area efficiency at higher frequencies than that of previously known decoupling capacitor designs. The improved decoupling capacitor designs utilize transistor gates with shorter channel lengths to reduce the total parasitic resistance of the channel, thereby providing higher effective capacitance at higher frequencies. To enable higher area efficiency of this decoupling capacitor design, excess contacts are replaced with polysilicon in a grid or waffle pattern.
摘要翻译：提供了改进的去耦电容器设计和布局方案，其在比先前已知的去耦电容器设计更高的频率下产生高有效电容和高的面积效率。改进的去耦电容器设计利用具有较短沟道长度的晶体管栅极来减小沟道的总寄生电阻，从而在较高频率下提供更高的有效电容。为了实现该去耦电容器设计的更高的面积效率，多余的触点被以栅格或华夫饼形式的多晶硅替代。

2. 发明授权

US07378868B2 Modular I/O bank architecture 有权
标题翻译：模块化I / O银行架构
公开(公告)号：US07378868B2
公开(公告)日：2008-05-27
申请号：US11558363
申请日：2006-11-09
申请人： Jeffrey Tyhach , Chiakang Sung , Khai Nguyen , Sanjay K. Charagulla , Ali Burney
发明人： Jeffrey Tyhach , Chiakang Sung , Khai Nguyen , Sanjay K. Charagulla , Ali Burney
IPC分类号： H03K19/173
CPC分类号： H03K19/17744
摘要： A programmable device I/O architecture allows for a variable number of I/O banks. Each I/O bank is of an I/O bank type. Each I/O bank type has a fixed number of I/O pins. I/O banks of the same I/O bank type are compatible within the same programmable device and between different types of programmable devices. The largest size I/O bank type and intermediate size I/O bank types are adapted to be a compatible supersets of every smaller I/O bank type. Support pins are regularly distributed between data pins in each I/O bank type. Multiple instances of the same or compatible I/O banks are arranged to be accessible from different sides of the programmable device. To facilitate circuit board layout, each I/O bank is arranged as a mirror and/or rotation of other I/O banks on the device.
摘要翻译：可编程器件I / O架构允许可变数量的I / O bank。每个I / O bank都是I / O bank类型。每个I / O bank类型都有固定数量的I / O引脚。相同I / O bank类型的I / O组在同一可编程器件内和不同类型的可编程器件之间兼容。最大尺寸的I / O库类型和中等大小的I / O库类型适合于每个更小的I / O bank类型的兼容超集。支持引脚定期分布在每个I / O bank类型的数据引脚之间。相同或兼容的I / O组的多个实例被布置为可从可编程设备的不同侧面访问。为了便于电路板布局，每个I / O组被布置为设备上的其他I / O组的镜像和/或旋转。

3. 发明授权

US07218155B1 Techniques for controlling on-chip termination resistance using voltage range detection 有权
标题翻译：使用电压范围检测控制片上终端电阻的技术
公开(公告)号：US07218155B1
公开(公告)日：2007-05-15
申请号：US11040343
申请日：2005-01-20
申请人： Tzung-Chin Chang , Xiaobao Wang , Henry Kim , Chiakang Sung , Khai Q. Nguyen , Bonnie Wang , Jeffrey Tyhach , Gopinath Rangan
发明人： Tzung-Chin Chang , Xiaobao Wang , Henry Kim , Chiakang Sung , Khai Q. Nguyen , Bonnie Wang , Jeffrey Tyhach , Gopinath Rangan
IPC分类号： H03B1/00
CPC分类号： H03K19/0005
摘要： Techniques are provided for controlling an on-chip termination resistance in an input or output (IO) buffer using a calibration circuit. The calibration circuit monitors the voltage between an external resistor and a group of on-chip transistors. When voltage between the external resistor and the group of transistors is within a selected range, the calibration circuit causes the effective resistance of the transistors to match the resistance of the external resistor as closely as possible. The calibration circuit enables another set of transistors in the IO buffer so that the effective on resistance of the transistors in the IO buffer closely match the resistance of the external resistor.
摘要翻译：提供了使用校准电路控制输入或输出（IO）缓冲器中的片上终端电阻的技术。校准电路监视外部电阻和片上晶体管组之间的电压。当外部电阻和晶体管组之间的电压在选定范围内时，校准电路会使晶体管的有效电阻尽可能接近外部电阻的电阻。校准电路使得IO缓冲器中的另一组晶体管能够使得IO缓冲器中的晶体管的有效导通电阻与外部电阻器的电阻紧密匹配。

4. 发明授权

US07046037B1 Differential input buffers with elevated power supplies 有权
标题翻译：带升压电源的差分输入缓冲器
公开(公告)号：US07046037B1
公开(公告)日：2006-05-16
申请号：US11153676
申请日：2005-06-15
申请人： Jeffrey Tyhach , Bonnie Wang , Chiakang Sung , Khai Nguyen
发明人： Jeffrey Tyhach , Bonnie Wang , Chiakang Sung , Khai Nguyen
IPC分类号： H03K19/0175
CPC分类号： H03K19/018528 , H03K17/04106 , H04L25/0272 , H04L25/0292
摘要： Input buffer circuitry for handling high-speed differential input signals on an integrated circuit is provided. The input buffer circuitry may use two parallel differential input buffers with overlapping input-voltage ranges. Logic on the integrated circuit may be powered at a core-logic power supply voltage. Input-output circuitry on the integrated circuit may be powered at an input-output voltage level. To improve the performance of the input buffers in the overlap range, at least one the input buffers can be powered using a total power supply voltage drop that exceeds the core-logic power supply level. One of the input buffers may be configured to handle lower-voltage input signals. This input buffer may be powered using the input-output power supply level.
摘要翻译：提供了用于处理集成电路中的高速差分输入信号的输入缓冲电路。输入缓冲器电路可以使用具有重叠输入电压范围的两个并行差分输入缓冲器。集成电路上的逻辑可以以核心逻辑电源电压供电。集成电路上的输入输出电路可以以输入 - 输出电压电平供电。为了在重叠范围内提高输入缓冲器的性能，可以使用超过核心逻辑电源电平的总电源电压降供电至少一个输入缓冲器。其中一个输入缓冲器可被配置为处理较低电压的输入信号。该输入缓冲器可以使用输入 - 输出电源电平供电。

5. 发明授权

US07250660B1 ESD protection that supports LVDS and OCT 有权
标题翻译：支持LVDS和OCT的ESD保护
公开(公告)号：US07250660B1
公开(公告)日：2007-07-31
申请号：US10891988
申请日：2004-07-14
申请人： Cheng-Hsiung Huang , Chih-Ching Shih , Jeffrey Tyhach , Guu Lin , Chiakang Sung , Stephanie T. Tran
发明人： Cheng-Hsiung Huang , Chih-Ching Shih , Jeffrey Tyhach , Guu Lin , Chiakang Sung , Stephanie T. Tran
IPC分类号： H01L23/62 , H01L29/72 , H01L29/73 , H01L29/74 , H01L31/111
CPC分类号： H01L27/0266
摘要： Circuits are described that provide electrostatic discharge protection for I/O circuits that support the low voltage differential signaling (LVDS) and on-chip termination (OCT) standards. At least one additional transistor is connected across an I/O transistor. In the case of LVDS, a pair of stacked transistors is used in which the distance between the source/drain region and a well tap is considerably greater for the transistor connected to the I/O pad. A PMOS transistor and an NMOS transistor may also be connected in series between a first node such as a power supply node and the I/O pad. An OCT circuit is also disclosed in which the spacing between the source/drain region and a well tap in the OCT transistor is smaller than that in the I/O transistor.
摘要翻译：描述了为支持低电压差分信号（LVDS）和片上终止（OCT）标准的I / O电路提供静电放电保护的电路。在I / O晶体管上连接至少一个附加晶体管。在LVDS的情况下，使用一对堆叠的晶体管，其中源/漏区和阱抽头之间的距离对于连接到I / O焊盘的晶体管相当大。 PMOS晶体管和NMOS晶体管也可以串联连接在诸如电源节点的第一节点和I / O焊盘之间。还公开了一种OCT电路，其中源极/漏极区域和OCT晶体管中的阱阱之间的间隔小于I / O晶体管中的间距。

6. 发明授权

US06956401B1 Differential input buffers with elevated power supplies 失效
标题翻译：带升压电源的差分输入缓冲器
公开(公告)号：US06956401B1
公开(公告)日：2005-10-18
申请号：US10704964
申请日：2003-11-10
申请人： Jeffrey Tyhach , Bonnie Wang , Chiakang Sung , Khai Nguyen
发明人： Jeffrey Tyhach , Bonnie Wang , Chiakang Sung , Khai Nguyen
IPC分类号： H03K17/041 , H03K19/0175 , H03K19/0185 , H04L25/02
CPC分类号： H03K19/018528 , H03K17/04106 , H04L25/0272 , H04L25/0292
摘要： Input buffer circuitry for handling high-speed differential input signals on an integrated circuit is provided. The input buffer circuitry may use two parallel differential input buffers with overlapping input-voltage ranges. Logic on the integrated circuit may be powered at a core-logic power supply voltage. Input-output circuitry on the integrated circuit may be powered at an input-output voltage level. To improve the performance of the input buffers in the overlap range, at least one the input buffers can be powered using a total power supply voltage drop that exceeds the core-logic power supply level. One of the input buffers may be configured to handle lower-voltage input signals. This input buffer may be powered using the input-output power supply level.
摘要翻译：提供了用于处理集成电路中的高速差分输入信号的输入缓冲电路。输入缓冲器电路可以使用具有重叠输入电压范围的两个并行差分输入缓冲器。集成电路上的逻辑可以以核心逻辑电源电压供电。集成电路上的输入输出电路可以以输入 - 输出电压电平供电。为了在重叠范围内提高输入缓冲器的性能，可以使用超过核心逻辑电源电平的总电源电压降供电至少一个输入缓冲器。其中一个输入缓冲器可被配置为处理较低电压的输入信号。该输入缓冲器可以使用输入 - 输出电源电平供电。

7. 发明申请

US20070165478A1 MODULAR I/O BANK ARCHITECTURE 有权
标题翻译：模块化I / O银行架构
公开(公告)号：US20070165478A1
公开(公告)日：2007-07-19
申请号：US11558363
申请日：2006-11-09
申请人： Jeffrey Tyhach , Chiakang Sung , Khai Nguyen , Sanjay K. Charagulla , Ali Burney
发明人： Jeffrey Tyhach , Chiakang Sung , Khai Nguyen , Sanjay K. Charagulla , Ali Burney
IPC分类号： G11C8/00
CPC分类号： H03K19/17744
摘要： A programmable device I/O architecture allows for a variable number of I/O banks. Each I/O bank is of an I/O bank type. Each I/O bank type has a fixed number of I/O pins. I/O banks of the same I/O bank type are compatible within the same programmable device and between different types of programmable devices. The largest size I/O bank type and intermediate size I/O bank types are adapted to be a compatible supersets of every smaller I/O bank type. Support pins are regularly distributed between data pins in each I/O bank type. Multiple instances of the same or compatible I/O banks are arranged to be accessible from different sides of the programmable device. To facilitate circuit board layout, each I/O bank is arranged as a mirror and/or rotation of other I/O banks on the device.
摘要翻译：可编程器件I / O架构允许可变数量的I / O bank。每个I / O bank都是I / O bank类型。每个I / O bank类型都有固定数量的I / O引脚。相同I / O bank类型的I / O组在同一可编程器件内和不同类型的可编程器件之间兼容。最大尺寸的I / O库类型和中等大小的I / O库类型适合于每个更小的I / O bank类型的兼容超集。支持引脚定期分布在每个I / O bank类型的数据引脚之间。相同或兼容的I / O组的多个实例被布置为可从可编程设备的不同侧面访问。为了便于电路板布局，每个I / O组被布置为设备上的其他I / O组的镜像和/或旋转。

8. 发明授权

US09129935B1 Multi-chip packages with reduced power distribution network noise 有权
标题翻译：具有降低配电网络噪声的多芯片封装
公开(公告)号：US09129935B1
公开(公告)日：2015-09-08
申请号：US13646477
申请日：2012-10-05
申请人： Karthik Chandrasekar , Arifur Rahman , Jeffrey Tyhach
发明人： Karthik Chandrasekar , Arifur Rahman , Jeffrey Tyhach
IPC分类号： H01L23/48 , H01L49/02 , H01L21/50 , H01L21/48 , H01L23/498 , H01L25/065
CPC分类号： H01L28/40 , H01L21/486 , H01L21/50 , H01L23/147 , H01L23/49816 , H01L23/49827 , H01L23/50 , H01L23/5384 , H01L23/5385 , H01L23/642 , H01L24/05 , H01L24/14 , H01L24/16 , H01L25/0655 , H01L25/0657 , H01L2224/0401 , H01L2224/05548 , H01L2224/1411 , H01L2224/16145 , H01L2224/16225 , H01L2224/16235 , H01L2924/15192 , H01L2924/15311 , H01L2924/157
摘要： A multi-chip package that includes multiple integrated circuits is provided. An integrated circuit in the multi-chip package may be mounted on an interposer. The interposer may be mounted on a package substrate. The integrated circuit may have internal power supply terminals coupled to on-package decoupling (OPD) capacitor circuitry that are formed as part of the package substrate. The power supply terminals on the integrated circuit may be coupled to conductive routing paths and through-silicon vias (TSVs) in the interposer via microbumps. The through-silicon vias in the interposer may be coupled to the OPD capacitor circuitry via flip-chip bumps. The conductive routing paths and the TSVs in the interposer may be coupled to the internal integrated circuit power supply terminals in a way that minimizes power supply resonance noise.
摘要翻译：提供了包括多个集成电路的多芯片封装。多芯片封装中的集成电路可以安装在插入器上。插入器可以安装在封装衬底上。集成电路可以具有耦合到作为封装衬底的一部分形成的封装间去耦（OPD）电容器电路的内部电源端子。集成电路上的电源端子可以经由微注入件与中介层中的导电布线路径和穿硅通孔（TSV）耦合。插入器中的穿硅通孔可以通过倒装芯片凸块耦合到OPD电容器电路。插入器中的导电布线路径和TSV可以以最小化电源谐振噪声的方式耦合到内部集成电路电源端子。

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