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81. 发明授权

US07321518B1 Apparatus and methods for providing redundancy in integrated circuits 有权
标题翻译：在集成电路中提供冗余的装置和方法
公开(公告)号：US07321518B1
公开(公告)日：2008-01-22
申请号：US10757928
申请日：2004-01-15
申请人： Joseph Huang , Chiakang Sung , Philip Pan , Yan Chong
发明人： Joseph Huang , Chiakang Sung , Philip Pan , Yan Chong
IPC分类号： G11C7/00 , G11C29/00 , G06F7/38 , H03K19/177
CPC分类号： H03K19/1776 , G11C29/802 , G11C2229/726 , H03K19/17764
摘要： An integrated circuit (IC) includes a redundancy feature. The redundancy feature is provided by a redundancy circuitry within the IC. The redundancy circuitry is configured to provide the redundancy by using a decoder circuitry. The decoder circuitry receives and decodes coded defect information from a set of circuit elements adapted to provide the coded defect information.
摘要翻译：集成电路（IC）包括冗余特征。冗余特性由IC内的冗余电路提供。冗余电路被配置为通过使用解码器电路来提供冗余。解码器电路从适于提供编码缺陷信息的一组电路元件接收并解码编码的缺陷信息。

82. 发明授权

US06946872B1 Multiple data rate interface architecture 失效
标题翻译：多数据速率接口架构
公开(公告)号：US06946872B1
公开(公告)日：2005-09-20
申请号：US10623394
申请日：2003-07-18
申请人： Philip Pan , Chiakang Sung , Joseph Huang , Yan Chong , Bonnie I. Wang
发明人： Philip Pan , Chiakang Sung , Joseph Huang , Yan Chong , Bonnie I. Wang
IPC分类号： H03K19/177
CPC分类号： H03K19/1776 , H03K19/1774 , H03K19/17744
摘要： Method and circuitry for implementing high speed multiple-data-rate interface architectures for programmable logic devices. The invention partitions I/O pins and their corresponding registers into independent multiple-data rate I/O modules each having at least one pin dedicated to the strobe signal DQS and others to DQ data signals. The modular architecture facilitates pin migration from one generation of PLDs to the next larger generation.
摘要翻译：用于实现可编程逻辑器件的高速多数据速率接口架构的方法和电路。本发明将I / O引脚及其对应的寄存器分为独立的多数据速率I / O模块，每个I / O引脚具有至少一个专用于选通信号DQS的引脚和其他引脚用于DQ数据信号。模块化架构便于引脚从一代PLD迁移到下一代。

83. 发明授权

US06433579B1 Programmable logic integrated circuit devices with differential signaling capabilities 有权
标题翻译：具有差分信号功能的可编程逻辑集成电路器件
公开(公告)号：US06433579B1
公开(公告)日：2002-08-13
申请号：US09863143
申请日：2001-05-22
申请人： Bonnie I. Wang , Chiakang Sung , Yan Chong , Philip Pan , Khai Nguyen , Joseph Huang , Xiaobao Wang , In Whan Kim , Gopinath Rangan
发明人： Bonnie I. Wang , Chiakang Sung , Yan Chong , Philip Pan , Khai Nguyen , Joseph Huang , Xiaobao Wang , In Whan Kim , Gopinath Rangan
IPC分类号： H03K19177
CPC分类号： H03K19/17744 , H03K19/018521 , H03K19/1778 , H03K19/17784 , H03K19/17792
摘要： A programmable logic device is equipped for various differential signaling schemes by providing a differential output buffer on the device that can be configured according to the needs of the particular differential signaling schemes that may be used. The buffer includes a differential output driver, an adjustable current limiting circuit between the supply voltage and the differential output driver, and an adjustable current limiting circuit between the differential output driver and ground. By selectively adjusting the two current limiting circuits, the output impedance and current, as well as the common mode output voltage and the differential output voltage can be controlled.
摘要翻译：通过在设备上提供可根据可能使用的特定差分信令方案的需要进行配置的差分输出缓冲器，为各种差分信令方案配备了可编程逻辑器件。缓冲器包括差分输出驱动器，电源电压和差分输出驱动器之间的可调节限流电路，以及差分输出驱动器和地之间的可调电流限制电路。通过选择性地调节两个限流电路，可以控制输出阻抗和电流，以及共模输出电压和差分输出电压。

84. 发明授权

US07590879B1 Clock edge de-skew 有权
标题翻译：时钟边缘去偏移
公开(公告)号：US07590879B1
公开(公告)日：2009-09-15
申请号：US11043524
申请日：2005-01-24
申请人： Henry Kim , Bonnie I. Wang , ChiaKang Sung , Joseph Huang
发明人： Henry Kim , Bonnie I. Wang , ChiaKang Sung , Joseph Huang
IPC分类号： G06F1/12 , G06F9/00 , G06F13/42
CPC分类号： G06F13/4243
摘要： Circuits, methods, and apparatus for deskewing rising and falling edges of a clock signal. One embodiment of the present invention utilizes a delay element in a data path to adjust a data signal such that a clock signal is centered relative to the data. A further embodiment of the present invention recovers a double-data rate signal using two flip-flops, one clocked by clock rising edges, the other clocked by clock falling edges. An additional delay element is inserted in front of one or both flip-flop clock inputs. If two additional delay elements are used, they are independently adjustable such that each edge can be independently adjusted for improved data recovery.
摘要翻译：用于对时钟信号的上升沿和下降沿进行偏移的电路，方法和装置。本发明的一个实施例利用数据路径中的延迟元件来调整数据信号，使得时钟信号相对于数据居中。本发明的另一实施例使用两个触发器来恢复双数据速率信号，其中一个触发器由时钟上升沿计时，另一个由时钟下降沿计时。在一个或两个触发器时钟输入的前面插入一个附加的延迟元件。如果使用两个额外的延迟元件，则它们可独立调节，以便可以独立调整每个边沿以改善数据恢复。

85. 发明授权

US09099999B1 Adjustable drive strength input-output buffer circuitry 有权
标题翻译：可调驱动强度输入输出缓冲电路
公开(公告)号：US09099999B1
公开(公告)日：2015-08-04
申请号：US13485768
申请日：2012-05-31
申请人： Bonnie I. Wang , Chiakang Sung , Joseph Huang , Khai Nguyen , Tony Ngai , Zhe Li , Hong Shi
发明人： Bonnie I. Wang , Chiakang Sung , Joseph Huang , Khai Nguyen , Tony Ngai , Zhe Li , Hong Shi
IPC分类号： H01L29/73 , H01L29/40 , H03K17/00 , H05K1/18 , H01L25/065 , H01L27/06
CPC分类号： H03K17/00 , H01L25/0652 , H01L25/0657 , H01L27/0688 , H01L2224/16145 , H01L2224/16225 , H01L2924/0002 , H01L2924/15174 , H01L2924/15192 , H01L2924/15311 , H05K1/144 , H05K1/181 , H05K2201/045 , H05K2201/10378 , H05K2201/10674 , H05K2201/10734 , H01L2924/00
摘要： An integrated circuit in a multi-chip package is provided. The integrated circuit may include adjustable interface circuitry configured to interface with other off-chip components. In particular, the adjustable interface circuitry may include a microbump input-output buffer operable to drive signals off of the integrated circuit and operable to receive signals from other integrated circuits in the multi-chip package via a microbump. The microbump input-output buffer may include output buffers and input buffers. The output buffers may have programmable drive strengths and may each be selectively switched in and out of use depending on the desired application. Each output buffer may include a level shifter, a buffer circuit, and multiple inverter-like circuits each of which can be turned on or off to adjust the drive strength of that output buffer.
摘要翻译：提供了一种多芯片封装中的集成电路。该集成电路可以包括被配置为与其它片外部件接口的可调节接口电路。特别地，可调接口电路可以包括微控制输入 - 输出缓冲器，其可操作用于驱动离开集成电路的信号，并且可操作以经由微型小型接收器从多芯片封装中的其他集成电路接收信号。微控制输入 - 输出缓冲器可以包括输出缓冲器和输入缓冲器。输出缓冲器可以具有可编程驱动强度，并且可以根据期望的应用选择性地切换和使用。每个输出缓冲器可以包括电平移位器，缓冲电路和多个类似逆变器的电路，每个可以导通或关断以调整该输出缓冲器的驱动强度。

86. 发明申请

US20110227606A1 PROGRAMMABLE HIGH-SPEED INTERFACE 有权
标题翻译：可编程高速接口
公开(公告)号：US20110227606A1
公开(公告)日：2011-09-22
申请号：US13149168
申请日：2011-05-31
申请人： Bonnie I. Wang , Chiakang Sung , Joseph Huang , Khai Nguyen , Philip Pan
发明人： Bonnie I. Wang , Chiakang Sung , Joseph Huang , Khai Nguyen , Philip Pan
IPC分类号： H03K19/0175 , H03K3/00
CPC分类号： H03K19/17744 , H03K19/0175 , H03K19/017509 , H03K19/017581 , H03K19/1774 , H03K19/17788
摘要： Methods and apparatus for providing either high-speed, or lower-speed, flexible inputs and outputs. An input and output structure having a high-speed input, a high-speed output, a low or moderate speed input, and an low or moderate speed output is provided. One of the input and output circuits are selected and the others are deselected. The high-speed input and output circuits are comparatively simple, in one example having only a clear signal for a control line input, and are able to interface to lower speed circuitry inside the core of an integrated circuit. The low or moderate speed input and output circuits are more flexible, for example, having preset, enable, and clear as control line inputs, and are able to support JTAG boundary testing. These parallel high and lower speed circuits are user selectable such that the input output structure is optimized between speed and functionality depending on the requirements of the application.
摘要翻译：提供高速或低速灵活的输入和输出的方法和设备。提供具有高速输入，高速输出，低速或中速输入以及低速或中速输出的输入和输出结构。选择其中一个输入和输出电路，并取消选择其他电路。高速输入和输出电路相对简单，在一个示例中，仅具有用于控制线输入的清除信号，并且能够与集成电路的核心内的低速电路接口。低速或中速输入和输出电路比较灵活，例如具有预置，使能和清除作为控制线路输入，并且能够支持JTAG边界测试。这些并行高速和低速电路是用户可选择的，使得输入输出结构根据应用的要求在速度和功能之间进行优化。

87. 发明申请

US20080186056A1 PROGRAMMABLE HIGH-SPEED INTERFACE 有权
标题翻译：可编程高速接口
公开(公告)号：US20080186056A1
公开(公告)日：2008-08-07
申请号：US11830831
申请日：2007-07-30
申请人： Bonnie I. Wang , Chiakang Sung , Joseph Huang , Khai Nguyen , Philip Pan
发明人： Bonnie I. Wang , Chiakang Sung , Joseph Huang , Khai Nguyen , Philip Pan
IPC分类号： H03K19/0175
CPC分类号： H03K19/17744 , H03K19/0175 , H03K19/017509 , H03K19/017581 , H03K19/1774 , H03K19/17788
摘要： Methods and apparatus for providing either high-speed, or lower-speed, flexible inputs and outputs. An input and output structure having a high-speed input, a high-speed output, a low or moderate speed input, and an low or moderate speed output is provided. One of the input and output circuits are selected and the others are deselected. The high-speed input and output circuits are comparatively simple, in one example having only a clear signal for a control line input, and are able to interface to lower speed circuitry inside the core of an integrated circuit. The low or moderate speed input and output circuits are more flexible, for example, having preset, enable, and clear as control line inputs, and are able to support JTAG boundary testing. These parallel high and lower speed circuits are user selectable such that the input output structure is optimized between speed and functionality depending on the requirements of the application.
摘要翻译：提供高速或低速灵活的输入和输出的方法和设备。提供具有高速输入，高速输出，低速或中速输入以及低速或中速输出的输入和输出结构。选择其中一个输入和输出电路，并取消选择其他电路。高速输入和输出电路相当简单，在一个示例中，仅具有用于控制线路输入的清除信号，并且能够与集成电路的核心内的低速电路接口。低速或中速输入和输出电路比较灵活，例如具有预置，使能和清除作为控制线路输入，并且能够支持JTAG边界测试。这些并行高速和低速电路是用户可选择的，使得输入输出结构根据应用的要求在速度和功能之间进行优化。

88. 发明授权

US07190755B1 Phase-locked loop circuitry for programmable logic devices 有权
标题翻译：用于可编程逻辑器件的锁相环电路
公开(公告)号：US07190755B1
公开(公告)日：2007-03-13
申请号：US10266092
申请日：2002-10-04
申请人： Chiakang Sung , Joseph Huang , Bonnie I Wang , Richard G Cliff
发明人： Chiakang Sung , Joseph Huang , Bonnie I Wang , Richard G Cliff
IPC分类号： H03D3/24
CPC分类号： H03K19/1774 , H03K19/177 , H03L7/0891 , H03L7/0996 , H03L7/183
摘要： A phase-locked loop circuit (“PLL”) is adjustable in both phase and frequency. By providing a plurality of taps on the voltage-controlled oscillator of the PLL, and providing separate multiplexers, each of which can select a different tap—one for the PLL feedback loop and one for the PLL output—one allows the user to adjust the phase of the output relative to that of the input. Similarly, by providing loadable pre-scale (divide by N), post-scale (divide by K) and feedback-scale (divide by M) counters, one allows the user to adjust the frequency of the output to be M/(NK) times that of the input.
摘要翻译：锁相环电路（“PLL”）可在相位和频率两个方面调节。通过在PLL的压控振荡器上提供多个抽头，并提供单独的多路复用器，每个复用器可以为PLL反馈回路选择不同的抽头，并为PLL输出选择一个，一个允许用户调整输出的相位相对于输入的相位。类似地，通过提供可加载的预缩放（除以N），后标尺（除以K）和反馈量表（除以M）计数器，允许用户将输出的频率调整为M /（NK ）倍的输入。

89. 发明授权

US06707399B1 Data realignment techniques for serial-to-parallel conversion 有权
标题翻译：用于串行到并行转换的数据重新对准技术
公开(公告)号：US06707399B1
公开(公告)日：2004-03-16
申请号：US10269370
申请日：2002-10-10
申请人： Bonnie Wang , Chiakang Sung , Khai Nguyen , Joseph Huang , Gopi Rangan , Nitin Prasad
发明人： Bonnie Wang , Chiakang Sung , Khai Nguyen , Joseph Huang , Gopi Rangan , Nitin Prasad
IPC分类号： H03M900
CPC分类号： H03M9/00
摘要： Techniques for adjusting the boundary between bytes of data in a serial-to-parallel converter are provided. Bits of serial data are shifted into a first register. Data bytes are then shifted out of the first register along parallel signal lines into a second register. The timing of the parallel load of data from the first register to the second register determines the parallel data byte boundary. The boundary between the parallel data bytes can be shifted using a load enable signal. The phase of the load enable signal can be changed to shift the boundary between data bytes by one or more bits. The parallel data can then be loaded from the second register into a third register. The data output signal of the third register is synchronized to a core clock signal to ensure enough set up and hold time for signals output by the third register.
摘要翻译：提供了用于调整串并转换器中的数据字节之间边界的技术。串行数据的位被移入第一寄存器。然后，数据字节沿并行信号线移出第一寄存器，进入第二寄存器。从第一寄存器到第二寄存器的并行加载数据的时序确定并行数据字节边界。可以使用负载使能信号来移位并行数据字节之间的边界。可以改变负载使能信号的相位，以将数据字节之间的边界移位一个或多个位。然后可以将并行数据从第二寄存器加载到第三寄存器中。第三寄存器的数据输出信号与核心时钟信号同步，以确保第三寄存器输出的信号的足够的建立和保持时间。

90. 发明授权

US06437650B1 Phase-locked loop or delay-locked loop circuitry for programmable logic devices 有权
标题翻译：用于可编程逻辑器件的锁相环或延迟锁定环电路
公开(公告)号：US06437650B1
公开(公告)日：2002-08-20
申请号：US09855865
申请日：2001-05-15
申请人： Chiakang Sung , Joseph Huang , Bonnie I. Wang , Robert R. N. Bielby
发明人： Chiakang Sung , Joseph Huang , Bonnie I. Wang , Robert R. N. Bielby
IPC分类号： H03L706
CPC分类号： G06F1/10 , H03L7/0812 , H03L7/0996 , H03L7/0997
摘要： A programmable logic device is provided with phase-locked loop (“PLL”) or delay-locked loop (“DLL”) circuitry in which the feedback loop circuitry substantially parallels and duplicates a portion of the clock signal distribution network on the device that receives the main PLL/DLL output signal. In this way the distributed feedback loop circuit more readily provides a substantially exact match for the distributed delay experienced by the signal propagating through the clock signal distribution network that the PLL/DLL circuitry serves.
摘要翻译：可编程逻辑器件提供有锁相环（“PLL”）或延迟锁定环（“DLL”）电路，其中反馈回路电路在接收的设备上基本平行并复制时钟信号分配网络的一部分主PLL / DLL输出信号。以这种方式，分布式反馈环路更容易地提供对通过PLL / DLL电路服务的时钟信号分配网络传播的信号经历的分布延迟的基本精确的匹配。

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