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81. 发明授权

US6157948A Program reception/execution apparatus which can start execution of program even when only part of program is received, and program transmitter for it 失效
标题翻译：程序接收/执行装置即使只接收部分程序，也可以开始程序执行程序发送器
公开(公告)号：US6157948A
公开(公告)日：2000-12-05
申请号：US68321
申请日：1998-05-04
申请人： Shinji Inoue , Masahiro Oashi , Yuki Kusumi , Tatsuya Shimoji , Ikuo Minakata , Masayuki Kozuka , Yoshihiro Mimura , Yoshiyuki Miyabe , Kazuo Okamura , Takashi Kakiuchi , Junichi Hirai , Naoya Takao , Toshiya Mori
发明人： Shinji Inoue , Masahiro Oashi , Yuki Kusumi , Tatsuya Shimoji , Ikuo Minakata , Masayuki Kozuka , Yoshihiro Mimura , Yoshiyuki Miyabe , Kazuo Okamura , Takashi Kakiuchi , Junichi Hirai , Naoya Takao , Toshiya Mori
IPC分类号： G06F9/445 , G06F9/45 , H04N7/173 , H04N21/235 , H04N21/435 , G06F17/30
CPC分类号： G06F9/44521 , G06F8/61 , H04N21/234318 , H04N21/235 , H04N21/23614 , H04N21/4331 , H04N21/4334 , H04N21/4348 , H04N21/435 , H04N21/47815 , Y10S707/99945 , Y10S707/99948
摘要： When a program transmission apparatus divides a program into a plurality of partial programs before transmission, a program reception execution apparatus executes a partial program when the partial program has already been received, and, when the execution needs to proceed to from a present partial program to a next partial program, executes the other partial program when the next partial program has been received.
摘要翻译： PCT No.PCT / JP97 / 03143 Sec。 371日期：1998年5月4日 102（e）日期1998年5月4日PCT 1997年9月8日PCT公布。公开号WO98 / 11723 日期1998年3月19日当程序发送装置在发送之前将程序划分为多个部分程序时，程序接收执行装置在已经接收到部分程序时执行部分程序，并且当执行需要从对下一个部分节目的当前部分节目在已经接收到下一个部分节目时执行另一部分节目。

82. 发明授权

US5787471A Cache memory management apparatus having a replacement method based on the total data retrieval time and the data size 失效
标题翻译：具有基于总数据检索时间和数据大小的替换方法的缓存存储器管理装置
公开(公告)号：US5787471A
公开(公告)日：1998-07-28
申请号：US814600
申请日：1997-03-10
申请人： Shinji Inoue , Takashi Kakiuchi , Hiroki Nakamura , Masahiro Ooashi
发明人： Shinji Inoue , Takashi Kakiuchi , Hiroki Nakamura , Masahiro Ooashi
IPC分类号： G06F12/12 , G06F12/00
CPC分类号： G06F12/121
摘要： In a cache memory management device, a time measuring unit measures a time period required to obtain data from a database. The data obtained from the database is linked to the time information and both are stored in a data cache unit. If the data cache does not have sufficient room to store the data obtained from the database, a data replacement determination is made. In one embodiment, the data is replaced by referring to the total data access time. In a second embodiment, if a statistics processing unit judges that the access time and the size of each data are proportional to each other, then cache data is replaced by referring to the size information from a size calculation unit. If, however, the statistics processing unit judges that the access time and the size of each data are not proportional to each other, cache data is replaced by referring to the time information from the time measuring unit.
摘要翻译：在高速缓冲存储器管理装置中，时间测量单元测量从数据库获得数据所需的时间段。从数据库获得的数据链接到时间信息，并且两者都存储在数据高速缓存单元中。如果数据高速缓存没有足够的空间存储从数据库获得的数据，则进行数据替换确定。在一个实施例中，通过参考总数据访问时间来替换数据。在第二实施例中，如果统计处理单元判断每个数据的访问时间和大小彼此成比例，则通过参考来自大小计算单元的大小信息来替换高速缓存数据。然而，如果统计处理单元判定每个数据的访问时间和大小彼此不成比例，则参考来自时间测量单元的时间信息来代替高速缓存数据。

83. 发明授权

US4707626A Internal time-out circuit for CMOS dynamic RAM 失效
标题翻译： CMOS动态RAM的内部超时电路
公开(公告)号：US4707626A
公开(公告)日：1987-11-17
申请号：US634897
申请日：1984-07-26
申请人： Shinji Inoue
发明人： Shinji Inoue
IPC分类号： G11C11/407 , G11C11/34 , H03K3/355 , H03K5/13 , H03K3/284 , H03K5/153 , H03K17/30 , H03K19/094
CPC分类号： H03K3/355
摘要： A delay circuit for internal clock generation in a dynamic RAM uses a one-shot multivibrator composed of a pair of cross-coupled CMOS NOR gates with a RC delay circuit in the coupling path between the output of one NOR gate and the input of the other. The RC delay circuit uses an MOS transistor as the resistor, with the gate of this device connected to the supply voltage, so the resistance varies with changes in the supply. A CMOS inverter stage in the delay circuit has its input connected across the capacitor of the RC delay, so the trip point will vary with threshold voltage. In a dynamic RAM, this circuit may be used to establish the critical timing between write and read mode.
摘要翻译：用于动态RAM中内部时钟产生的延迟电路使用由一对交叉耦合的CMOS或非门组成的单稳态多谐振荡器，其中一个或非门的输出与另一个或非门的输入之间的耦合路径中具有RC延迟电路。 RC延迟电路使用MOS晶体管作为电阻，该器件的栅极连接到电源电压，因此电阻随电源的变化而变化。延迟电路中的CMOS反相器级的输入端连接在RC延迟的电容器两端，因此跳变点将随阈值电压而变化。在动态RAM中，该电路可用于建立写入和读取模式之间的关键定时。

84. 发明授权

US4631421A CMOS substrate bias generator 失效
标题翻译： CMOS衬底偏置发生器
公开(公告)号：US4631421A
公开(公告)日：1986-12-23
申请号：US640720
申请日：1984-08-14
申请人： Shinji Inoue , Rama S. Akundi
发明人： Shinji Inoue , Rama S. Akundi
IPC分类号： G05F3/20 , G11C5/14 , H03L1/00
CPC分类号： G11C5/146 , G05F3/205
摘要： A generator for producing a negative bias voltage on a semiconductor device employs an on-chip oscillator driving two charge pump circuits. The oscillator produces a frequency inversely related to the negative bias, using a feedback circuit, thus reducing standby current. Each of the charge pumps include a CMOS inverter for controlling the transistor that functions as a diode connection to the ground terminal, producing an efficient charge transfer and speeding up generation of the bias voltage. Both charge pumps are used during power-up so the bias is rapidly increased to the operating level, then one is turned off to reduce current drain. A shunt circuit prevents CMOS latch-up during power-UP by coupling the substrate node to ground, preventing forward bias of N+ source/drain regions with respect to P substrate.
摘要翻译：用于在半导体器件上产生负偏压的发生器采用驱动两个电荷泵电路的片上振荡器。振荡器产生与负偏压成反比的频率，使用反馈电路，从而降低待机电流。每个电荷泵包括用于控制用作到接地端子的二极管连接的晶体管的CMOS反相器，产生有效的电荷传输并加速产生偏置电压。在上电期间使用两个电荷泵，因此偏置快速增加到工作电平，然后关闭电源以减少漏电。分流电路通过将衬底节点耦合到地来防止上电期间的CMOS闩锁，从而防止N +源极/漏极区相对于P衬底的正向偏置。

85. 发明授权

US08180738B2 Memory controller, nonvolatile storage device, and nonvolatile storage device system 有权
标题翻译：存储控制器，非易失性存储设备和非易失性存储设备系统
公开(公告)号：US08180738B2
公开(公告)日：2012-05-15
申请号：US12304668
申请日：2007-06-15
申请人： Hiroki Etoh , Shinji Inoue , Masahiro Nakanishi
发明人： Hiroki Etoh , Shinji Inoue , Masahiro Nakanishi
IPC分类号： G06F7/00 , G06F17/00 , G06F17/30
CPC分类号： G06F21/10 , G01J5/004 , G06F21/71 , G06F21/79 , G06F2221/2141 , G06F2221/2143 , G06F2221/2153 , G11B20/00086 , G11B20/00181 , G11B20/00195 , G11B20/00492 , G11B20/00731 , G11B20/00797 , G11B27/034 , G11B27/105 , G11B27/36 , G11B2020/10537 , G11B2220/61 , H04N5/775 , H04N5/907 , H04N9/7921 , H04N9/8042 , H04N9/8205 , H04N21/4147 , H04N21/4183 , H04N21/4627 , H04N21/482 , H04N21/8355 , H04N2005/91328 , H04N2005/91364
摘要： A memory controller, a nonvolatile storage device and a nonvolatile storage device system are provided, in which the matching check between content data and meta data can be simplified, a starting time can be shortened, and further, a host device side can provide users with a common GUI without being conscious of the Usage Rule including an encryption method for copyright protection and a copyright protection method and a content management. A write status holding unit that holds write status information to identify the content data being written, and a content management unit that manages the content data and the meta data are included. The content management unit eliminates mismatch between the content data and the meta data based on the write status information. Further, a GUI script generating unit is included which generates a script describing the screen display contents in accordance with a request from the host device for the content data.
摘要翻译：提供了存储器控制器，非易失性存储装置和非易失性存储装置系统，其中可以简化内容数据和元数据之间的匹配检查，可以缩短开始时间，此外，主机装置侧可以向用户提供通用GUI，而不意识到使用规则，包括用于版权保护的加密方法和版权保护方法和内容管理。一种写入状态保持单元，其保持用于识别正在写入的内容数据的写入状态信息，以及管理内容数据和元数据的内容管理单元。内容管理单元基于写入状态信息消除内容数据和元数据之间的不匹配。此外，包括GUI脚本生成单元，其生成描述根据来自主机设备的用于内容数据的请求描述屏幕显示内容的脚本。

86. 发明申请

US20100064145A1 SEMICONDUCTOR MEMORY CARD, PLAYBACK APPARATUS, RECORDING APPARATUS, PLAYBACK METHOD, RECORDING METHOD, AND COMPUTER-READABLE RECORDING MEDIUM 有权
标题翻译：半导体存储卡，回放装置，记录装置，回放方法，记录方法和计算机可读记录介质
公开(公告)号：US20100064145A1
公开(公告)日：2010-03-11
申请号：US12539845
申请日：2009-08-12
申请人： Teruto Hirota , Kenji Tagawa , Hideki Matsushima , Tomokazu Ishikawa , Shinji Inoue , Masayuki Kozuka
发明人： Teruto Hirota , Kenji Tagawa , Hideki Matsushima , Tomokazu Ishikawa , Shinji Inoue , Masayuki Kozuka
IPC分类号： G06F12/14
CPC分类号： G11C7/16 , G06F3/16 , H04N1/32112 , H04N2201/3264
摘要： An audio stream is divided into a plurality of audio object (AOB) files that are recorded having each been encrypted using a different encryption key. At least one piece of track management information (TKI) is provided corresponding to each track. Playlist information (PLI) assigns a playback position in a playback order to each track when a plurality of tracks are to be played back one after the other.
摘要翻译：音频流被分成多个被记录的音频对象（AOB）文件，每一个都使用不同的加密密钥进行加密。对应于每个轨道提供至少一条轨道管理信息（TKI）。播放列表信息（PLI）在多个曲目要一个接一个地播放时，以播放顺序将播放位置分配给每个轨道。

87. 发明授权

US07533378B2 File-update apparatus for updating a file recorded on a recording medium 有权
标题翻译：用于更新记录在记录介质上的文件的文件更新装置
公开(公告)号：US07533378B2
公开(公告)日：2009-05-12
申请号：US10685539
申请日：2003-10-16
申请人： Takuji Maeda , Shinji Inoue
发明人： Takuji Maeda , Shinji Inoue
IPC分类号： G06F9/44
CPC分类号： G06F17/30067 , G06F11/1435
摘要： A file-update apparatus, which can mount a removable information recording medium storing a FAT and a directory entry that show a storage location, on the medium, of data constituting a content of a file, and which executes a plurality of update procedures to update the file, records progress information showing which of the update procedures have been executed in updating the file into an internal memory having a continuous power supply. Even if an abnormal stoppage of the update procedures caused by a power-down or the like occurs during updating of the FAT, for example, the progress and update information remain in the memory. Thus, the FAT and the like can be re-updated and inconsistencies resolved using this information, after recovering from the abnormal stoppage.
摘要翻译：一种文件更新装置，其能够在介质上安装存储FAT和存储位置的目录条目的可移动信息记录介质，构成文件内容的数据，并且执行多个更新程序来更新该文件记录显示在将文件更新为具有连续电源的内部存储器中执行了更新程序的进度信息。即使在更新FAT期间发生由掉电等引起的更新过程的异常停止，例如，进度和更新信息保留在存储器中。因此，在从异常停止恢复之后，可以使用该信息来重新更新FAT等并且解决不一致。

88. 发明授权

US07392342B2 Semiconductor memory card, playback apparatus, recording apparatus, playback method, recording method, and a computer-readable storage medium 有权
标题翻译：半导体存储卡，回放装置，记录装置，回放方法，记录方法以及计算机可读存储介质
公开(公告)号：US07392342B2
公开(公告)日：2008-06-24
申请号：US10968258
申请日：2004-10-20
申请人： Kenji Tagawa , Hideki Matsushima , Teruto Hirota , Tomokazu Ishikawa , Shinji Inoue , Masayuki Kozuka
发明人： Kenji Tagawa , Hideki Matsushima , Teruto Hirota , Tomokazu Ishikawa , Shinji Inoue , Masayuki Kozuka
IPC分类号： G06F12/02
CPC分类号： G11B27/105 , G06F3/16 , G11B27/329 , G11B2220/61 , G11C7/16 , H04N1/32112 , H04N2201/3264
摘要： A semiconductor memory card stores a plurality of audio objects (AOBs) that compose a plurality of tracks and playlist information showing a reproduction order for the tracks. The semiconductor memory card also stores, as resume information (PLMG_RSM_PL), (1) a Playlist_Number showing which playlist information was used the last time playback was performed for the semiconductor memory card, (2) a Track_Number showing the last track to be played back, and (3) a Playback_Time showing a position at which where playback was stopped as a time expressed in relation to the start of the track.
摘要翻译：半导体存储卡存储组成多个轨道的多个音频对象（AOB）和表示轨迹的再现顺序的播放列表信息。半导体存储卡还存储作为恢复信息（PLMG_RSM_PL）的恢复信息（1）表示最后一次为半导体存储卡重放时使用哪个播放列表信息的播放列表号，（2）显示要播放的最后一个轨道的Track_Number ，和（3）播放停止时间的播放时间，该播放时间表示相对于轨道开始表示的时间。

89. 发明申请

US20080046606A1 Host Device, Storage Device, and Method for Accessing a Storage Device 有权
标题翻译：主机设备，存储设备和访问存储设备的方法
公开(公告)号：US20080046606A1
公开(公告)日：2008-02-21
申请号：US11571597
申请日：2005-06-28
申请人： Masayuki Toyama , Takuji Maeda , Tomoaki Izumi , Shouichi Tsujita , Masahiro Nakanishi , Shinji Inoue
发明人： Masayuki Toyama , Takuji Maeda , Tomoaki Izumi , Shouichi Tsujita , Masahiro Nakanishi , Shinji Inoue
IPC分类号： G06F13/28
CPC分类号： G06F3/0659 , G06F3/0607 , G06F3/0623 , G06F3/0679
摘要： A host device (1) adds host function information indicating a function of the host device (1) to a command and transmits it to a storage device (2). The storage device (2) receives the command transmitted from the host device (1) and determines whether the function indicated by the host function information can be processed. When the function can be processed, the function is processed based on the command. When the function cannot be processed, no response is returned or error information is returned. Thus, under simple control, it is possible to prevent data destruction by a host device of an old version.
摘要翻译：主机设备（1）将指示主机设备（1）的功能的主机功能信息添加到命令中，并将其发送到存储设备（2）。存储装置（2）接收从主机装置（1）发送的命令，并且确定是否可以处理由主机功能信息指示的功能。当功能可以处理时，该功能将根据该命令进行处理。当函数无法处理时，不返回任何响应或返回错误信息。因此，在简单的控制下，可以防止主机装置破坏老版本的数据。

90. 发明申请

US20070255917A1 Host Device, Storage Device, and Method for Accessing Storage Device 有权
标题翻译：主机，存储设备和访问存储设备的方法
公开(公告)号：US20070255917A1
公开(公告)日：2007-11-01
申请号：US11571592
申请日：2005-06-28
申请人： Masayuki Toyama , Takuji Maeda , Tomoaki Izumi , Shouichi Tsujita , Masahiro Nakanishi , Shinji Inoue
发明人： Masayuki Toyama , Takuji Maeda , Tomoaki Izumi , Shouichi Tsujita , Masahiro Nakanishi , Shinji Inoue
IPC分类号： G06F12/16
CPC分类号： G06F3/0659 , G06F3/0619 , G06F3/0679
摘要： A host device transmits a command from a command transmission unit (101a) along a predetermined command sequence. A storage device (2) receives the command in a command reception unit (202a). An access determination unit (202c) determines the sequence of the command transmitted from the host device (1) and determines that reception of the access to the host device (1) is enabled only when the sequence is identical with a predetermined sequence. Thus, with simple control, it is possible to prevent data destruction by a host device of an old version.
摘要翻译：主机设备沿着预定的命令序列从命令发送单元（101a）发送命令。存储装置（2）在命令接收部（202a）中接收命令。访问确定单元（202c）确定从主机设备（1）发送的命令的顺序，并且确定只有当序列与预定序列相同时，对主机设备（1）的接入才能被使能。因此，通过简单的控制，可以防止主机装置破坏老版本的数据。

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