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81. 发明申请

US20050077955A1 Low-pass filter for a pll, phase-locked loop and semiconductor integrated circuit 失效
标题翻译：低通滤波器，用于pll，锁相环和半导体集成电路
公开(公告)号：US20050077955A1
公开(公告)日：2005-04-14
申请号：US10500875
申请日：2003-05-22
申请人： Shiro Dosho , Naoshi Yanagisawa , Masaomi Toyama , Keijiro Umehara , Masahiro Fukui , Takefumi Yoshikawa , Toru Iwata , Shiro Sakiyama , Ryoichi Suzuki
发明人： Shiro Dosho , Naoshi Yanagisawa , Masaomi Toyama , Keijiro Umehara , Masahiro Fukui , Takefumi Yoshikawa , Toru Iwata , Shiro Sakiyama , Ryoichi Suzuki
IPC分类号： H03H11/12 , H03H11/04 , H03L7/08 , H03L7/081 , H03L7/089 , H03L7/093 , H03L7/107 , H03B1/00
CPC分类号： H03L7/0812 , H03L7/0891 , H03L7/0893 , H03L7/0896 , H03L7/093
摘要： The invention provides a low-pass filter suitably used as a loop filter for a PLL or a DLL that has a filtering characteristic equivalent to that of a conventional one and can be realized in a smaller circuit area. The low-pass filter includes first filtering means (31) for accepting, as an input, an input signal to the low-pass filter and outputting a first voltage; a circuit element (311) included in the first filtering means (31) for allowing a first current to flow in accordance with the first voltage; current generating means (32) for generating a second current at a given rate to the first current; second filtering means (33) for accepting, as an input, the second current and outputting a second voltage; and adding means (34) for adding the first voltage and the second voltage and outputting an output signal of the low-pass filter, in which the second current is set to be smaller than the first current.
摘要翻译：本发明提供一种适合用作PLL或DLL的环路滤波器的低通滤波器，其具有与常规滤波特性相同的滤波特性，并且可以在较小的电路面积中实现。低通滤波器包括第一滤波装置（31），用于接收输入到低通滤波器的输入信号作为输入，并输出第一电压; 包括在第一过滤装置（31）中的用于允许第一电流根据第一电压流动的电路元件（311）电流产生装置（32），用于以给定的速率产生与第一电流的第二电流; 第二滤波装置（33），用于接受第二电流作为输入并输出第二电压; 以及添加装置（34），用于将第一电压和第二电压相加，并输出低通滤波器的输出信号，其中第二电流被设置为小于第一电流。

82. 发明授权

US06853223B2 Phase comparator and clock recovery circuit 有权
标题翻译：相位比较器和时钟恢复电路
公开(公告)号：US06853223B2
公开(公告)日：2005-02-08
申请号：US10345994
申请日：2003-01-17
申请人： Tsuyoshi Ebuchi , Takefumi Yoshikawa , Toru Iwata
发明人： Tsuyoshi Ebuchi , Takefumi Yoshikawa , Toru Iwata
IPC分类号： H03K5/26 , H03D13/00 , H03L7/08 , H03L7/087 , H03L7/089 , H04L7/033 , H03L7/06
CPC分类号： H03D13/004 , H04L7/033
摘要： The present invention aims at providing a phase comparator and a clock recovery circuit suitable for applications that support data signals with high-speed bit rates in the order of one gigabit per second. Phase comparators receive frequency divided signals NHOLDH and NHOLDL generated from a data signal RD/NRD, respectively, and intermittently perform a phase comparison between a signal dDAT and a signal CLK. This increases the timing margin for the phase comparison and makes it possible to perform a phase comparison for high-speed bit rate signals. The provision of phase comparators that serve as clock recovery circuits makes it possible to handle data signals with high-speed bit rates in the order of one gigabit per second.
摘要翻译：本发明的目的在于提供一种相位比较器和时钟恢复电路，适用于支持高速比特速率为每秒千兆位的数据信号的应用。相位比较器分别接收从数据信号RD / NRD产生的分频信号NHOLDH和NHOLDL，并间歇地执行信号dDAT和信号CLK之间的相位比较。这增加了相位比较的定时裕度，并且可以对高速比特率信号执行相位比较。提供用作时钟恢复电路的相位比较器使得可以以高达1吉比特每秒的高速比特率来处理数据信号。

83. 发明授权

US06809953B2 Potential generating circuit, potential generating device and semiconductor device using the same, and driving method thereof 有权
标题翻译：电位发生电路，电位产生装置及使用其的半导体装置及其驱动方法
公开(公告)号：US06809953B2
公开(公告)日：2004-10-26
申请号：US10440277
申请日：2003-05-16
申请人： Kenji Toyoda , Michihito Ueda , Kiyoshi Morimoto , Kiyoyuki Morita , Toru Iwata , Jun Kajiwara
发明人： Kenji Toyoda , Michihito Ueda , Kiyoshi Morimoto , Kiyoyuki Morita , Toru Iwata , Jun Kajiwara
IPC分类号： G11C1122
CPC分类号： H02M3/07 , H02M3/073
摘要： A potential generating circuit comprises a capacitor (4); a ferroelectric capacitor (6) connected in series to the capacitor (4); an output terminal (11); a capacitor (10) for grounding the output terminal (11); a switch (9) for connecting a connecting node (5) between the two capacitors (4, 6) to the output terminal (11); and a switch (1) for connecting the connecting node (5) to the ground; wherein during a first period, with the switches (1) and (9) placed in the OFF state, a terminal (3) is provided with a positive potential and a terminal (7) is grounded; wherein during a second period following the first period, the terminal (3) is grounded and the switch (9) is placed in the ON state; wherein during a third period following the second period, the switch (9) is placed in the OFF state, the switch (1) is placed in the ON state, and the terminal (7) is provided with a positive potential; wherein during a fourth period following the third period, the terminal (7) is grounded; and wherein the first through fourth periods are repeated.
摘要翻译：电位发生电路包括电容器（4）; 与电容器（4）串联连接的铁电电容器（6）。输出端子（11）; 用于使输出端子（11）接地的电容器（10）; 用于将两个电容器（4,6）之间的连接节点（5）连接到输出端子（11）的开关（9）; 和用于将连接节点（5）连接到地面的开关（1）; 其中在第一时段期间，当开关（1）和（9）处于断开状态时，端子（3）被提供有正电位并且端子（7）接地; 其中在所述第一周期之后的第二时段期间，所述端子（3）接地，并且所述开关（9）处于接通状态; 其中在所述第二时段之后的第三时段期间，所述开关（9）处于断开状态，所述开关（1）处于接通状态，并且所述端子（7）被提供有正电位; 其中在所述第三周期之后的第四周期期间，所述终端（7）接地; 并且其中重复第一至第四周期。

84. 发明授权

US06473873B1 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US06473873B1
公开(公告)日：2002-10-29
申请号：US09206534
申请日：1998-12-07
申请人： Hironori Akamatsu , Toru Iwata
发明人： Hironori Akamatsu , Toru Iwata
IPC分类号： G06F1100
CPC分类号： G11C29/10 , G11C29/36 , H01L27/10897
摘要： A semiconductor memory device includes: a memory block including a plurality of memory cells; and a test pattern generation circuit for generating at least one test pattern for use in testing the memory block. A first bus line for coupling the memory block and the test pattern generation circuit has a larger width than that of a second bus line for coupling the memory block to the exterior of the semiconductor memory device.
摘要翻译：半导体存储器件包括：包括多个存储器单元的存储器块; 以及测试图案生成电路，用于生成用于测试存储块的至少一个测试图案。用于耦合存储块和测试图案生成电路的第一总线具有比用于将存储块耦合到半导体存储器件的外部的第二总线的宽度大的宽度。

85. 发明授权

US06400637B1 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US06400637B1
公开(公告)日：2002-06-04
申请号：US09673419
申请日：2000-10-18
申请人： Hironori Akamatsu , Toru Iwata , Makoto Kojima
发明人： Hironori Akamatsu , Toru Iwata , Makoto Kojima
IPC分类号： G11C800
CPC分类号： G11C8/14 , G11C8/12 , G11C11/4087
摘要： Four memory banks (10 to 13), each having a hierarchical word line structure, are provided. If a particular mode for one of the memory banks is specified by a control packet (PKT), a mode recognizer (15) produces the leading edges of change-of-sub-word enable (SEN0-3) and change-of-column enable (CEN-3) signals with the logical level of change-of-main-word enable (MEN0-3) signal fixed. This is done to make activated ones of sub-word and column select lines changeable in each of the memory banks with the same main word line still selected. In this manner, the row access speeds increase for the respective memory banks.
摘要翻译：提供四个具有分层字线结构的存储体（10至13）。如果通过控制分组（PKT）指定存储器组中的一个的特定模式，则模式识别器（15）产生子字改变使能（SEN0-3）和列更改的前沿使能（CEN-3）信号与主字使能（MEN0-3）信号的逻辑电平固定。这样做是为了使具有相同主字线仍被选择的每个存储体中的子字和列选择线的激活的一个可变。以这种方式，各存储体的行访问速度增加。

86. 发明授权

US06246627B1 Semiconductor device capable of cutting off a leakage current in a defective array section and method thereof 有权
标题翻译：能够切断缺陷阵列部分的漏电流的半导体装置及其方法
公开(公告)号：US06246627B1
公开(公告)日：2001-06-12
申请号：US09397239
申请日：1999-09-16
申请人： Hiroyuki Yamauchi , Hironori Akamatsu , Toru Iwata , Keiichi Kusumoto , Satoshi Takahashi , Yutaka Terada , Takashi Hirata
发明人： Hiroyuki Yamauchi , Hironori Akamatsu , Toru Iwata , Keiichi Kusumoto , Satoshi Takahashi , Yutaka Terada , Takashi Hirata
IPC分类号： G11C514
CPC分类号： G01R31/3004 , H01L2924/0002 , H01L2924/00
摘要： The semiconductor device of this invention includes: an array section including a plurality of circuit blocks; a leakage current cutoff section for cutting off a leakage current occurring in at least one of the plurality of circuit blocks in the array section; and a control section for controlling the leakage current cutoff section in accordance with leakage current cutoff information.
摘要翻译：本发明的半导体器件包括：包括多个电路块的阵列部分; 泄漏电流切断部，切断在所述阵列部中的所述多个电路块中的至少一个电路中发生的漏电流; 以及控制部分，用于根据泄漏电流切断信息控制漏电流切断部分。

87. 发明授权

US06226583B1 Control device for continuously variable transmission 有权
标题翻译：无级变速器控制装置
公开(公告)号：US06226583B1
公开(公告)日：2001-05-01
申请号：US09158499
申请日：1998-09-23
申请人： Toru Iwata
发明人： Toru Iwata
IPC分类号： G06F700
CPC分类号： F16H61/6648 , F16H59/54 , F16H2059/506 , Y10T477/624 , Y10T477/65
摘要： A continuously variable transmission of an automobile which varies the drive ratio arbitrarily between an input axis and an output axis is combined with a traction control device for example which performs braking corresponding to vehicle running conditions and irrespective of the accelerator pedal depression. A microprocessor calculates the vehicle speed from the rotation speed of the output axis, calculates the target drive ratio depending on the vehicle speed, and controls the drive ratio of the continuously variable transmission to be equal to the target ratio. When the brake operation device performs braking, fluctuation of the drive ratio based on the rotation variation of the output axis is prevented by the correction of the drive ratio in the upshift direction.
摘要翻译：将输入轴与输出轴之间的驱动比任意变化的汽车的无级变速器与例如对应于车辆行驶状态进行制动的牵引力控制装置进行组合，并且与加速器踏板下压无关。微处理器根据输出轴的转速计算车速，根据车速计算目标驱动比，并将无级变速器的驱动比控制为目标比。当制动操作装置执行制动时，通过校正升档方向上的驱动比来防止基于输出轴的旋转变化的驱动比的波动。

88. 发明授权

US6145065A Memory access buffer and reordering apparatus using priorities 失效
标题翻译：使用优先级的存储器访问缓冲器和重新排序装置
公开(公告)号：US6145065A
公开(公告)日：2000-11-07
申请号：US67899
申请日：1998-04-29
申请人： Satoshi Takahashi , Hiroyuki Yamauchi , Hironori Akamatsu , Keiichi Kusumoto , Toru Iwata , Yutaka Terada , Takashi Hirata
发明人： Satoshi Takahashi , Hiroyuki Yamauchi , Hironori Akamatsu , Keiichi Kusumoto , Toru Iwata , Yutaka Terada , Takashi Hirata
IPC分类号： G06F13/16 , G06F12/02
CPC分类号： G06F13/1631
摘要： A current problem is that when a DRAM is to be accessed through a data bus, the DRAM is accessed independently of a bank, a row address, etc., and therefore, is inefficient. To solve this problem, an address bus and a data bus are connected to a main memory part independently of each other, a temporary memory part for holding a plurality of addresses in advance is disposed on the address bus side and holds addresses for every access to the main memory part regardless of transfer of data, thereby pipelining address inputting cycles. Further, for the purpose of an effective operation of the main memory part, using the addresses which are held, the addresses are rearranged in such a manner that addresses with the same row addresses become continuous to each other, or when there are not addresses with the same row addresses, addresses different banks from each other become continuous to each other, and the memory is thereafter accessed. This reduces the number of precharges, shortens a standby period which is necessary for a precharge, and realizes accessing while reducing a wasteful use of time.
摘要翻译：目前的问题在于，当通过数据总线访问DRAM时，独立于存储体，行地址等访问DRAM，因此是低效的。为了解决这个问题，地址总线和数据总线彼此独立地连接到主存储器部分，预先存储多个地址的临时存储器部分设置在地址总线侧，并且保存地址以进行每次访问主存储部分不管数据传输，从而流水线地址输入周期。此外，为了主存储器部分的有效操作，使用所保存的地址，地址被重新排列，使得具有相同行地址的地址彼此连续，或者当没有地址与相同的行地址，彼此不同的存储体彼此变得连续，并且此后访问存储器。这减少了预充电次数，缩短了预充电所需的待机时间，并实现了访问，同时减少了浪费时间的使用。

89. 发明授权

US6118309A Semiconductor circuit 失效
标题翻译：半导体电路
公开(公告)号：US6118309A
公开(公告)日：2000-09-12
申请号：US121191
申请日：1998-07-23
申请人： Hironori Akamatsu , Toru Iwata
发明人： Hironori Akamatsu , Toru Iwata
IPC分类号： G11C8/10 , H03K19/00 , H03K19/0948 , H03K19/096
CPC分类号： H03K19/0963 , G11C8/10 , H03K19/0016 , H03K19/0948
摘要： A semiconductor circuit includes an input, an output, and a first transistor and a second transistor coupled in series to a power source. The first transistor is coupled closer to the power source than the second transistor is, and the first transistor has a higher threshold voltage than a threshold voltage of the second transistor. The semiconductor circuit further includes a capacitor which is coupled between the first transistor and the second transistor.
摘要翻译：半导体电路包括输入，输出以及串联耦合到电源的第一晶体管和第二晶体管。第一晶体管比第二晶体管更靠近电源耦合，并且第一晶体管具有比第二晶体管的阈值电压更高的阈值电压。半导体电路还包括耦合在第一晶体管和第二晶体管之间的电容器。

90. 发明授权

US5970018A Semiconductor integrated circuit and decode circuit for memory 失效
标题翻译：半导体集成电路和存储器解码电路
公开(公告)号：US5970018A
公开(公告)日：1999-10-19
申请号：US974560
申请日：1997-11-19
申请人： Toru Iwata , Hironori Akamatsu
发明人： Toru Iwata , Hironori Akamatsu
IPC分类号： G11C8/10 , G11C8/00
CPC分类号： G11C8/10
摘要： In plural internal logic circuits, plural transistors having the same function are merged into a single merged transistor. This merged transistor is interposed between a ground and a virtual ground line connected with a ground node of an inverter included in each of the internal logic circuits, and has a threshold voltage higher than a threshold voltage of a transistor included in each inverter. The merged transistor is controlled in accordance with a block selecting signal. Since the merged transistor is merged among the internal logic circuits, its gate width can be set larger, resulting in attaining a high speed operation of each inverter. During a standby, a leakage current can be suppressed since the merged transistor is in an off-state. During an operation, a leakage current can be suppressed in an unselected circuit block since the merged transistor is in an off-state. Accordingly, while suppressing increase of the circuit area, the internal logic circuits can attain a high speed operation and a leakage current can be minimized during both a standby and an operation.
摘要翻译：在多个内部逻辑电路中，具有相同功能的多个晶体管被合并成单个合并晶体管。该合并后的晶体管被插入在与各内部逻辑电路中包含的逆变器的接地节点连接的地与虚拟地线之间，并且具有比每个逆变器所包含的晶体管的阈值电压高的阈值电压。合并晶体管根据块选择信号进行控制。由于合并的晶体管在内部逻辑电路之间合并，所以其栅极宽度可以设定得更大，从而达到每个逆变器的高速运行。在待机期间，由于合并晶体管处于截止状态，所以可以抑制泄漏电流。在操作期间，由于合并晶体管处于截止状态，所以在未选择的电路块中可以抑制漏电流。因此，在抑制电路面积增加的同时，内部逻辑电路能够实现高速运转，并且在备用和运转两者期间可以使漏电流最小化。

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