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81. 发明申请

US20120104507A1 METHOD FOR GROWING STRAIN-INDUCING MATERIALS IN CMOS CIRCUITS IN A GATE FIRST FLOW 有权
标题翻译：在门电路第一流程中生长应变诱导材料的方法
公开(公告)号：US20120104507A1
公开(公告)日：2012-05-03
申请号：US12938457
申请日：2010-11-03
申请人： Bo Bai , Linda Black , Abhishek Dube , Judson R. Holt , Viorel C. Ontalus , Kathryn T. Schonenberg , Matthew W. Stoker , Keith H. Tabakman
发明人： Bo Bai , Linda Black , Abhishek Dube , Judson R. Holt , Viorel C. Ontalus , Kathryn T. Schonenberg , Matthew W. Stoker , Keith H. Tabakman
IPC分类号： H01L27/092 , H01L21/8238
CPC分类号： H01L21/823807 , H01L21/823828
摘要： A method of manufacturing a complementary metal oxide semiconductor (CMOS) circuit, in which the method includes a reactive ion etch (RIE) of a CMOS circuit substrate that forms recesses, the CMOS circuit substrate including: an n-type field effect transistor (n-FET) region; a p-type field effect transistor (p-FET) region; an isolation region disposed between the n-FET and p-FET regions; and a gate wire comprising an n-FET gate, a p-FET gate, and gate material extending transversely from the n-FET gate across the isolation region to the p-FET gate, in which the recesses are formed adjacent to sidewalls of a reduced thickness; growing silicon germanium (SiGe) in the recesses; depositing a thin insulator layer on the CMOS circuit substrate; masking at least the p-FET region; removing the thin insulator layer from an unmasked n-FET region and an unmasked portion of the isolation region; etching the CMOS circuit substrate with hydrogen chloride (HCl) to remove the SiGe from the recesses in the n-FET region; and growing silicon carbon (SiC) in the exposed recesses.
摘要翻译：一种制造互补金属氧化物半导体（CMOS）电路的方法，其中所述方法包括形成凹部的CMOS电路基板的反应离子蚀刻（RIE），所述CMOS电路基板包括：n型场效应晶体管（n -FET）区域; p型场效应晶体管（p-FET）区域; 设置在n-FET和p-FET区之间的隔离区; 以及栅极线，其包括n-FET栅极，p-FET栅极和栅极材料，栅极材料从跨越隔离区域的n-FET栅极横向延伸到p-FET栅极，其中凹部形成为邻近于厚度减小在凹槽中生长硅锗（SiGe）; 在CMOS电路衬底上沉积薄的绝缘体层; 至少掩蔽p-FET区域; 从未掩蔽的n-FET区域和所述隔离区域的未屏蔽部分去除所述薄绝缘体层; 用氯化氢（HCl）蚀刻CMOS电路衬底以从n-FET区域中的凹槽去除SiGe; 并在暴露的凹槽中生长硅碳（SiC）。

82. 发明申请

US20110316044A1 DELTA MONOLAYER DOPANTS EPITAXY FOR EMBEDDED SOURCE/DRAIN SILICIDE 有权
标题翻译： DELTA MONOLAYER DOPANTS嵌入式源/漏极硅胶外观
公开(公告)号：US20110316044A1
公开(公告)日：2011-12-29
申请号：US12823163
申请日：2010-06-25
申请人： Kevin K. Chan , Abhishek Dube , Judson R. Holt , Jeffrey B. Johnson , Jinghong Li , Dae-Gyu Park , Zhengmao Zhu
发明人： Kevin K. Chan , Abhishek Dube , Judson R. Holt , Jeffrey B. Johnson , Jinghong Li , Dae-Gyu Park , Zhengmao Zhu
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/66636 , H01L21/823807 , H01L21/823814 , H01L29/165 , H01L29/665 , H01L29/6656 , H01L29/6659 , H01L29/7834 , H01L29/7848
摘要： Semiconductor structures are disclosed that have embedded stressor elements therein. The disclosed structures include at least one FET gate stack located on an upper surface of a semiconductor substrate. The at least one FET gate stack includes source and drain extension regions located within the semiconductor substrate at a footprint of the at least one FET gate stack. A device channel is also present between the source and drain extension regions and beneath the at least one gate stack. The structure further includes embedded stressor elements located on opposite sides of the at least one FET gate stack and within the semiconductor substrate. Each of the embedded stressor elements includes, from bottom to top, a first layer of a first epitaxy doped semiconductor material having a lattice constant that is different from a lattice constant of the semiconductor substrate and imparts a strain in the device channel, a second layer of a second epitaxy doped semiconductor material located atop the first layer, and a delta monolayer of dopant located on an upper surface of the second layer. The structure further includes a metal semiconductor alloy contact located directly on an upper surface of the delta monolayer.
摘要翻译：公开了在其中具有嵌入的应力元件的半导体结构。所公开的结构包括位于半导体衬底的上表面上的至少一个FET栅极堆叠。所述至少一个FET栅极堆叠包括在所述至少一个FET栅极堆叠中的覆盖区域处位于所述半导体衬底内的源极和漏极延伸区域。器件沟道也存在于源极延伸区域和漏极延伸区域之间以及至少一个栅极堆叠层下方。该结构还包括位于至少一个FET栅极堆叠的相对侧上并且位于半导体衬底内的嵌入式应力元件。每个嵌入式应力元件包括从底部到顶部的第一外延掺杂半导体材料的第一层，其具有不同于半导体衬底的晶格常数的晶格常数并且在器件沟道中施加应变;第二层位于第一层顶部的第二外延掺杂半导体材料和位于第二层的上表面上的掺杂剂的Δ单层。该结构还包括直接位于三角形单层的上表面上的金属半导体合金触点。

83. 发明申请

US20110298008A1 SELF-ALIGNED EMBEDDED SiGe STRUCTURE AND METHOD OF MANUFACTURING THE SAME 失效
标题翻译：自对准嵌入式SiGe结构及其制造方法
公开(公告)号：US20110298008A1
公开(公告)日：2011-12-08
申请号：US12795683
申请日：2010-06-08
申请人： Brian J. Greene , William K. Henson , Judson R. Holt , Michael D. Steigerwalt , Kuldeep Amarnath , Rohit Pal , Johan W. Weijtmans
发明人： Brian J. Greene , William K. Henson , Judson R. Holt , Michael D. Steigerwalt , Kuldeep Amarnath , Rohit Pal , Johan W. Weijtmans
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/66636 , H01L21/3247 , H01L29/665 , H01L29/6653 , H01L29/66545 , H01L29/7848
摘要： A low energy surface is formed by a high temperature anneal of the surfaces of trenches on each side of a gate stack. The material of the semiconductor layer reflows during the high temperature anneal such that the low energy surface is a crystallographic surface that is at a non-orthogonal angle with the surface normal of the semiconductor layer. A lattice mismatched semiconductor material is selectively grown on the semiconductor layer to fill the trenches, thereby forming embedded lattice mismatched semiconductor material portions in source and drain regions of a transistor. The embedded lattice mismatched semiconductor material portions can be in-situ doped without increasing punch-through. Alternately, a combination of intrinsic selective epitaxy and ion implantation can be employed to form deep source and drain regions.
摘要翻译：低能量表面通过栅极堆叠的每一侧的沟槽表面的高温退火形成。半导体层的材料在高温退火期间回流，使得低能表面是与半导体层的表面法线成非正交角的结晶表面。在半导体层上选择性地生长晶格失配的半导体材料以填充沟槽，从而在晶体管的源极和漏极区域中形成嵌入的晶格失配的半导体材料部分。嵌入的晶格不匹配的半导体材料部分可以原位掺杂而不增加穿通。或者，可以采用固有选择性外延和离子注入的组合来形成深的源极和漏极区域。

84. 发明申请

US20110215376A1 PRE-GATE, SOURCE/DRAIN STRAIN LAYER FORMATION 审中-公开
标题翻译：前馈，源/排水应变层形成
公开(公告)号：US20110215376A1
公开(公告)日：2011-09-08
申请号：US12719312
申请日：2010-03-08
申请人： Judson R. Holt , Viorel C. Ontalus , Keith H. Tabakman
发明人： Judson R. Holt , Viorel C. Ontalus , Keith H. Tabakman
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7848 , H01L21/823412 , H01L29/66477 , H01L29/78 , H01L29/7842 , H01L29/7849
摘要： A method produces a transistor. The method forms a strain-producing layer on a base layer and then removes at least one portion of the strain-producing layer to create at least one opening in the strain-producing layer. This leaves first and second portions of the strain-producing layer on the substrate. The first and second portions of the strain-producing layer comprise source and drain stressor regions of the transistor. The method then grows a channel region in the opening of the strain-producing layer from the base layer, forms a gate insulator on the channel region, and forms a gate conductor on the gate insulator.
摘要翻译：一种方法产生晶体管。该方法在基层上形成应变产生层，然后去除应变产生层的至少一部分以在应变产生层中产生至少一个开口。这使得在基片上产生应变的层的第一和第二部分。应变产生层的第一和第二部分包括晶体管的源极和漏极应力区域。然后，该方法从基底层在应变产生层的开口中生长通道区域，在沟道区上形成栅极绝缘体，并在栅极绝缘体上形成栅极导体。

85. 发明授权

US07687829B2 Stressed field effect transistors on hybrid orientation substrate 失效
标题翻译：混合取向衬底上强调场效应晶体管
公开(公告)号：US07687829B2
公开(公告)日：2010-03-30
申请号：US12144250
申请日：2008-06-23
申请人： Dureseti Chidambarrao , Judson R. Holt , Meikei Ieong , Qiqing C. Ouyang , Siddhartha Panda
发明人： Dureseti Chidambarrao , Judson R. Holt , Meikei Ieong , Qiqing C. Ouyang , Siddhartha Panda
IPC分类号： H01L29/04
CPC分类号： H01L29/045 , H01L21/823807 , H01L29/7843
摘要： A semiconductor structure having improved carrier mobility is provided. The semiconductor structures includes a hybrid oriented semiconductor substrate having at least two planar surfaces of different crystallographic orientation, and at least one CMOS device located on each of the planar surfaces of different crystallographic orientation, wherein each CMOS device has a stressed channel. The present invention also provides methods of fabricating the same. In general terms, the inventive method includes providing a hybrid oriented substrate having at least two planar surfaces of different crystallographic orientation, and forming at least one CMOS device on each of the planar surfaces of different crystallographic orientation, wherein each CMOS device has a stressed channel.
摘要翻译：提供了具有改进的载流子迁移率的半导体结构。半导体结构包括具有不同晶体取向的至少两个平坦表面的混合取向半导体衬底，以及位于不同结晶取向的每个平面上的至少一个CMOS器件，其中每个CMOS器件具有应力通道。本发明还提供了制造该方法的方法。一般来说，本发明的方法包括提供具有至少两个具有不同晶体取向的平面表面的混合取向衬底，以及在不同结晶取向的每个平面上形成至少一个CMOS器件，其中每个CMOS器件具有受压沟道。

86. 发明申请

US20090108302A1 MULTIPLE CRYSTALLOGRAPHIC ORIENTATION SEMICONDUCTOR STRUCTURES 失效
标题翻译：多晶体取向半导体结构
公开(公告)号：US20090108302A1
公开(公告)日：2009-04-30
申请号：US11931209
申请日：2007-10-31
申请人： Shreesh Narasimha , Paul David Agnello , Xiaomeng Chen , Judson R. Holt , Mukesh Vijay Khare , Byeong Y. Kim , Devandra K. Sadana
发明人： Shreesh Narasimha , Paul David Agnello , Xiaomeng Chen , Judson R. Holt , Mukesh Vijay Khare , Byeong Y. Kim , Devandra K. Sadana
IPC分类号： H01L27/112 , H01L21/82
CPC分类号： H01L27/1203 , H01L21/84 , H01L27/1207
摘要： A semiconductor structure includes an epitaxial surface semiconductor layer having a first dopant polarity and a first crystallographic orientation, and a laterally adjacent semiconductor-on-insulator surface semiconductor layer having a different second dopant polarity and different second crystallographic orientation. The epitaxial surface semiconductor layer has a first edge that has a defect and an adjoining second edge absent a defect. Located within the epitaxial surface semiconductor layer is a first device having a first gate perpendicular to the first edge and a second device having a second gate perpendicular to the second edge. The first device may comprise a performance sensitive logic device and the second device may comprise a yield sensitive memory device. An additional semiconductor structure includes a further laterally adjacent second semiconductor-on-insulator surface semiconductor layer having the first polarity and the second crystallographic orientation, and absent edge defects, to accommodate yield sensitive devices.
摘要翻译：半导体结构包括具有第一掺杂剂极性和第一晶体取向的外延表面半导体层以及具有不同的第二掺杂剂极性和不同的第二晶体取向的横向相邻的绝缘体上半导体表面半导体层。外延表面半导体层具有缺陷的第一边缘和缺少缺陷的邻接的第二边缘。位于外延表面半导体层内的是具有垂直于第一边缘的第一栅极的第一器件和具有垂直于第二边缘的第二栅极的第二器件。第一设备可以包括性能敏感逻辑设备，并且第二设备可以包括产出敏感存储器设备。附加的半导体结构包括具有第一极性和第二晶体取向的另外的横向相邻的第二绝缘体上半导体表面半导体层，并且没有边缘缺陷，以适应屈服敏感器件。

87. 发明申请

US20080268609A1 STACKING FAULT REDUCTION IN EPITAXIALLY GROWN SILICON 失效
标题翻译：封装在外延硅中的故障减少
公开(公告)号：US20080268609A1
公开(公告)日：2008-10-30
申请号：US12131214
申请日：2008-06-02
申请人： Yun-Yu Wang , Linda Black , Judson R. Holt , Woo-Hyeong Lee , Scott Luning , Christopher D. Sheraw
发明人： Yun-Yu Wang , Linda Black , Judson R. Holt , Woo-Hyeong Lee , Scott Luning , Christopher D. Sheraw
IPC分类号： H01L21/76
CPC分类号： H01L21/02639 , H01L21/02381 , H01L21/02433 , H01L21/02532 , H01L21/02609 , H01L21/84
摘要： Methods are disclosed for providing stacking fault reduced epitaxially grown silicon for use in hybrid surface orientation structures. In one embodiment, a method includes depositing a silicon nitride liner over a silicon oxide liner in an opening, etching to remove the silicon oxide liner and silicon nitride liner on a lower surface of the opening, undercutting the silicon nitride liner adjacent to the lower surface, and epitaxially growing silicon in the opening. The silicon is substantially reduced of stacking faults because of the negative slope created by the undercut.
摘要翻译：公开了用于提供用于混合表面取向结构的堆垛层错缺陷外延生长的硅的方法。在一个实施例中，一种方法包括在开口中的氧化硅衬垫上沉积氮化硅衬垫，蚀刻以除去开口的下表面上的氧化硅衬垫和氮化硅衬垫，将邻近下表面的氮化硅衬垫并且在开口中外延生长硅。由于底切产生的负斜率，硅片堆积层错误大大减少。

88. 发明申请

US20080206951A1 HIGH PERFORMANCE FIELD EFFECT TRANSISTORS ON SOI SUBSTRATE WITH STRESS-INDUCING MATERIAL AS BURIED INSULATOR AND METHODS 失效
标题翻译：具有应力诱导材料的SOI衬底上的高性能场效应晶体管作为绝缘绝缘体和方法
公开(公告)号：US20080206951A1
公开(公告)日：2008-08-28
申请号：US12115106
申请日：2008-05-05
申请人： Judson R. Holt , Qiqing C. Ouyang
发明人： Judson R. Holt , Qiqing C. Ouyang
IPC分类号： H01L21/86
CPC分类号： H01L29/78 , H01L21/76254 , H01L27/1203 , H01L27/1207 , H01L29/7846
摘要： The present invention provides a semiconductor structure that includes a high performance field effect transistor (FET) on a semiconductor-on-insulator (SOI) in which the insulator thereof is a stress-inducing material of a preselected geometry. Such a structure achieves performance enhancement from uniaxial stress, and the stress in the channel is not dependent on the layout design of the local contacts. In broad terms, the present invention relates to a semiconductor structure that comprises an upper semiconductor layer and a bottom semiconductor layer, wherein said upper semiconductor layer is separated from said bottom semiconductor layer in at least one region by a stress-inducing insulator having a preselected geometric shape, said stress-inducing insulator exerting a strain on the upper semiconductor layer.
摘要翻译：本发明提供了一种半导体结构，其包括绝缘体（SOI）上的高性能场效应晶体管（FET），其绝缘体是预选几何形状的应力诱导材料。这种结构可以实现单轴应力的性能提高，并且通道中的应力不依赖于局部触点的布局设计。广义而言，本发明涉及一种包括上半导体层和底半导体层的半导体结构，其中所述上半导体层通过具有预选的应力诱导绝缘体在至少一个区域中与所述底部半导体层分离几何形状，所述应力诱导绝缘子在上半导体层上施加应变。

89. 发明授权

US07381623B1 Pre-epitaxial disposable spacer integration scheme with very low temperature selective epitaxy for enhanced device performance 有权
标题翻译：具有非常低温选择性外延的预外延一次性间隔物集成方案，以提高器件性能
公开(公告)号：US07381623B1
公开(公告)日：2008-06-03
申请号：US11623882
申请日：2007-01-17
申请人： Huajie Chen , Judson R. Holt , Kern Rim , Dominic J. Schepis
发明人： Huajie Chen , Judson R. Holt , Kern Rim , Dominic J. Schepis
IPC分类号： H01L21/8234 , H01L21/336 , H01L21/331 , H01L21/36
CPC分类号： H01L21/823864 , H01L21/823412 , H01L21/823418 , H01L21/823468 , H01L21/823807 , H01L21/823814 , H01L29/165 , H01L29/6653 , H01L29/66628 , H01L29/66636 , H01L29/7848
摘要： The embodiments of the invention provide a method, etc. for a pre-epitaxial disposable spacer integration scheme with very low temperature selective epitaxy for enhanced device performance. More specifically, one method begins by forming a first gate and a second gate on a substrate. Next, an oxide layer is formed on the first and second gates; and, a nitride layer is formed on the oxide layer. Portions of the nitride layer proximate the first gate, portions of the oxide layer proximate the first gate, and portions of the substrate proximate the first gate are removed so as to form source and drain recesses proximate the first gate. Following this, the method removes remaining portions of the nitride layer, including exposing remaining portions of the oxide layer. The removal of the remaining portions of the nitride layer only exposes the remaining portions of the oxide layer and the source and drain recesses.
摘要翻译：本发明的实施例提供了一种用于具有非常低的温度选择性外延的预外延一次性间隔物集成方案的方法等，以增强器件性能。更具体地，一种方法是通过在衬底上形成第一栅极和第二栅极开始的。接下来，在第一和第二栅极上形成氧化物层; 并且在氧化物层上形成氮化物层。接近第一栅极的氮化物层的部分，靠近第一栅极的氧化物层的部分以及靠近第一栅极的衬底的部分被去除，以便形成靠近第一栅极的源极和漏极。接下来，该方法去除氮化物层的剩余部分，包括暴露氧化物层的剩余部分。去除氮化物层的剩余部分仅暴露氧化物层和源极和漏极凹槽的剩余部分。

90. 发明申请

US20070295989A1 Strained semiconductor device and method of making same 有权
标题翻译：应变半导体器件及其制造方法
公开(公告)号：US20070295989A1
公开(公告)日：2007-12-27
申请号：US11473883
申请日：2006-06-23
申请人： Jin-Ping Han , Hung Y. Ng , Judson R. Holt
发明人： Jin-Ping Han , Hung Y. Ng , Judson R. Holt
IPC分类号： H01L31/00 , H01L21/336
CPC分类号： H01L29/78 , H01L21/02532 , H01L21/0262 , H01L21/02639 , H01L29/165 , H01L29/66545 , H01L29/66628 , H01L29/66636 , H01L29/7848
摘要： A semiconductor body is formed from a first semiconductor material, e.g., silicon. A compound semiconductor region, e.g., silicon germanium, is embedded in the semiconductor body. The compound semiconductor region includes the first semiconductor material and a second semiconductor material. The compound semiconductor region has a concentration of the second semiconductor material that varies along an interface between the side portion of the compound semiconductor region and the side portion of the semiconductor body
摘要翻译：半导体本体由诸如硅的第一半导体材料形成。诸如硅锗的化合物半导体区域被嵌入在半导体本体中。化合物半导体区域包括第一半导体材料和第二半导体材料。化合物半导体区域具有沿着化合物半导体区域的侧部与半导体本体的侧部之间的界面变化的第二半导体材料的浓度

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