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    • 87. 发明授权
    • Delay adjusting method and LSI that uses air-gap wiring
    • 延时调整方法和使用气隙接线的LSI
    • US08122405B2
    • 2012-02-21
    • US12253469
    • 2008-10-17
    • Takashi MatsumotoJunji NoguchiTakayuki Oshima
    • Takashi MatsumotoJunji NoguchiTakayuki Oshima
    • G06F17/50
    • G06F17/5031H01L21/7682H01L2924/0002H01L2924/00
    • Provided is a method for manufacturing a semiconductor integrated circuit device which enables a timing optimization without giving additions to a manufacturing process and increasing cost and TAT. Existence of a timing constraint violation is determined, and when a timing constraint violation is detected, to dissolve the violation, a void formation inhibition zone is set up in a part or all of a spacing (inter-wiring spacing) between an optimization-target wiring which needs a further delay time of a signal and clock and an adjacent wiring adjacent to the optimization-target wiring having a spacing within a specified wiring spacing, and an insulating film is formed in a spacing (inter-wiring spacing) between the optimization-target wiring and the adjacent wiring in the void formation inhibition zone, and voids are formed in a spacing (inter-wiring spacing) between the optimization-target wiring and the adjacent wiring outside the void formation inhibition zone.
    • 提供一种制造半导体集成电路器件的方法,其能够进行定时优化,而不增加制造工艺并增加成本和TAT。 确定定时约束违规的存在,并且当检测到定时约束违规时,为了解决违规,在优化目标之间的间隔(布线间距)的一部分或全部中建立空隙形成禁止区 需要进一步延迟信号和时钟的延迟时间的布线以及与优选目标布线相邻的相邻布线,其间距在指定布线间距内,并且绝缘膜以优选的间隔(布线间距)形成 在空隙形成抑制区域中的目标布线和相邻布线,并且在空隙形成抑制区外部的优化目标布线和相邻布线之间的间隔(布线间距)形成空隙。