专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

81. 发明申请

US20080298553A1 Particle-Beam Treatment System 有权
标题翻译：粒子束处理系统
公开(公告)号：US20080298553A1
公开(公告)日：2008-12-04
申请号：US11870512
申请日：2007-10-11
申请人： Osamu Takahashi , Yuehu Pu , Hisashi Harada , Masahiro Ikeda , Yasuyuki Takatani , Hiroshi Otani
发明人： Osamu Takahashi , Yuehu Pu , Hisashi Harada , Masahiro Ikeda , Yasuyuki Takatani , Hiroshi Otani
IPC分类号： G21K5/04
CPC分类号： A61N5/1042 , A61B5/1127 , A61N5/1064 , A61N2005/1059 , A61N2005/1087 , G21K1/046
摘要： Provision is made for a particle-beam treatment system in which, even during particle-beam irradiation, the shape of a multileaf collimator is monitored. The particle-beam treatment system, in which multi-layer conformal irradiation is performed while the setting of the shape of the multileaf collimator in an irradiation head is changed during particle-beam irradiation, is provided with an optical shape-monitoring unit mounted attachably and detachably in the snout portion at the downstream side of the multileaf collimator, the optical shape-monitoring unit having a shape-monitoring mirror, opposing the multileaf collimator, for monitoring the shape of the multileaf collimator; a video camera for shooting the multileaf-collimator shape reflected by the shape-monitoring mirror; and an image monitor for displaying an image of the video camera that shoots the shape of the multileaf collimator.
摘要翻译：规定了一种粒子束处理系统，其中即使在粒子束照射期间，监视多叶准直器的形状。在粒子束照射期间，在照射头中的多叶准直器的形状的设定被改变的同时进行多层共形照射的粒子束处理系统设置有可安装地安装的光学形状监视单元，所述光学形状监视单元具有与所述多叶准直器相对的形状监视镜，用于监视所述多叶准直器的形状; 用于拍摄由形状监视镜反射的多叶准直器形状的摄像机; 以及用于显示拍摄多叶准直器的形状的摄像机的图像的图像监视器。

82. 发明申请

US20080189670A1 METHOD OF LOGIC CIRCUIT SYNTHESIS AND DESIGN USING A DYNAMIC CIRCUIT LIBRARY 有权
标题翻译：使用动态电路图的逻辑电路合成和设计方法
公开(公告)号：US20080189670A1
公开(公告)日：2008-08-07
申请号：US12060768
申请日：2008-04-01
申请人： Sang Hoo Dhong , Harm Peter Hofstee , Stephen Douglas Posluszny , Joel Abraham Silberman , Osamu Takahashi , Dieter F. Wendel
发明人： Sang Hoo Dhong , Harm Peter Hofstee , Stephen Douglas Posluszny , Joel Abraham Silberman , Osamu Takahashi , Dieter F. Wendel
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： The circuit library available for logic synthesis is limited to a single dynamic circuit block or logic synthesis block. The circuit design method includes first defining the logic synthesis block and then performing logic synthesis for a predetermined logical operation to be implemented. The logic synthesis step constrained to the single logic synthesis block produces an intermediate circuit design which necessarily comprises a series of dynamic circuit blocks, each associated with a single reset signal. Once the intermediate circuit is produced, the circuit design method includes eliminating unnecessary devices from the intermediate circuit to produce a final logic circuit, and then sizing the devices in the final circuit to complete the design.
摘要翻译：可用于逻辑合成的电路库限于单个动态电路块或逻辑合成块。电路设计方法包括首先定义逻辑合成块，然后执行用于要实现的预定逻辑运算的逻辑合成。限制到单个逻辑合成块的逻辑合成步骤产生中间电路设计，其必然包括一系列动态电路块，每个动态电路块与单个复位信号相关联。一旦生成了中间电路，电路设计方法包括从中间电路中消除不必要的设备，产生最终的逻辑电路，然后对最终电路中的器件进行尺寸调整以完成设计。

83. 发明授权

US07363609B2 Method of logic circuit synthesis and design using a dynamic circuit library 有权
标题翻译：使用动态电路库的逻辑电路合成与设计方法
公开(公告)号：US07363609B2
公开(公告)日：2008-04-22
申请号：US09915437
申请日：2001-07-26
申请人： Sang Hoo Dhong , Harm Peter Hofstee , Stephen Douglas Posluszny , Joel Abraham Silberman , Osamu Takahashi , Dieter F. Wendel
发明人： Sang Hoo Dhong , Harm Peter Hofstee , Stephen Douglas Posluszny , Joel Abraham Silberman , Osamu Takahashi , Dieter F. Wendel
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： The circuit library available for logic synthesis is limited to a single dynamic circuit block or logic synthesis block. The circuit design method includes first defining the logic synthesis block (16) and then performing logic synthesis (17) for a predetermined logical operation to be implemented. The logic synthesis step constrained to the single logic synthesis block produces an intermediate circuit design (29) which necessarily comprises a series of dynamic circuit blocks, each associated with a single reset signal. Once the intermediate circuit (29) is produced, the circuit design method includes eliminating unnecessary devices (46) from the intermediate circuit (29) to produce a final logic circuit, and then sizing the devices (48) in the final circuit to complete the design.
摘要翻译：可用于逻辑合成的电路库限于单个动态电路块或逻辑合成块。电路设计方法包括首先定义逻辑合成块（16），然后执行用于要实现的预定逻辑运算的逻辑合成（17）。限制到单个逻辑合成块的逻辑合成步骤产生中间电路设计（29），其必须包括一系列与单个复位信号相关联的动态电路块。一旦产生中间电路（29），电路设计方法包括从中间电路（29）消除不必要的装置（46）以产生最终的逻辑电路，然后对最终电路中的装置（48）进行尺寸调整以完成设计。

84. 发明申请

US20080013388A1 Method and Apparatus for Wordline Redundancy Control of Memory in an Information Handling System 失效
标题翻译：信息处理系统中字节冗余控制的方法与装置
公开(公告)号：US20080013388A1
公开(公告)日：2008-01-17
申请号：US11457507
申请日：2006-07-14
申请人： Toru Asano , Sang H. Dhong , Takaaki Nakazato , Osamu Takahashi
发明人： Toru Asano , Sang H. Dhong , Takaaki Nakazato , Osamu Takahashi
IPC分类号： G11C7/00 , G11C29/00
CPC分类号： G11C29/848
摘要： A memory system including a memory array with redundant wordlines is disclosed. The memory system includes a memory wordline tester that determines if any of the wordlines exhibits a defect. The memory system also includes decoder redundancy logic that efficiently couples to wordline shift logic using a reduced number of control signal lines therebetween. The shift logic shifts defective wordlines to upstream wordlines in the array to bypass the defective wordlines.
摘要翻译：公开了一种包括具有冗余字线的存储器阵列的存储器系统。存储器系统包括存储器字线测试器，其确定任何字线是否存在缺陷。存储器系统还包括使用其间数量减少的控制信号线有效地耦合到字线移位逻辑的解码器冗余逻辑。移位逻辑将有缺陷的字线转移到阵列中的上游字线以绕过有缺陷的字线。

85. 发明申请

US20070147863A1 Image forming apparatus 有权
标题翻译：图像形成装置
公开(公告)号：US20070147863A1
公开(公告)日：2007-06-28
申请号：US11645038
申请日：2006-12-26
申请人： Osamu Takahashi
发明人： Osamu Takahashi
IPC分类号： G03G15/00 , G03G15/01 , G03G15/16
CPC分类号： G03G15/754 , G03G2215/0119 , G03G2215/0158
摘要： An image forming apparatus includes; an image forming unit; an annular belt that moves circularly; a detection unit that detects a state of a surface of the belt; and a tension increase 5 unit that increases a tension of the belt, at a detection position by the detection unit, when detection is performed by the detection unit, as compared with the tension of the belt before detection at the detection position is performed by the detection unit.
摘要翻译：图像形成装置包括：图像形成单元; 循环移动的环形带; 检测所述带的表面的状态的检测单元; 以及张力增加5单元，当检测单元检测到与检测位置的检测前的带张力相比时，由检测单元检测位置增加带张力，检测单元

86. 发明授权

US07194214B2 Patch density measuring apparatus and image forming apparatus 有权
标题翻译：贴片密度测定装置及成像装置
公开(公告)号：US07194214B2
公开(公告)日：2007-03-20
申请号：US11039828
申请日：2005-01-24
申请人： Osamu Takahashi
发明人： Osamu Takahashi
IPC分类号： G03G15/00
CPC分类号： G03G15/5058 , G03G15/5041 , G03G2215/0164
摘要： When a regular reflection light receiving unit is receiving a reflected light in a non-image area where the test patches are not formed, a clamp switch is closed. Then, a first reference voltage generated by a pull-up resistor and a zener diode is corresponded to an electric potential of a terminal of a capacitor on the side of an A/D converter. The capacitor is charged by the difference in electric potential between the first reference voltage and an output voltage from the regular reflection light receiving unit. Next, the clamp switch is opened. After the regular reflection light receiving unit receives the reflected light from an image area where the test patches are formed with this state of things, the output voltage from the regular reflection light receiving unit is changed. The difference in density between the image area and the non-image area can be quantified by the A/D converter.
摘要翻译：当正反射光接收单元在未形成测试片的非图像区域中接收到反射光时，闭合开关。然后，由上拉电阻和齐纳二极管产生的第一参考电压对应于A / D转换器一侧的电容器的端子的电位。电容器由第一参考电压和来自正反射光接收单元的输出电压之间的电位差来充电。接下来，夹紧开关打开。在正常反射光接收单元接收到来自具有这种状态的测试贴片的图像区域的反射光之后，来自正反射光接收单元的输出电压被改变。图像区域和非图像区域之间的密度差可以通过A / D转换器来量化。

87. 发明申请

US20070043895A1 Method and apparatus for row based power control of a microprocessor memory array 审中-公开
标题翻译：微处理器存储器阵列的基于行的功率控制的方法和装置
公开(公告)号：US20070043895A1
公开(公告)日：2007-02-22
申请号：US11204417
申请日：2005-08-16
申请人： Chad Adams , Toru Asano , Sang Dhong , Takaaki Nakazato , Joel Silberman , Osamu Takahashi
发明人： Chad Adams , Toru Asano , Sang Dhong , Takaaki Nakazato , Joel Silberman , Osamu Takahashi
IPC分类号： G06F12/06 , G06F1/00
CPC分类号： G06F1/3203 , G06F1/3237 , G06F1/3243 , G06F1/3275 , G11C8/08 , Y02D10/128 , Y02D10/14 , Y02D10/152
摘要： An apparatus, a method, and a computer program are provided to efficiently use a microprocessor array. Typically, microprocessor arrays can be divided into multiple subarrays. Also, in the conventional arrays, each of the subarrays were engaged when the microprocessor array is used. To alleviate the power consumed by the microprocessor arrays, row selection logic is employed to engage only specific rows of subarrays. Therefore, power consumed by unused subarrys is saved.
摘要翻译：提供了一种装置，方法和计算机程序以有效地使用微处理器阵列。通常，微处理器阵列可以分为多个子阵列。此外，在常规阵列中，当使用微处理器阵列时，每个子阵列被接合。为了减轻微处理器阵列消耗的功率，采用行选择逻辑仅与特定的子阵列相啮合。因此，省去了未使用的亚军消耗的电力。

88. 发明授权

US07170328B2 Scannable latch 失效
标题翻译：可扫描闩锁
公开(公告)号：US07170328B2
公开(公告)日：2007-01-30
申请号：US10982112
申请日：2004-11-05
申请人： Sang Hoo Dhong , Joel A. Silberman , Osamu Takahashi
发明人： Sang Hoo Dhong , Joel A. Silberman , Osamu Takahashi
IPC分类号： H03K3/289 , H03K3/356
CPC分类号： H03K3/356113 , G01R31/318541
摘要： A scannable latch is disclosed. The scannable latch includes a dynamic circuit, two cross-coupled NAND gates coupled to the dynamic circuit, and a pair of stacked transistors coupled to the dynamic circuit. One of the stacked transistors is for receiving data signals, and the other stacked transistors is for receiving scan in signals.
摘要翻译：公开了可扫描的闩锁。可扫描锁存器包括动态电路，耦合到动态电路的两个交叉耦合NAND门和耦合到动态电路的一对堆叠晶体管。堆叠晶体管中的一个用于接收数据信号，而另一个堆叠晶体管用于接收扫描信号。

89. 发明授权

US07168022B2 Transmission control method and system 失效
标题翻译：变速箱控制方法及系统
公开(公告)号：US07168022B2
公开(公告)日：2007-01-23
申请号：US10743635
申请日：2003-12-22
申请人： Motoharu Miyake , Hiroshi Inamura , Taro Ishikawa , Kazuhisa Yokota , Osamu Takahashi
发明人： Motoharu Miyake , Hiroshi Inamura , Taro Ishikawa , Kazuhisa Yokota , Osamu Takahashi
IPC分类号： G08C25/02 , H04L1/18
CPC分类号： H04L1/1883 , H04L1/1809
摘要： A first elapsed time from transmission of a data segment until receipt of an acknowledgement is measured. A probability distribution of the first elapsed time is generated for a client device 50 on the basis of the measured first elapsed time. A second elapsed time from retransmission of a data segment until receipt of an acknowledgement is measured. A probability distribution of the second elapsed time is generated for a client device 50 on the basis of the measured first elapsed time. An estimation is made as to whether an acknowledgment pertains to which data segment on the basis of the generated probability distribution.
摘要翻译：测量从数据段传输到接收到确认之前的第一个经过时间。基于测量的第一经过时间，为客户端设备50生成第一经过时间的概率分布。测量从数据段的重传到接收确认的第二次经过时间。基于所测量的第一经过时间，为客户端设备50生成第二经过时间的概率分布。根据生成的概率分布来估计确认是关于哪个数据段。

90. 发明授权

US07165006B2 Scan chain disable function for power saving 失效
标题翻译：扫描链禁用功能进行省电
公开(公告)号：US07165006B2
公开(公告)日：2007-01-16
申请号：US10976259
申请日：2004-10-28
申请人： Sang Hoo Dhong , Joel Abraham Silberman , Osamu Takahashi , James Douglas Warnock , Dieter Wendel
发明人： Sang Hoo Dhong , Joel Abraham Silberman , Osamu Takahashi , James Douglas Warnock , Dieter Wendel
IPC分类号： G06F19/00
CPC分类号： G06F1/3203 , G06F1/325
摘要： An apparatus, a method and a computer program product are provided for conserving energy during functional mode of a processor by disabling the scan chain. By inserting logic gating into the scan chain it is possible to disable the scan chain during the processor's functional mode. During functional mode the scan out port of the latch bit in a scan chain toggles, which leads to unnecessary energy consumption. By gating scan control signals and the scan out port of a latch bit, the scan chain segment between latch bits can be disconnected. Therefore, the scan control signals can disable the scan chain during functional mode.
摘要翻译：提供了一种装置，方法和计算机程序产品，用于通过禁用扫描链来在处理器的功能模式期间节省能量。通过将逻辑门控插入到扫描链中，可以在处理器的功能模式期间禁用扫描链。在功能模式期间，扫描链中锁存位的扫描输出端口切换，这导致不必要的能量消耗。通过门控扫描控制信号和锁存位的扫描输出端口，可以断开锁存位之间的扫描链段。因此，扫描控制信号可以在功能模式下禁用扫描链。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式