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1. 再颁专利

USRE44969E1 Storage media with benchmark representative of data originally stored thereon 有权
标题翻译：存储介质，其基准代表原始存储在其上的数据
公开(公告)号：USRE44969E1
公开(公告)日：2014-06-24
申请号：US11400762
申请日：2006-04-06
申请人： Eric Ryon Heiser , Robert L. Short , Chad Adams , Ronald F. Hales
发明人： Eric Ryon Heiser , Robert L. Short , Chad Adams , Ronald F. Hales
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28
CPC分类号： G06F21/80 , G11B20/00086 , G11B20/00094 , G11B20/00123 , G11B20/0021 , G11B20/00557 , G11B20/00688 , Y10S707/99953
摘要： Data on a master is read into a master image file, and the master image file is manipulated to include a benchmark comprising tracking and verification information tied to at least a portion of the master image file. Thus, a copied-to storage media as copied from the master image file also includes such benchmark, a data alteration of the master image file causes a mis-match with regard to the benchmark in such master image file, and a data alteration of the copied-to storage media also causes a mis-match with regard to the benchmark in such storage media as copied from such master image file. The benchmark may include a part identifier and a security identifier.
摘要翻译：主机上的数据被读入主映像文件，并且操纵主映像文件以包括绑定到主映像文件的至少一部分的跟踪和验证信息的基准。因此，从主图像文件复制的复制到存储介质也包括这样的基准，主图像文件的数据变更导致与这种主图像文件中的基准的错误匹配，并且数据更改复制到存储介质也会导致与从这样的主映像文件复制的这样的存储介质中的基准测试不匹配。基准可以包括部件标识符和安全标识符。

2. 发明授权

US07860172B2 Self clock generation structure for low power local clock buffering decoder 有权
标题翻译：用于低功耗本地时钟缓冲解码器的自身时钟生成结构
公开(公告)号：US07860172B2
公开(公告)日：2010-12-28
申请号：US10845540
申请日：2004-05-13
申请人： Chad Adams , Toru Asano , Andrew Maust
发明人： Chad Adams , Toru Asano , Andrew Maust
IPC分类号： H04B14/04
CPC分类号： G06F1/32 , G06F1/06
摘要： A k-to-2k decoder is provided. Within the final stage of a k-to-2k decoder is a plurality of word line drivers. These word line drivers utilize clocking signals to fire word lines to a memory array. However, power consumption by clocks has become a serious issue with the increase component density on silicon wafers. To alleviate the problem, signals from the first stage of the k-to-2k decoder provide enablement signals to Local Clock Buffers (LCBs) that allow the word line drivers to fire. The enablement signal reduces the number of active buffers and signals carried to word line drivers, reducing power consumption.
摘要翻译：提供k-to-2k解码器。在k-to-2k解码器的最后阶段是多个字线驱动器。这些字线驱动器利用时钟信号将字线触发到存储器阵列。然而，随着硅晶片的组件密度的增加，时钟功耗成为一个严重的问题。为了减轻这个问题，来自k-2k解码器的第一级的信号向本地时钟缓冲器（LCB）提供允许字线驱动器触发的启动信号。启用信号减少了向字线驱动器传送的有效缓冲器和信号的数量，从而降低了功耗。

3. 发明申请

US20070043895A1 Method and apparatus for row based power control of a microprocessor memory array 审中-公开
标题翻译：微处理器存储器阵列的基于行的功率控制的方法和装置
公开(公告)号：US20070043895A1
公开(公告)日：2007-02-22
申请号：US11204417
申请日：2005-08-16
申请人： Chad Adams , Toru Asano , Sang Dhong , Takaaki Nakazato , Joel Silberman , Osamu Takahashi
发明人： Chad Adams , Toru Asano , Sang Dhong , Takaaki Nakazato , Joel Silberman , Osamu Takahashi
IPC分类号： G06F12/06 , G06F1/00
CPC分类号： G06F1/3203 , G06F1/3237 , G06F1/3243 , G06F1/3275 , G11C8/08 , Y02D10/128 , Y02D10/14 , Y02D10/152
摘要： An apparatus, a method, and a computer program are provided to efficiently use a microprocessor array. Typically, microprocessor arrays can be divided into multiple subarrays. Also, in the conventional arrays, each of the subarrays were engaged when the microprocessor array is used. To alleviate the power consumed by the microprocessor arrays, row selection logic is employed to engage only specific rows of subarrays. Therefore, power consumed by unused subarrys is saved.
摘要翻译：提供了一种装置，方法和计算机程序以有效地使用微处理器阵列。通常，微处理器阵列可以分为多个子阵列。此外，在常规阵列中，当使用微处理器阵列时，每个子阵列被接合。为了减轻微处理器阵列消耗的功率，采用行选择逻辑仅与特定的子阵列相啮合。因此，省去了未使用的亚军消耗的电力。

4. 发明授权

US06718446B1 Storage media with benchmark representative of data originally stored thereon 有权
标题翻译：存储介质，其基准代表原始存储在其上的数据
公开(公告)号：US06718446B1
公开(公告)日：2004-04-06
申请号：US09588149
申请日：2000-06-05
申请人： Eric Ryon Peters , Robert L. Short , Chad Adams , Ronald F. Hales
发明人： Eric Ryon Peters , Robert L. Short , Chad Adams , Ronald F. Hales
IPC分类号： G06F1216
CPC分类号： G06F21/80 , G11B20/00086 , G11B20/00094 , G11B20/00123 , G11B20/0021 , G11B20/00557 , G11B20/00688 , Y10S707/99953
摘要： Data on a master is read into a master image file, and the master image file is manipulated to include a benchmark comprising tracking and verification information tied to at least a portion of the master image file. Thus, a copied-to storage media as copied from the master image file also includes such benchmark, a data alteration of the master image file causes a mis-match with regard to the benchmark in such master image file, and a data alteration of the copied-to storage media also causes a mis-match with regard to the benchmark in such storage media as copied from such master image file. The benchmark may include a part identifier and a security identifier.
摘要翻译：主机上的数据被读入主映像文件，并且操纵主映像文件以包括绑定到主映像文件的至少一部分的跟踪和验证信息的基准。因此，从主图像文件复制的复制到存储介质也包括这样的基准，主图像文件的数据变更导致与这种主图像文件中的基准的错误匹配，并且数据更改复制到存储介质也会导致与从这样的主映像文件复制的这样的存储介质中的基准测试不匹配。基准可以包括部件标识符和安全标识符。

5. 发明授权

US08725622B2 System and method for conducting electronic auctions with multi-parameter optimal bidding 有权
标题翻译：用多参数优化投标进行电子拍卖的系统和方法
公开(公告)号：US08725622B2
公开(公告)日：2014-05-13
申请号：US11982339
申请日：2007-10-31
申请人： Virind S. Gujral , Tim Jackovic , Greg S. Anderson , Dan V. Pedersen , William D. Rupp , Chad Adams
发明人： Virind S. Gujral , Tim Jackovic , Greg S. Anderson , Dan V. Pedersen , William D. Rupp , Chad Adams
IPC分类号： G06Q40/00
CPC分类号： G06Q30/02 , G06Q30/0234 , G06Q30/0235 , G06Q30/0601 , G06Q30/08 , G06Q40/04 , G06Q40/06
摘要： An auction methodology wherein the auction competition among the bidders is generated by allowing each bidder to bid for non-price bid parameters (e.g., lead time, labor rate, contract length, etc.) in addition to the price of the lot on auction. Such a multi-parameter bidding provides the buyer (i.e., the auction requester) with more diverse information when selecting the winning bidder. The buyer and each bidder participating in the electronic auction may receive a real-time feedback of the bidding activity including details on bids placed for price and non-price parameters, which allows each bidder to adjust or modify one or more of its own bids (for price and non-price bid parameters) to effectively compete in the auction. The bidding software nullifies the effect of each bidder's bids for the non-price parameters on that bidder's bid for the price parameter by multiplying the value of the bid for each non-price parameter by the number zero (0) and also locks the bid values initially received for the non-price parameters to avoid affecting their values when lot price is changed during bidding. Such zero-weighting and locking helps the buyer objectively determine the optimal bid for the lot on auction.
摘要翻译：一种拍卖方法，其中投标者之间的拍卖竞争是通过允许每个投标者除了拍卖的拍卖价格之外，还可以出价非价格出价参数（例如，交货时间，劳动力，合同长度等）。这种多参数投标在选择中标者时向买方（即拍卖请求者）提供更多样化的信息。参与电子拍卖的买家和每个投标人可以获得投标活动的实时反馈，包括针对价格和非价格参数的出价的细节，这允许每个投标人调整或修改自己的一个或多个投标（对于价格和非价格出价参数），以有效竞争拍卖。投标软件通过将每个非价格参数的出价值乘以零（0），将价格参数中的每个出价者的出价对该投标人的出价价格参数的出价消除，并锁定出价值最初收到的非价格参数，以避免在招标时更改批次价格时影响其价值。这种零加权和锁定有助于买方客观地确定拍卖地段的最佳出价。

6. 发明授权

US07635352B2 Catheter and introducer needle assembly with needle shield 有权
标题翻译：导管和导针针组合带针罩
公开(公告)号：US07635352B2
公开(公告)日：2009-12-22
申请号：US11138215
申请日：2005-05-27
申请人： Chad Adams
发明人： Chad Adams
IPC分类号： A61M5/178
CPC分类号： A61M25/0618
摘要： An assembly with a needle shield is provided. The needle shield includes a lock for preventing unwanted proximal and distal movement of the needle once the needle has been withdrawn into the needle shield.
摘要翻译：提供具有针护罩的组件。针护罩包括锁，用于防止针已经被抽出到针护罩中时针的不必要的近端和远端移动。

7. 发明申请

US20070053231A1 Flood Mode Implementation for Continuous Bitline Local Evaluation Circuit 失效
标题翻译：连续位线局部评估电路的洪水模式实现
公开(公告)号：US20070053231A1
公开(公告)日：2007-03-08
申请号：US11552791
申请日：2006-10-25
申请人： Chad Adams , Derick Behrends , Ryan Kivimagi
发明人： Chad Adams , Derick Behrends , Ryan Kivimagi
IPC分类号： G11C7/00
CPC分类号： G11C29/50 , G11C11/41
摘要： A method, an apparatus, and a computer program product are provided for flood mode implementation of SRAM cells that employ a continuous bitline local evaluation circuit. Flood mode testing is used to weed out marginal SRAM cells by stressing the SRAM cells. Flood mode is induced by beginning with a normal write operation. After new data values have been forced into the SRAM cells, then the write signal is chopped off. A delay block keeps the wordline signal at the high supply, and the SRAM cells go into flood mode. At this juncture marginal cells can be easily detected and later mapped to redundant cells.
摘要翻译：提供了一种方法，装置和计算机程序产品，用于采用连续位线局部评估电路的SRAM单元的泛洪模式实现。洪水模式测试用于通过强调SRAM单元来清除边缘SRAM单元。通过开始正常的写操作来引发洪泛模式。在新的数据值被强制进入SRAM单元之后，写入信号被切断。延迟块将字线信号保持在高电源，SRAM单元进入泛洪模式。在这个关键点，边缘细胞可以很容易地被检测，并且稍后映射到冗余细胞。

8. 发明申请

US20070044049A1 Apparatus and methods for predicting and/or calibrating memory yields 失效
标题翻译：用于预测和/或校准记忆的装置和方法产生
公开(公告)号：US20070044049A1
公开(公告)日：2007-02-22
申请号：US11207068
申请日：2005-08-18
申请人： Chad Adams , Anthony Aipperspach , George Paulik
发明人： Chad Adams , Anthony Aipperspach , George Paulik
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： An apparatus and methods for predicting and/or for calibrating memory yields due to process defects and/or device variations, including determining a model of a memory cell, identifying a subset of parameters associated with the model, determining and executing a refined model using the parameters, determining a predicted probability the simulated memory cell will be operational based on the simulated operation of the refined model, determining yield prediction information from the predicted probability, and determining the minimum number of repair elements to include in a memory array design to insure a desired yield percentage based on the yield prediction information.
摘要翻译：用于由于过程缺陷和/或设备变化而预测和/或校准存储器的装置和方法，包括确定存储器单元的模型，识别与模型相关联的参数的子集，使用参数，基于精炼模型的模拟操作确定模拟存储器单元将可操作的预测概率，根据预测概率确定收益率预测信息，以及确定修复元素的最小数量以包括在存储器阵列设计中以确保基于产量预测信息的期望产量百分比。

9. 发明申请

US20070041240A1 Random Access Memory With A Plurality Of Symmetrical Memory Cells 失效
标题翻译：具有多个对称存储单元的随机存取存储器
公开(公告)号：US20070041240A1
公开(公告)日：2007-02-22
申请号：US11462380
申请日：2006-08-04
申请人： Chad Adams , Torsten Mahuke , Juergen Pille , Oto Wagner
发明人： Chad Adams , Torsten Mahuke , Juergen Pille , Oto Wagner
IPC分类号： G11C11/00
CPC分类号： G11C11/412 , G11C11/419
摘要： The invention proposes a Random Access Memory (1) with a plurality of symmetrical memory cells (2) which are connected in groups to complementary bit lines (blc, blt), and the complementary bit lines (blc, blt) are coupled through a cross coupled device (31, 32), and the groups of memory cells are connected to complementary global data lines (data_c, data_t) used to provide data to a selected cell of the group of memory cells. The Random Access Memory is characterized in that switches (33, 34) are provided that deactivate the cross coupled device, wherein the switches (33, 34) are driven by the complementary global data lines (data_c, data_t). The invention relates further on to a computer comprising such a Random Access Memory.
摘要翻译：本发明提出一种具有多个对称存储单元（2）的随机存取存储器（1），它们分组连接到互补位线（blc，blt），互补位线（blc，blt）通过交叉耦合设备（31,32），并且存储器单元组被连接到用于向存储器单元组的所选单元提供数据的互补全局数据线（data_c，data_t）。随机存取存储器的特征在于提供了使交叉耦合器件去激活的开关（33,34），其中开关（33,34）由互补的全局数据线（data_c，data_t）驱动。本发明进一步涉及包括这种随机存取存储器的计算机。

10. 发明申请

US20060270991A1 Catheter and introducer needle assembly with needle shield 有权
公开(公告)号：US20060270991A1
公开(公告)日：2006-11-30
申请号：US11138215
申请日：2005-05-27
申请人： Chad Adams
发明人： Chad Adams
IPC分类号： A61M5/178
CPC分类号： A61M25/0618
摘要： An assembly with a needle shield is provided. The needle shield includes a lock for preventing unwanted proximal and distal movement of the needle once the needle has been withdrawn into the needle shield.

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