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81. 发明申请

US20130248998A1 SEMICONDUCTOR DEVICE 审中-公开
标题翻译：半导体器件
公开(公告)号：US20130248998A1
公开(公告)日：2013-09-26
申请号：US13619336
申请日：2012-09-14
申请人： Shinichiro Misu , Tsuyoshi Ota , Tatsuya Nishiwaki , Takeshi Uchihara , Yusuke Kawaguchi
发明人： Shinichiro Misu , Tsuyoshi Ota , Tatsuya Nishiwaki , Takeshi Uchihara , Yusuke Kawaguchi
IPC分类号： H01L29/78
CPC分类号： H01L29/7801 , H01L29/0623 , H01L29/0634 , H01L29/0878 , H01L29/407 , H01L29/4175 , H01L29/42368 , H01L29/42376 , H01L29/66704 , H01L29/66734 , H01L29/66787 , H01L29/7813 , H01L29/7825 , H01L29/872
摘要： According to one embodiment, a semiconductor device includes, a drain, source, base and drift regions, a gate electrode, a gate insulating film, a first semiconductor region, a drain electrode, and a source electrode. The drain region has a first portion, and a second portion having a surface extending in a first direction which is vertical to a main surface of the first portion. The source region extends in a second direction which is parallel to the second portion, and is provided to be spaced from the drain region. The gate electrode extends in the first direction and a third direction which is vertical to the first direction and the second direction, and passes through the base region in the third direction. The first semiconductor region is provided between the gate insulating film and the drain region, and has a lower impurity concentration than the drift region.
摘要翻译：根据一个实施例，半导体器件包括漏极，源极，基极和漂移区，栅电极，栅绝缘膜，第一半导体区，漏电极和源电极。漏区具有第一部分，第二部分具有沿垂直于第一部分的主表面的第一方向延伸的表面。源极区域在与第二部分平行的第二方向上延伸，并且设置成与漏极区域间隔开。栅极电极在第一方向和与第一方向和第二方向垂直的第三方向上延伸，并且在第三方向上穿过基极区域。第一半导体区域设置在栅极绝缘膜和漏极区之间，并且具有比漂移区更低的杂质浓度。

82. 发明申请

US20070131967A1 Self-standing GaN single crystal substrate, method of making same, and method of making a nitride semiconductor device 审中-公开
标题翻译：自立GaN单晶衬底，其制造方法以及制造氮化物半导体器件的方法
公开(公告)号：US20070131967A1
公开(公告)日：2007-06-14
申请号：US11413115
申请日：2006-04-28
申请人： Yusuke Kawaguchi , Takeshi Meguro
发明人： Yusuke Kawaguchi , Takeshi Meguro
IPC分类号： H01L31/00
CPC分类号： H01L21/02008
摘要： A self-standing gallium nitride-based semiconductor single crystal substrate has a surface (Ga-face) mirror-polished, and a rear surface (N-face) having an arithmetic mean roughness Ra of 1 micrometer or more and 10 micrometers or less. A nitride semiconductor device is fabricated such that, before the gallium nitride-based semiconductor single crystal substrate is attached to a substrate holder of a vapor phase growth apparatus, the substrate is adjusted such that its rear surface (N-face) has a arithmetic mean roughness Ra to be in face-to-face contact with the substrate holder.
摘要翻译：自立式氮化镓系半导体单晶基板具有镜面抛光的表面（Ga面）和具有1微米以上且10微米以下的算术平均粗糙度Ra的后表面（N面）。制造氮化物半导体器件，使得在氮化镓基半导体单晶衬底附着到气相生长装置的衬底保持器之前，调节衬底，使得其背面（N面）具有算术平均值粗糙度Ra与衬底保持器面对面接触。

83. 发明授权

US08502309B2 Semiconductor device including field effect transistor for use as a high-speed switching device and a power device 有权
标题翻译：包括用作高速开关装置的场效应晶体管和功率器件的半导体装置
公开(公告)号：US08502309B2
公开(公告)日：2013-08-06
申请号：US12645072
申请日：2009-12-22
申请人： Yusuke Kawaguchi , Norio Yasuhara , Tomoko Matsudai , Kenichi Matsushita
发明人： Yusuke Kawaguchi , Norio Yasuhara , Tomoko Matsudai , Kenichi Matsushita
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/119
CPC分类号： H01L29/0847 , H01L29/0653 , H01L29/0878 , H01L29/1095 , H01L29/42368 , H01L29/66659 , H01L29/66681 , H01L29/7816 , H01L29/7835
摘要： A body layer of a first conductivity type is formed on a semiconductor substrate, and a source layer of a second conductivity type is formed in a surface region of the body layer. An offset layer of the second conductivity type is formed on the semiconductor substrate, and a drain layer of the second conductivity type is formed in a surface region of the offset layer. An insulating film is embedded in a trench formed in the surface region of the offset layer between the source layer and the drain layer. A gate insulating film is formed on the body layer and the offset layer between the source layer and the insulating film. A gate electrode is formed on the gate insulating film. A first peak of an impurity concentration profile in the offset layer is formed at a position deeper than the insulating film.
摘要翻译：在半导体衬底上形成第一导电类型的主体层，并且在主体层的表面区域中形成第二导电类型的源极层。第二导电类型的偏移层形成在半导体衬底上，并且第二导电类型的漏极层形成在偏移层的表面区域中。绝缘膜嵌入形成在源极层和漏极层之间的偏移层的表面区域中的沟槽中。在主体层和源极层与绝缘膜之间的偏移层上形成栅极绝缘膜。在栅极绝缘膜上形成栅电极。偏移层中的杂质浓度分布的第一峰形成在比绝缘膜更深的位置。

84. 发明申请

US20120061747A1 SEMICONDUCTOR DEVICE 失效
标题翻译：半导体器件
公开(公告)号：US20120061747A1
公开(公告)日：2012-03-15
申请号：US13052917
申请日：2011-03-21
申请人： Takeshi UCHIHARA , Yusuke Kawaguchi , Keiko Kawamura , Hitoshi Shinohara , Yosefu Fujiki
发明人： Takeshi UCHIHARA , Yusuke Kawaguchi , Keiko Kawamura , Hitoshi Shinohara , Yosefu Fujiki
IPC分类号： H01L29/78
CPC分类号： H01L29/7813 , H01L21/823487 , H01L27/088 , H01L29/0626 , H01L29/0696 , H01L29/0886 , H01L29/1095 , H01L29/4238 , H01L29/66734 , H01L29/7808
摘要： According to one embodiment, a semiconductor device includes a drift region of a first conductivity type, a base region of a second conductivity type, a source region of the first conductivity type, a gate electrode in a trench shape, a contact region of the second conductivity type, a drain electrode, and a source electrode. The drift region is selectively provided in a drain layer of the first conductivity type from a surface of the drain layer to an inside of the drain layer. The base region is selectively provided in the drift region from a surface of the drift region to an inside of the drift region. The source region is selectively provided in the base region from a surface of the base region to an inside of the base region. The gate electrode penetrates from a part of the source region through the base region adjacent to the part of the source region to reach a part of the drift region in a direction substantially parallel to a major surface of the drain layer. The contact region is selectively provided on the surface of the drift region. The contact region contains an impurity having a concentration higher than an impurity concentration of the base region. The drain electrode is connected to the drain layer. The source electrode is connected to the source region and the contact region. The contact region extends from a side of the drain layer toward the drift region and does not contact the drain layer.
摘要翻译：根据一个实施例，半导体器件包括第一导电类型的漂移区域，第二导电类型的基极区域，第一导电类型的源极区域，沟槽形状的栅电极，第二导电类型的接触区域导电类型，漏电极和源电极。漂移区选择性地设置在从漏层的表面到漏层的内部的第一导电类型的漏极层中。基极区域选择性地设置在漂移区域中，从漂移区域的表面到漂移区域的内部。源极区域从基极区域的表面到基极区域的内部选择性地设置在基极区域中。栅极电极从源极区域的一部分穿过与源极区域相邻的基极区域，以在与漏极层的主表面基本平行的方向上到达漂移区域的一部分。接触区选择性地设置在漂移区的表面上。接触区域含有浓度高于碱性区域的杂质浓度的杂质。漏电极连接到漏极层。源电极连接到源极区域和接触区域。接触区域从漏极层的侧面朝向漂移区域延伸，并且不接触漏极层。

85. 发明授权

US07998849B2 Semiconductor device used as high-speed switching device and power device 有权
标题翻译：半导体器件用作高速开关器件和功率器件
公开(公告)号：US07998849B2
公开(公告)日：2011-08-16
申请号：US12716352
申请日：2010-03-03
申请人： Tomoko Matsudai , Norio Yasuhara , Yusuke Kawaguchi , Kenichi Matsushita
发明人： Tomoko Matsudai , Norio Yasuhara , Yusuke Kawaguchi , Kenichi Matsushita
IPC分类号： H01L21/336
CPC分类号： H01L29/1045 , H01L21/26586 , H01L29/1083 , H01L29/1087 , H01L29/66659 , H01L29/7835 , H01L29/7838
摘要： A low resistance layer is formed on a semiconductor substrate, and a high resistance layer formed on the low resistance layer. A source region of a first conductivity type is formed on a surface region of the high resistance layer. A drain region of the first conductivity type is formed at a distance from the source region. A first resurf region of the first conductivity type is formed in a surface region of the high resistance layer between the source region and the drain region. A channel region of a second conductivity type is formed between the source region and the first resurf region. A gate insulating film is formed on the channel region, and a gate electrode formed on the gate insulating film. An impurity concentration in the channel region under the gate electrode gradually lowers from the source region toward the first resurf region.
摘要翻译：在半导体衬底上形成低电阻层，形成在低电阻层上的高电阻层。第一导电类型的源区形成在高电阻层的表面区域上。第一导电类型的漏极区域形成在与源极区域一定距离处。在源极区域和漏极区域之间的高电阻层的表面区域中形成第一导电类型的第一再结晶区域。在源极区域和第一再结晶区域之间形成第二导电类型的沟道区域。栅极绝缘膜形成在沟道区上，栅极形成在栅极绝缘膜上。栅电极下方的沟道区域中的杂质浓度从源极区域朝向第一再结晶区域逐渐降低。

86. 发明授权

US07646059B2 Semiconductor device including field effect transistor for use as a high-speed switching device and a power device 失效
标题翻译：包括用作高速开关装置的场效应晶体管和功率器件的半导体装置
公开(公告)号：US07646059B2
公开(公告)日：2010-01-12
申请号：US11501715
申请日：2006-08-10
申请人： Yusuke Kawaguchi , Norio Yasuhara , Tomoko Matsudai , Kenichi Matsushita
发明人： Yusuke Kawaguchi , Norio Yasuhara , Tomoko Matsudai , Kenichi Matsushita
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/119
CPC分类号： H01L29/0847 , H01L29/0653 , H01L29/0878 , H01L29/1095 , H01L29/42368 , H01L29/66659 , H01L29/66681 , H01L29/7816 , H01L29/7835
摘要： A body layer of a first conductivity type is formed on a semiconductor substrate, and a source layer of a second conductivity type is formed in a surface region of the body layer. An offset layer of the second conductivity type is formed on the semiconductor substrate, and a drain layer of the second conductivity type is formed in a surface region of the offset layer. An insulating film is embedded in a trench formed in the surface region of the offset layer between the source layer and the drain layer. A gate insulating film is formed on the body layer and the offset layer between the source layer and the insulating film. A gate electrode is formed on the gate insulating film. A first peak of an impurity concentration profile in the offset layer is formed at a position deeper than the insulating film.
摘要翻译：在半导体衬底上形成第一导电类型的主体层，并且在主体层的表面区域中形成第二导电类型的源极层。第二导电类型的偏移层形成在半导体衬底上，并且第二导电类型的漏极层形成在偏移层的表面区域中。绝缘膜嵌入形成在源极层和漏极层之间的偏移层的表面区域中的沟槽中。在主体层和源极层与绝缘膜之间的偏移层上形成栅极绝缘膜。在栅极绝缘膜上形成栅电极。偏移层中的杂质浓度分布的第一峰形成在比绝缘膜更深的位置。

87. 发明申请

US20070040216A1 Semiconductor device used as high-speed switching device and power device 失效
标题翻译：半导体器件用作高速开关器件和功率器件
公开(公告)号：US20070040216A1
公开(公告)日：2007-02-22
申请号：US11505337
申请日：2006-08-17
申请人： Tomoko Matsudai , Norio Yasuhara , Yusuke Kawaguchi , Kenichi Matsushita
发明人： Tomoko Matsudai , Norio Yasuhara , Yusuke Kawaguchi , Kenichi Matsushita
IPC分类号： H01L29/76
CPC分类号： H01L29/1045 , H01L21/26586 , H01L29/1083 , H01L29/1087 , H01L29/66659 , H01L29/7835 , H01L29/7838
摘要： A low resistance layer is formed on a semiconductor substrate, and a high resistance layer formed on the low resistance layer. A source region of a first conductivity type is formed on a surface region of the high resistance layer. A drain region of the first conductivity type is formed at a distance from the source region. A first resurf region of the first conductivity type is formed in a surface region of the high resistance layer between the source region and the drain region. A channel region of a second conductivity type is formed between the source region and the first resurf region. A gate insulating film is formed on the channel region, and a gate electrode formed on the gate insulating film. An impurity concentration in the channel region under the gate electrode gradually lowers from the source region toward the first resurf region.
摘要翻译：在半导体衬底上形成低电阻层，形成在低电阻层上的高电阻层。第一导电类型的源区形成在高电阻层的表面区域上。第一导电类型的漏极区域形成在与源极区域一定距离处。在源极区域和漏极区域之间的高电阻层的表面区域中形成第一导电类型的第一再结晶区域。在源极区域和第一再结晶区域之间形成第二导电类型的沟道区域。栅极绝缘膜形成在沟道区上，栅极形成在栅极绝缘膜上。栅电极下方的沟道区域中的杂质浓度从源极区域朝向第一再结晶区域逐渐降低。

88. 发明授权

US08395204B2 Power semiconductor device 有权
标题翻译：功率半导体器件
公开(公告)号：US08395204B2
公开(公告)日：2013-03-12
申请号：US13233993
申请日：2011-09-15
申请人： Yusuke Kawaguchi
发明人： Yusuke Kawaguchi
IPC分类号： H01L29/788
CPC分类号： H01L29/7813 , H01L29/0626 , H01L29/0696 , H01L29/407 , H01L29/4236 , H01L29/42368 , H01L29/4238 , H01L29/7805 , H01L29/7808
摘要： According to one embodiment, a semiconductor device, includes an element unit including a vertical-type MOSFET, the vertical-type MOSFET in including a first semiconductor layer, a second semiconductor layer, a third semiconductor layer, a fourth semiconductor layer, a fifth semiconductor layer sequentially stacked in order, an impurity concentration of the second semiconductor layer being lower than the first semiconductor layer, an insulator covering inner surfaces of a plurality of trenches, the adjacent trenches being provided with a first interval in between, and a diode unit including basically with the units of the element unit, the adjacent trenches being provided with a second interval in between, the second interval being larger than the first interval.
摘要翻译：根据一个实施例，半导体器件包括包括垂直型MOSFET的元件单元，包括第一半导体层的垂直型MOSFET，第二半导体层，第三半导体层，第四半导体层，第五半导体层层，所述第二半导体层的杂质浓度低于所述第一半导体层，绝缘体覆盖多个沟槽的内表面，所述相邻沟槽之间设置有第一间隔，二极管单元包括：基本上与元件单元的单元相邻，相邻沟槽之间设置有第二间隔，第二间隔大于第一间隔。

89. 发明申请

US20100096696A1 SEMICONDUCTOR DEVICE INCLUDING FIELD EFFECT TRANSISTOR FOR USE AS A HIGH-SPEED SWITCHING DEVICE AND A POWER DEVICE 有权
标题翻译：包括用作高速开关器件和功率器件的场效应晶体管的半导体器件
公开(公告)号：US20100096696A1
公开(公告)日：2010-04-22
申请号：US12645072
申请日：2009-12-22
申请人： Yusuke Kawaguchi , Norio Yasuhara , Tomoko Matsudai , Kenichi Matsushita
发明人： Yusuke Kawaguchi , Norio Yasuhara , Tomoko Matsudai , Kenichi Matsushita
IPC分类号： H01L29/78
CPC分类号： H01L29/0847 , H01L29/0653 , H01L29/0878 , H01L29/1095 , H01L29/42368 , H01L29/66659 , H01L29/66681 , H01L29/7816 , H01L29/7835
摘要： A body layer of a first conductivity type is formed on a semiconductor substrate, and a source layer of a second conductivity type is formed in a surface region of the body layer. An offset layer of the second conductivity type is formed on the semiconductor substrate, and a drain layer of the second conductivity type is formed in a surface region of the offset layer. An insulating film is embedded in a trench formed in the surface region of the offset layer between the source layer and the drain layer. A gate insulating film is formed on the body layer and the offset layer between the source layer and the insulating film. A gate electrode is formed on the gate insulating film. A first peak of an impurity concentration profile in the offset layer is formed at a position deeper than the insulating film.
摘要翻译：在半导体衬底上形成第一导电类型的主体层，并且在主体层的表面区域中形成第二导电类型的源极层。第二导电类型的偏移层形成在半导体衬底上，并且第二导电类型的漏极层形成在偏移层的表面区域中。绝缘膜嵌入形成在源极层和漏极层之间的偏移层的表面区域中的沟槽中。在主体层和源极层与绝缘膜之间的偏移层上形成栅极绝缘膜。在栅极绝缘膜上形成栅电极。偏移层中的杂质浓度分布的第一峰形成在比绝缘膜更深的位置。

90. 发明授权

US07692242B2 Semiconductor device used as high-speed switching device and power device 失效
标题翻译：半导体器件用作高速开关器件和功率器件
公开(公告)号：US07692242B2
公开(公告)日：2010-04-06
申请号：US11505337
申请日：2006-08-17
申请人： Tomoko Matsudai , Norio Yasuhara , Yusuke Kawaguchi , Kenichi Matsushita
发明人： Tomoko Matsudai , Norio Yasuhara , Yusuke Kawaguchi , Kenichi Matsushita
IPC分类号： H01L29/04 , H01L29/06
CPC分类号： H01L29/1045 , H01L21/26586 , H01L29/1083 , H01L29/1087 , H01L29/66659 , H01L29/7835 , H01L29/7838
摘要： A low resistance layer is formed on a semiconductor substrate, and a high resistance layer formed on the low resistance layer. A source region of a first conductivity type is formed on a surface region of the high resistance layer. A drain region of the first conductivity type is formed at a distance from the source region. A first resurf region of the first conductivity type is formed in a surface region of the high resistance layer between the source region and the drain region. A channel region of a second conductivity type is formed between the source region and the first resurf region. A gate insulating film is formed on the channel region, and a gate electrode formed on the gate insulating film. An impurity concentration in the channel region under the gate electrode gradually lowers from the source region toward the first resurf region.
摘要翻译：在半导体衬底上形成低电阻层，形成在低电阻层上的高电阻层。第一导电类型的源区形成在高电阻层的表面区域上。第一导电类型的漏极区域形成在与源极区域一定距离处。在源极区域和漏极区域之间的高电阻层的表面区域中形成第一导电类型的第一再结晶区域。在源极区域和第一再结晶区域之间形成第二导电类型的沟道区域。栅极绝缘膜形成在沟道区上，栅极形成在栅极绝缘膜上。栅电极下方的沟道区域中的杂质浓度从源极区域朝向第一再结晶区域逐渐降低。

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