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81. 发明授权

US08030706B2 Power semiconductor device 失效
标题翻译：功率半导体器件
公开(公告)号：US08030706B2
公开(公告)日：2011-10-04
申请号：US12540192
申请日：2009-08-12
申请人： Miho Watanabe , Masaru Izumisawa , Yasuto Sumi , Hiroshi Ohta , Wataru Sekine , Wataru Saito , Syotaro Ono , Nana Hatano
发明人： Miho Watanabe , Masaru Izumisawa , Yasuto Sumi , Hiroshi Ohta , Wataru Sekine , Wataru Saito , Syotaro Ono , Nana Hatano
IPC分类号： H01L29/66
CPC分类号： H01L29/7811 , H01L29/0634 , H01L29/1095 , H01L29/7802
摘要： A semiconductor device according to an embodiment of the present invention includes a device part and a terminal part. The device includes a first semiconductor layer, and second and third semiconductor layers formed on the first semiconductor layer, and alternately arranged along a direction parallel to a surface of the first semiconductor layer, wherein the device part is provided with a first region and a second region, each of which includes at least one of the second semiconductor layers and at least one of the third semiconductor layers, and with regard to a difference value ΔN (=NA−NB) obtained by subtracting an impurity amount NB per unit length of each of the third semiconductor layers from an impurity amount NA per unit length of each of the second semiconductor layers, a difference value ΔNC1 which is the difference value ΔN in the first region of the device part, a difference value ΔNC2 which is the difference value ΔN in the second region of the device part, and a difference value ΔNT which is the difference value ΔN in the terminal part satisfy a relationship of ΔNC1>ΔNT>ΔNC2.
摘要翻译：根据本发明实施例的半导体器件包括器件部分和端子部分。该器件包括第一半导体层，以及形成在第一半导体层上的第二和第三半导体层，并且沿着与第一半导体层的表面平行的方向交替布置，其中器件部分设置有第一区域和第二半导体层区域，其中每一个包括第二半导体层和至少一个第三半导体层中的至少一个，并且关于通过从每单位长度减去杂质量NB获得的差值Dgr; N（= NA-NB）从每个第二半导体层的每单位长度的杂质量NA中的每个第三半导体层的差分值＆Dgr; NC1，其是器件部分的第一区域中的差值＆Dgr; N，差值＆Dgr ;作为装置部分的第二区域中的差值Dgr; N的NC2，作为终端部分中的差值Dgr; N的差值＆Dgr; NT满足关系的＆Dgr; NC1>＆Dgr; NT>＆Dgr; NC2。

82. 发明申请

US20110215418A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20110215418A1
公开(公告)日：2011-09-08
申请号：US13029925
申请日：2011-02-17
申请人： Wataru SAITO , Syotaro Ono , Munehisa Yabuzaki , Shunji Taniuchi , Miho Watanabe
发明人： Wataru SAITO , Syotaro Ono , Munehisa Yabuzaki , Shunji Taniuchi , Miho Watanabe
IPC分类号： H01L27/07 , H01L29/72
CPC分类号： H01L27/07 , H01L29/72
摘要： According to one embodiment, a semiconductor device includes a first semiconductor region of a first conductivity type, a second semiconductor region of the first conductivity type, a first main electrode, a third semiconductor region of a second conductivity type, a second main electrode, and a plurality of embedded semiconductor regions of the second conductivity type. The second semiconductor region is formed on a first major surface of the first semiconductor region. The first main electrode is formed on a face side opposite to the first major surface of the first semiconductor region. The third semiconductor region is formed on a second major surface of the second semiconductor region on a side opposite to the first semiconductor region. The second main electrode is formed to bond to the third semiconductor region. The embedded semiconductor regions are provided in a termination region. A distance between the embedded semiconductor region and the second major surface along a direction from the second major surface toward the first major surface becomes longer toward outside from the device region.
摘要翻译：根据一个实施例，半导体器件包括第一导电类型的第一半导体区域，第一导电类型的第二半导体区域，第一主电极，第二导电类型的第三半导体区域，第二主电极和多个第二导电类型的嵌入式半导体区域。第二半导体区域形成在第一半导体区域的第一主表面上。第一主电极形成在与第一半导体区域的第一主表面相对的正面上。第三半导体区域形成在第二半导体区域的与第一半导体区域相对的一侧的第二主表面上。第二主电极形成为结合到第三半导体区域。嵌入式半导体区域设置在终端区域中。沿着从第二主表面朝向第一主表面的方向在嵌入式半导体区域和第二主表面之间的距离从器件区域向外部变长。

83. 发明授权

US07759733B2 Power semiconductor device and method for producing the same 有权
标题翻译：功率半导体器件及其制造方法
公开(公告)号：US07759733B2
公开(公告)日：2010-07-20
申请号：US12055585
申请日：2008-03-26
申请人： Syotaro Ono , Wataru Saito
发明人： Syotaro Ono , Wataru Saito
IPC分类号： H01L29/76
CPC分类号： H01L29/7802 , H01L29/0634 , H01L29/0878 , H01L29/1095 , H01L29/66712
摘要： A power semiconductor device includes: a first semiconductor substrate; a second semiconductor layer; a plurality of third semiconductor pillar regions and a plurality of fourth semiconductor pillar regions that are provided in an upper layer of the second semiconductor layer and alternatively arranged along a direction parallel to an upper surface of the first semiconductor substrate; a first main electrode; and a second main electrode. A concentration of first-conductivity-type impurity in a connective portion between the second semiconductor layer and the third semiconductor pillar regions is lower than concentrations of first-conductivity-type impurity in portions of both sides of the connective portion in a direction from the second semiconductor layer to the third semiconductor pillar regions.
摘要翻译：功率半导体器件包括：第一半导体衬底; 第二半导体层; 多个第三半导体柱区域和多个第四半导体柱区域，其设置在所述第二半导体层的上层中，并且沿着与所述第一半导体衬底的上表面平行的方向交替布置; 第一主电极; 和第二主电极。在第二半导体层和第三半导体柱区域之间的连接部分中的第一导电型杂质的浓度低于第二导电类型杂质在连接部分的两侧部分中的浓度半导体层到第三半导体柱区域。

84. 发明授权

US07622771B2 Semiconductor apparatus 失效
标题翻译：半导体装置
公开(公告)号：US07622771B2
公开(公告)日：2009-11-24
申请号：US12123072
申请日：2008-05-19
申请人： Syotaro Ono , Wataru Saito , Masakatsu Takashita , Yasuto Sumi , Masaru Izumisawa , Hiroshi Ohta , Wataru Sekine
发明人： Syotaro Ono , Wataru Saito , Masakatsu Takashita , Yasuto Sumi , Masaru Izumisawa , Hiroshi Ohta , Wataru Sekine
IPC分类号： H01L31/119 , H01L21/336
CPC分类号： H01L29/7811 , H01L29/0634 , H01L29/0638 , H01L29/0878 , H01L29/7395 , H01L29/861 , H01L29/868 , H01L29/872
摘要： A semiconductor apparatus includes a first semiconductor layer, a second semiconductor layer provided on a major surface of the first semiconductor layer, a third semiconductor layer provided on the major surface and being adjacent to the second semiconductor layer, a termination semiconductor layer provided on the major surface of the first semiconductor layer in a termination region outside the device region, a channel stop layer, and a channel stop electrode. The channel stop layer is provided in contact with the termination semiconductor layer on the major surface of the first semiconductor layer in an outermost peripheral portion outside the termination semiconductor layer and has a higher impurity concentration than the termination semiconductor layer. The channel stop electrode is provided on at least part of a surface of the channel stop layer and projects toward the termination semiconductor layer beyond at least a superficial portion of the channel stop layer.
摘要翻译：半导体装置包括第一半导体层，设置在第一半导体层的主表面上的第二半导体层，设置在主表面上并与第二半导体层相邻的第三半导体层，设置在主体上的端接半导体层在器件区域外的终端区域中的第一半导体层的表面，沟道阻挡层和沟道停止电极。沟道阻挡层设置成与终端半导体层外部的最外周部分中的第一半导体层的主表面上的端接半导体层接触，并且具有比端接半导体层更高的杂质浓度。通道阻挡电极设置在通道阻挡层的表面的至少一部分上，并且朝向端子半导体层突出超过通道阻挡层的至少表面部分。

85. 发明申请

US20080246079A1 POWER SEMICONDUCTOR DEVICE 有权
标题翻译：功率半导体器件
公开(公告)号：US20080246079A1
公开(公告)日：2008-10-09
申请号：US12050415
申请日：2008-03-18
申请人： Wataru Saito , Syotaro Ono , Masakatsu Takashita , Yauto Sumi , Masaru Izumisawa , Wataru Sekine , Hiroshi Ohta , Shoichiro Kurushima
发明人： Wataru Saito , Syotaro Ono , Masakatsu Takashita , Yauto Sumi , Masaru Izumisawa , Wataru Sekine , Hiroshi Ohta , Shoichiro Kurushima
IPC分类号： H01L29/00
CPC分类号： H01L29/7802 , H01L29/0634 , H01L29/0878 , H01L29/1095
摘要： A power semiconductor device includes: a first semiconductor layer; a second semiconductor layer and a third semiconductor layer provided in an upper portion of the first semiconductor layer and alternately arranged parallel to an upper surface of the first semiconductor layer; a plurality of fourth semiconductor layers provided on the third semiconductor layer; a fifth semiconductor layer selectively formed in an upper surface of each of the fourth semiconductor layers; a control electrode; a gate insulating film; a first main electrode provided on a lower surface of the first semiconductor layer; and a second main electrode provided on the fourth and the fifth semiconductor layers. Sum of the amount of impurities in the second semiconductor layer and the amount of impurities in the third semiconductor layer at an end on the second main electrode side of the second semiconductor layer and the third semiconductor layer is smaller than the sum at a center of the second semiconductor layer and the third semiconductor layer in the direction from the first main electrode to the second main electrode.
摘要翻译：功率半导体器件包括：第一半导体层; 第二半导体层和第三半导体层，设置在所述第一半导体层的上部并且交替地平行于所述第一半导体层的上表面布置; 设置在所述第三半导体层上的多个第四半导体层; 选择性地形成在每个第四半导体层的上表面中的第五半导体层; 控制电极; 栅极绝缘膜; 设置在所述第一半导体层的下表面上的第一主电极; 以及设置在第四和第五半导体层上的第二主电极。第二半导体层中的杂质量和第二半导体层的第二主电极侧端部的第三半导体层中的杂质量的和小于第二半导体层的第二主电极侧的和第二半导体层和第三半导体层在从第一主电极到第二主电极的方向上。

86. 发明申请

US20070272977A1 POWER SEMICONDUCTOR DEVICE 失效
标题翻译：功率半导体器件
公开(公告)号：US20070272977A1
公开(公告)日：2007-11-29
申请号：US11680912
申请日：2007-03-01
申请人： Wataru Saito , Syotaro Ono , Masakatsu Takashita , Yasuto Sumi , Masaru Izumisawa , Hiroshi Ohta
发明人： Wataru Saito , Syotaro Ono , Masakatsu Takashita , Yasuto Sumi , Masaru Izumisawa , Hiroshi Ohta
IPC分类号： H01L29/78
CPC分类号： H01L29/7811 , H01L29/0634 , H01L29/0696 , H01L29/0878 , H01L29/1095 , H01L29/66712 , H01L2924/0002 , H01L2924/00
摘要： A power semiconductor device includes: a first semiconductor layer of a first conductivity type; a second semiconductor layer of the first conductivity type and a third semiconductor layer of a second conductivity type formed on the first semiconductor layer and alternately arranged along at least one direction parallel to a surface of the first semiconductor layer; a first main electrode; a fourth semiconductor layer of the second conductivity type selectively formed in a surface of the second semiconductor layer and a surface of the third semiconductor layer; a fifth semiconductor layer of the first conductivity type selectively formed in a surface of the fourth semiconductor layer; a second main electrode; and a control electrode. At least one of the second and the third semiconductor layers has a dopant concentration profile along the one direction, the dopant concentration profile having a local minimum at a position except both ends thereof.
摘要翻译：功率半导体器件包括：第一导电类型的第一半导体层; 第一导电类型的第二半导体层和形成在第一半导体层上的第二导电类型的第三半导体层，并且沿着平行于第一半导体层的表面的至少一个方向交替布置; 第一主电极; 选择性地形成在第二半导体层的表面和第三半导体层的表面上的第二导电类型的第四半导体层; 选择性地形成在第四半导体层的表面中的第一导电类型的第五半导体层; 第二主电极; 和控制电极。第二和第三半导体层中的至少一个具有沿着一个方向的掺杂剂浓度分布，掺杂剂浓度分布在其两端以外的位置处具有局部最小值。

87. 发明申请

US20060081920A1 Semiconductor device and method of manufacturing the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US20060081920A1
公开(公告)日：2006-04-20
申请号：US11245204
申请日：2005-10-07
申请人： Kazutoshi Nakamura , Syotaro Ono
发明人： Kazutoshi Nakamura , Syotaro Ono
IPC分类号： H01L21/336 , H01L29/94
CPC分类号： H01L29/7813 , H01L29/4236 , H01L29/42372 , H01L29/42376 , H01L29/4933 , H01L29/66719 , H01L29/66734
摘要： A semiconductor device includes: a semiconductor substrate of the first-type; a semiconductor region of the first-type formed on the substrate; a gate electrode a part of which is present within a trench selectively formed in part of the semiconductor region, and an extended top-end to have a wide width via a stepped-portion; a gate insulating-film formed between the trench and the gate electrode along a wall surface of the trench; a base layer of the second-type on the region via the film to enclose a side-wall except a bottom of the trench; a source region of the first-type adjacent to the film outside the trench in the vicinity of a top surface of the base layer; and an insulating-film formed partially between a bottom-surface of the top-end and a top-surface of the source region and formed to have a thickness larger than that of the gate insulating-film within the trench.
摘要翻译：半导体器件包括：第一类型的半导体衬底; 在基板上形成第一类型的半导体区域; 栅极电极，其一部分存在于在半导体区域的一部分中选择性地形成的沟槽中，并且延伸的顶端经由阶梯部分具有宽的宽度; 栅沟绝缘膜，沿着沟槽的壁表面形成在沟槽和栅电极之间; 经由膜在该区域上的第二类型的基底层以包围沟槽底部以外的侧壁; 所述第一类型的源极区域在所述基底层的顶表面附近与所述沟槽外部的膜相邻; 以及部分地形成在顶部的底表面和源极区的顶表面之间并且形成为具有比沟槽内的栅极绝缘膜的厚度大的厚度的绝缘膜。

88. 发明授权

US09093474B2 Electric power semiconductor device and manufacturing method of the same 有权
标题翻译：电力半导体器件及其制造方法相同
公开(公告)号：US09093474B2
公开(公告)日：2015-07-28
申请号：US13600616
申请日：2012-08-31
申请人： Wataru Saito , Syotaro Ono , Toshiyuki Naka , Shunji Taniuchi , Hiroaki Yamashita
发明人： Wataru Saito , Syotaro Ono , Toshiyuki Naka , Shunji Taniuchi , Hiroaki Yamashita
IPC分类号： H01L29/78 , H01L29/66 , H01L29/06 , H01L29/08 , H01L29/10
CPC分类号： H01L29/66712 , H01L29/0634 , H01L29/0653 , H01L29/0878 , H01L29/1095 , H01L29/66719 , H01L29/7802 , H01L29/7811
摘要： A manufacturing method of an electric power semiconductor device includes following processes. A plurality of first second conductivity type impurity implantation layers are formed in a surface of a second semiconductor layer of a first conductivity type. A first trench is formed between a first non-implantation region and one of the plurality of first second conductivity type impurity implantation layers. An epitaxial layer of the first conductivity type is formed and covers the plurality of first second conductivity type impurity implantation layers. A plurality of second second conductivity type impurity implantation layers are formed in a surface of the epitaxial layer. A second trench is formed between a second non-implantation region and one of the plurality of second second conductivity type impurity implantation layers. A third semiconductor layer of the first conductivity type is formed and covers the plurality of second second conductivity type impurity implantation layers.
摘要翻译：电力半导体装置的制造方法包括以下处理。在第一导电类型的第二半导体层的表面中形成多个第一第二导电型杂质注入层。在第一非注入区域和多个第一第二导电型杂质注入层中的一个之间形成第一沟槽。形成第一导电类型的外延层并覆盖多个第一第二导电型杂质注入层。在外延层的表面形成多个第二第二导电型杂质注入层。在第二非注入区域和多个第二第二导电型杂质注入层中的一个之间形成第二沟槽。形成第一导电类型的第三半导体层并且覆盖多个第二第二导电型杂质注入层。

89. 发明授权

US08680608B2 Power semiconductor device with a low on resistence 失效
标题翻译：具有低导通电阻的功率半导体器件
公开(公告)号：US08680608B2
公开(公告)日：2014-03-25
申请号：US12862490
申请日：2010-08-24
申请人： Wataru Saito , Syotaro Ono , Munehisa Yabuzaki , Nana Hatano , Miho Watanabe
发明人： Wataru Saito , Syotaro Ono , Munehisa Yabuzaki , Nana Hatano , Miho Watanabe
IPC分类号： H01L29/78
CPC分类号： H01L29/7802 , H01L29/0634 , H01L29/0649 , H01L29/0653 , H01L29/0873 , H01L29/0878 , H01L29/1095 , H01L29/7843
摘要： According to one embodiment, a power semiconductor device includes a second semiconductor layer of a first conductivity type and a third semiconductor layer of a second conductivity type periodically disposed repeatedly along a surface of the first semiconductor layer on a first semiconductor layer of the first conductivity type. A first main electrode is provided to electrically connect to the first semiconductor layer. A fourth semiconductor layer of the second conductivity type is provided to connect to the third semiconductor layer. Fifth semiconductor layers of the first conductivity type are selectively provided in the fourth semiconductor layer surface. A second main electrode is provided on a surface of the fourth and fifth semiconductor layers. A control electrode is provided on a surface of the fourth, fifth, and second semiconductor layers via a gate insulating film. First insulating films are provided by filling a trench made in the second semiconductor layer.
摘要翻译：根据一个实施例，功率半导体器件包括第一导电类型的第二半导体层和在第一导电类型的第一半导体层上沿着第一半导体层的表面周期性地重复设置的第二导电类型的第三半导体层。提供第一主电极以电连接到第一半导体层。提供第二导电类型的第四半导体层以连接到第三半导体层。在第四半导体层表面中选择性地设置第一导电类型的第五半导体层。第二主电极设置在第四和第五半导体层的表面上。控制电极经由栅极绝缘膜设置在第四，第五和第二半导体层的表面上。通过填充在第二半导体层中制成的沟槽来提供第一绝缘膜。

90. 发明申请

US20130248979A1 POWER SEMICONDUCTOR DEVICE 失效
标题翻译：功率半导体器件
公开(公告)号：US20130248979A1
公开(公告)日：2013-09-26
申请号：US13610532
申请日：2012-09-11
申请人： Syotaro Ono , Masaru Izumisawa , Hiroshi Ohta , Hiroaki Yamashita
发明人： Syotaro Ono , Masaru Izumisawa , Hiroshi Ohta , Hiroaki Yamashita
IPC分类号： H01L27/088
CPC分类号： H01L29/407 , H01L29/0634 , H01L29/0638 , H01L29/0696 , H01L29/1095 , H01L29/402 , H01L29/404 , H01L29/66712 , H01L29/7395 , H01L29/7811 , H01L2924/0002 , H01L2924/00
摘要： A power semiconductor device according to an embodiment includes an element portion in which MOSFET elements are provided and a termination portion provided around the element portion, and has pillar layers provided respectively in parallel to each other in a semiconductor substrate. The device includes a first trench and a first insulation film. The first trench is provided between end portions of the pillar layers, in the semiconductor substrate at the termination portion exposed from a source electrode of the MOSFET elements. The first insulation film is provided on a side surface and a bottom surface of the first trench.
摘要翻译：根据实施例的功率半导体器件包括其中设置MOSFET元件的元件部分和设置在元件部分周围的端接部分，并且在半导体衬底中分别彼此平行地设置有柱层。该器件包括第一沟槽和第一绝缘膜。第一沟槽设置在从MOSFET元件的源电极露出的终端部分的半导体衬底中的柱层的端部之间。第一绝缘膜设置在第一沟槽的侧表面和底表面上。

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