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81. 发明授权

US07605604B1 Integrated circuits with novel handshake logic 有权
标题翻译：具有新颖握手逻辑的集成电路
公开(公告)号：US07605604B1
公开(公告)日：2009-10-20
申请号：US12174945
申请日：2008-07-17
申请人： Steven P. Young
发明人： Steven P. Young
IPC分类号： G06F7/38 , H03K19/173
CPC分类号： H03K19/17736 , H03K19/1776
摘要： Integrated circuits (ICs) having novel handshake logic are provided. An IC includes a ready multiplexer, an acknowledge demultiplexer, a C-element coupled to the ready multiplexer and the acknowledge demultiplexer, a logic gate, and a storage element (e.g., a latch). The logic gate has a first input coupled to a control output of the C-element, and a second input. The storage element includes a data multiplexer and a latch. The data multiplexer has M data inputs coupled to data inputs of the storage element, a select input coupled to the output of the logic gate, and a data output, M being an integer greater than one. The latch has a data input coupled to the data output of the first data multiplexer and an output coupled to an output of the storage element. The logic gate can be a logical AND gate with the second input coupled to a memory cell.
摘要翻译：提供具有新颖握手逻辑的集成电路（IC）。 IC包括就绪复用器，确认解复用器，耦合到就绪复用器和确认解复用器的C元件，逻辑门和存储元件（例如，锁存器）。逻辑门具有耦合到C元件的控制输出的第一输入和第二输入。存储元件包括数据多路复用器和锁存器。数据多路复用器具有耦合到存储元件的数据输入的M个数据输入，耦合到逻辑门的输出的选择输入以及M是大于1的整数的数据输出。锁存器具有耦合到第一数据多路复用器的数据输出的数据输入和耦合到存储元件的输出的输出。逻辑门可以是与第二输入耦合到存储器单元的逻辑与门。

82. 发明申请

US20090121737A1 CHARACTERIZING CIRCUIT PERFORMANCE BY SEPARATING DEVICE AND INTERCONNECT IMPACT ON SIGNAL DELAY 失效
标题翻译：通过分离设备来表征电路性能和对信号延迟的互连影响
公开(公告)号：US20090121737A1
公开(公告)日：2009-05-14
申请号：US12355988
申请日：2009-01-19
申请人： Xiao-Jie Yuan , Michael J. Hart , Zicheng G. Ling , Steven P. Young
发明人： Xiao-Jie Yuan , Michael J. Hart , Zicheng G. Ling , Steven P. Young
IPC分类号： G01R31/26 , G01R31/02 , H01L23/58
CPC分类号： G01R31/2882 , G01R31/318511 , G01R31/318516 , G01R31/3187
摘要： An integrated circuit (IC) includes multiple embedded test circuits that all include a ring oscillator coupled to a test load. The test load either is a direct short in the ring oscillator or else is a interconnect load that is representative of one of the interconnect layers in the IC. A model equation is defined for each embedded test circuit, with each model equation specifying the output delay of its associated embedded test circuit as a function of Front End OF the Line (FEOL) and Back End Of the Line (BEOL) parameters. The model equations are then solved for the various FEOL and BEOL parameters as functions of the test circuit output delays. Finally, measured output delay values are substituted in to these parameter equations to generate actual values for the various FEOL and BEOL parameters, thereby allowing any areas of concern to be quickly and accurately identified.
摘要翻译：集成电路（IC）包括多个嵌入式测试电路，其中都包括耦合到测试负载的环形振荡器。测试负载在环形振荡器中是直接短路，或者是表示IC中互连层之一的互连负载。为每个嵌入式测试电路定义一个模型方程，每个模型方程式将其相关嵌入式测试电路的输出延迟指定为线路前端（FEOL）和线路后端（BEOL）参数的函数。然后，对于各种FEOL和BEOL参数求解模型方程，作为测试电路输出延迟的函数。最后，将测量的输出延迟值替换为这些参数方程，以生成各种FEOL和BEOL参数的实际值，从而允许快速准确地识别任何关注的领域。

83. 发明授权

US07499513B1 Method and apparatus for providing frequency synthesis and phase alignment in an integrated circuit 有权
标题翻译：用于在集成电路中提供频率合成和相位对准的方法和装置
公开(公告)号：US07499513B1
公开(公告)日：2009-03-03
申请号：US11049329
申请日：2005-02-02
申请人： David E. Tetzlaff , F. Erich Goetting , Steven P. Young , Marwan M. Hassoun , Moises E. Robinson
发明人： David E. Tetzlaff , F. Erich Goetting , Steven P. Young , Marwan M. Hassoun , Moises E. Robinson
IPC分类号： H04L7/00 , H03L7/06
CPC分类号： G06F1/10 , H03L7/07 , H03L7/0891 , H03L7/095 , H03L7/183
摘要： According to particular example embodiments, an integrated circuit includes one or more serializing data transmitters. Each such data transmitter is arranged to transmit data on a respective data output port of the integrated circuit, wherein the respective data output port for at least one of the data transmitters is dedicated to transmitting periodic data used for clocking a respective target circuit. In other particular embodiments involving feedback, phase-locked loop (PLL) signal control and/or delay-locked loop (DLL) signal control is achieved in functional blocks of a programmable logic device (PLD). The PLD is responsive to a source clock and includes a configurable logic array that includes configurable logic blocks and configurable routing blocks, and the respective data output port for at least one of the data transmitters provides a respective target clock.
摘要翻译：根据特定示例性实施例，集成电路包括一个或多个串行数据发送器。每个这样的数据发射器被布置成在集成电路的相应数据输出端口上发送数据，其中用于至少一个数据发射器的相应数据输出端口专用于发送用于对相应目标电路计时的周期性数据。在涉及反馈的其他具体实施例中，在可编程逻辑器件（PLD）的功能块中实现了锁相环（PLL）信号控制和/或延迟锁定环（DLL）信号控制。 PLD响应于源时钟并且包括可配置逻辑阵列，其包括可配置逻辑块和可配置路由块，并且用于至少一个数据发射器的相应数据输出端口提供相应的目标时钟。

84. 发明授权

US07491576B1 Yield-enhancing methods of providing a family of scaled integrated circuits 有权
标题翻译：提供一系列缩放集成电路的产量增强方法
公开(公告)号：US07491576B1
公开(公告)日：2009-02-17
申请号：US11333990
申请日：2006-01-17
申请人： Steven P. Young , Trevor J. Bauer , F. Erich Goetting , P. Hugo Lamarche , Patrick J. McGuire , Kwansuhk Oh , Raymond C. Pang , Bruce E. Talley , Paul Ying-Fung Wu
发明人： Steven P. Young , Trevor J. Bauer , F. Erich Goetting , P. Hugo Lamarche , Patrick J. McGuire , Kwansuhk Oh , Raymond C. Pang , Bruce E. Talley , Paul Ying-Fung Wu
IPC分类号： H01L21/66 , H01L21/44 , H01L21/48 , H01L21/50
CPC分类号： H01L22/22 , H01L23/544 , H01L2223/5444 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit die (e.g., a programmable logic device (PLD) die) is manufactured that has the capability of being configured as at least two differently-sized family members. The IC die is tested prior to packaging. If a first portion of the IC die is fully functional, but a second portion includes a localized defect, then the IC die is packaged with a product selection code that configures the IC die to operate as only the first portion of the die. The second portion of the die is deliberately rendered non-operational. Therefore, the IC die can still be sold as a fully functional packaged IC.
摘要翻译：制造集成电路管芯（例如，可编程逻辑器件（PLD）管芯），其具有被配置为至少两个不同尺寸的家庭部件的能力。在封装之前测试IC芯片。如果IC芯片的第一部分是完全功能的，但是第二部分包括局部缺陷，则IC芯片被封装成产品选择代码，所述产品选择代码构成IC裸片仅作为芯片的第一部分进行操作。死亡的第二部分故意使其不能运作。因此，IC芯片仍然可以作为全功能封装IC出售。

85. 发明授权

US07472155B2 Programmable logic device with cascading DSP slices 有权
标题翻译：具有级联DSP片的可编程逻辑器件
公开(公告)号：US07472155B2
公开(公告)日：2008-12-30
申请号：US11019783
申请日：2004-12-21
申请人： James M. Simkins , Steven P. Young , Jennifer Wong , Bernard J. New , Alvin Y. Ching
发明人： James M. Simkins , Steven P. Young , Jennifer Wong , Bernard J. New , Alvin Y. Ching
IPC分类号： G06F7/38
CPC分类号： H03K19/17736 , G06F15/7867 , H03K19/17732
摘要： Described is a programmable logic device (PLD) with columns of DSP slices that can be cascaded to create DSP circuits of varying size and complexity. Each DSP slice includes a plurality of operand input ports and a slice output port, all of which are programmably connected to general routing and logic resources. The operand ports receive operands for processing, and a slice output port conveys processed results. Each slice additionally includes a feedback port connected to the respective slice output port, to support accumulate functions in this embodiment, and a cascade input port connected to the output port of an upstream slice to support cascading.
摘要翻译：描述了可编程逻辑器件（PLD），其具有可以级联的DSP片段，以创建不同大小和复杂度的DSP电路。每个DSP片包括多个操作数输入端口和片输出端口，所有这些端口都可编程地连接到通用路由和逻辑资源。操作数端口接收处理的操作数，切片输出端口传送处理结果。每个切片还包括连接到相应切片输出端口的反馈端口，以支持在该实施例中的累积功能，以及连接到上游切片的输出端口以支持级联的级联输入端口。

86. 发明授权

US07467175B2 Programmable logic device with pipelined DSP slices 有权
标题翻译：可编程逻辑器件，带流水线DSP片
公开(公告)号：US07467175B2
公开(公告)日：2008-12-16
申请号：US11019782
申请日：2004-12-21
申请人： James M. Simkins , Steven P. Young , Jennifer Wong , Bernard J. New , Alvin Y. Ching
发明人： James M. Simkins , Steven P. Young , Jennifer Wong , Bernard J. New , Alvin Y. Ching
IPC分类号： G06F7/38
CPC分类号： H03K19/17736 , H03K19/17732
摘要： Described is a programmable logic device (PLD) with columns of DSP slices that can be combined to create DSP circuits of varying size and complexity. DSP slices in accordance with some embodiments includes programmable operand input registers that can be configured to introduce different amounts of delay, from zero to two clock cycles, for example, to support pipelining. In one such embodiment, each DSP slice includes a partial-product generator having a multiplier port, a multiplicand port, and a product port. The multiplier and multiplicand ports connect to the operand input port via respective first and second operand input registers, each of which is capable of introducing from zero to two clock cycles of delay. In another embodiment, the output of at least one operand input register can connect to the input of an operand input register of a downstream DSP slice so that operands can be transferred among one or more slices.
摘要翻译：描述了可编程逻辑器件（PLD），其具有可以组合的DSP片段，以创建不同大小和复杂度的DSP电路。根据一些实施例的DSP片段包括可被配置为从零到两个时钟周期引入不同量的延迟的可编程操作数输入寄存器，例如以支持流水线化。在一个这样的实施例中，每个DSP片包括具有乘法器端口，被乘数端口和产品端口的部分乘积生成器。乘法器和被乘数端口通过相应的第一和第二操作数输入寄存器连接到操作数输入端口，每个第一和第二操作数输入寄存器能够从零延迟到两个延迟的时钟周期。在另一个实施例中，至少一个操作数输入寄存器的输出可以连接到下游DSP片的操作数输入寄存器的输入，使得操作数可以在一个或多个片之间传送。

87. 发明授权

US07426678B1 Error checking parity and syndrome of a block of data with relocated parity bits 有权
标题翻译：错误检查具有重定位奇偶校验位的数据块的奇偶校验和校验
公开(公告)号：US07426678B1
公开(公告)日：2008-09-16
申请号：US10971220
申请日：2004-10-22
申请人： Warren E. Cory , David P. Schultz , Steven P. Young
发明人： Warren E. Cory , David P. Schultz , Steven P. Young
IPC分类号： H03M13/00
CPC分类号： H03M13/27 , H03M13/19 , H03M13/45
摘要： Method and apparatus for error checking information is described. Configuration data includes data bits and parity bits. Notably, parity bits may be relocated for determining a syndrome value. Syndrome bits are determined by computing a partial syndrome value for each word serially transmitted of the configuration data, where the configuration data includes one or more data vectors. Location of each word of the configuration data is identified. It is determined whether a partial syndrome value is an initial partial syndrome value or other partial syndrome value responsive to word location. An initial partial syndrome value is stored, and subsequent partial syndrome values are cumulatively added for each word of a data vector to arrive at a syndrome value for the data vector.
摘要翻译：描述了用于错误检查信息的方法和装置。配置数据包括数据位和奇偶校验位。值得注意的是，可以重新定位奇偶校验位以确定校正子值。通过对配置数据的串行发送的每个字计算部分校正子值来确定综合征位，其中配置数据包括一个或多个数据向量。识别配置数据的每个单词的位置。确定部分综合征值是否是初始部分综合征值或响应于词位置的其他部分综合征值。存储初始部分综合征值，并且随后的部分综合征值被累积地添加到数据向量的每个单词以得到数据向量的校正子值。

88. 发明授权

US07414430B2 Programmable logic device having an embedded differential clock tree 有权
标题翻译：具有嵌入式差分时钟树的可编程逻辑器件
公开(公告)号：US07414430B2
公开(公告)日：2008-08-19
申请号：US11511647
申请日：2006-08-29
申请人： Vasisht Mantra Vadi , Steven P. Young , Atul V. Ghia , Adebabay M. Bekele , Suresh M. Menon
发明人： Vasisht Mantra Vadi , Steven P. Young , Atul V. Ghia , Adebabay M. Bekele , Suresh M. Menon
IPC分类号： H03K19/177
CPC分类号： G06F1/10 , H03K5/15013 , H03K19/1774 , H03K19/17784 , H03K19/17796
摘要： A clock distribution network having: a backbone clock signal line configured to provide a differential clock signal; multiple branches coupled to the backbone clock signal line for distributing the differential clock signal to multiple programmable function elements; a first leaf node coupled to a first branch, where the first leaf node is configured to provide the differential clock signal to a first programmable function element; and a second leaf node coupled to a second branch, where the second leaf node is configured to provide a single ended clock signal derived from the differential clock signal to a second programmable function element.
摘要翻译：一种时钟分配网络，具有：骨干时钟信号线，被配置为提供差分时钟信号; 多个分支耦合到主干时钟信号线，用于将差分时钟信号分配给多个可编程功能元件; 耦合到第一分支的第一叶节点，其中所述第一叶节点被配置为将所述差分时钟信号提供给第一可编程功能元件; 以及耦合到第二分支的第二叶节点，其中所述第二叶节点被配置为将从所述差分时钟信号导出的单端时钟信号提供给第二可编程功能元件。

89. 发明授权

US07382157B1 Interconnect driver circuits for dynamic logic 有权
标题翻译：用于动态逻辑的互连驱动电路
公开(公告)号：US07382157B1
公开(公告)日：2008-06-03
申请号：US11541986
申请日：2006-10-02
申请人： Steven P. Young , Ramakrishna K. Tanikella , Manoj Chirania , Venu M. Kondapalli
发明人： Steven P. Young , Ramakrishna K. Tanikella , Manoj Chirania , Venu M. Kondapalli
IPC分类号： H03K19/177
CPC分类号： H03K19/17736 , H03K17/693 , H03K19/17728
摘要： Interconnect driver circuits that can be used in the interconnect structures of dynamic integrated circuits (ICs) such as dynamic programmable logic devices (PLDs). An exemplary IC includes two or more logic circuits, and two or more self-resetting interconnect driver circuits coupled between the logic circuits. Each self-resetting interconnect driver circuit includes a multiplexer circuit driving a buffer circuit. In a first state, the buffer circuit drives a first value onto the output terminal of the buffer circuit. In a second state, the buffer circuit first drives a second value onto the output terminal of the buffer circuit and then returns to the first state. Several different circuits are described in detail.
摘要翻译：互连驱动电路，可用于动态集成电路（IC）的互连结构，如动态可编程逻辑器件（PLD）。示例性IC包括两个或多个逻辑电路和耦合在逻辑电路之间的两个或多个自复位互连驱动器电路。每个自复位互连驱动器电路包括驱动缓冲电路的多路复用器电路。在第一状态下，缓冲电路将第一值驱动到缓冲电路的输出端上。在第二状态下，缓冲电路首先将第二值驱动到缓冲电路的输出端，然后返回到第一状态。详细描述了几个不同的电路。

90. 发明申请

US20080121311A1 Dadoing System 有权
标题翻译： Dadoing系统
公开(公告)号：US20080121311A1
公开(公告)日：2008-05-29
申请号：US11563107
申请日：2006-11-24
申请人： Steven P. Young
发明人： Steven P. Young
IPC分类号： B27C5/00
CPC分类号： B23Q9/0014 , B23Q3/069 , B23Q39/028 , Y10T409/303696 , Y10T409/309016
摘要： A dadoing system that can be set up to cut multiple dados in a workpiece. The dadoing system uses a sliding channel clamp to keep the workpiece from moving in a transverse direction, while the dados are being cut into the workpiece. The sliding guide rails are used to put downward pressure on a workpiece while guiding a router across the workpiece during the dadoing process. Once the system is set up to cut the dados in the desired locations on the workpiece, the sliding guide rail stops can be secured into place. The stops will insure that the sliding guide rails are set up in the same place thus allowing multiple workpieces to have matching dados that line up properly during assembly.
摘要翻译：可以设置在工件上切割多个dados的dadoing系统。 dadoing系统使用滑动通道夹具来保持工件在横向方向上移动，同时将dados切入工件。滑动导轨用于在进给过程中引导路由器穿过工件时向下施加工件。一旦将系统设置成在工件上的所需位置上切割dados，则可以将滑动导轨停止点固定到位。止动件将确保滑动导轨设置在相同的位置，从而允许多个工件具有在组装期间适当排列的匹配的dados。

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