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81. 发明申请

US20060268474A1 Tie-off circuit with ESD protection features 有权
标题翻译：具有ESD保护功能的断电电路
公开(公告)号：US20060268474A1
公开(公告)日：2006-11-30
申请号：US11137265
申请日：2005-05-25
申请人： Shao-Chang Huang , Jian-Hsing Lee
发明人： Shao-Chang Huang , Jian-Hsing Lee
IPC分类号： H02H9/00
CPC分类号： H01L27/0251
摘要： The present invention discloses a tie-off circuit coupled between a first potential and a gate of a MOS device whose source is connected to a second potential. The tie-off circuit includes at least one resistor and at least on diode. The resistor is coupled between the gate of the MOS device and the first potential for preventing the gate of the MOS device from floating during a normal circuit operation. The diode is coupled between the gate of the MOS device and the first potential, in parallel with the resistor, for reducing a voltage difference across a gate oxide layer of the MOS device during an electrostatic discharge (ESD) event, thereby protecting the same from ESD damage.
摘要翻译：本发明公开了一种耦合在源极连接到第二电位的MOS器件的第一电位和栅极之间的断开电路。连接电路至少包括一个电阻器，并且至少在二极管上。电阻器耦合在MOS器件的栅极和用于防止MOS器件的栅极在正常电路操作期间浮置的第一电位之间。二极管耦合在MOS器件的栅极和与电阻器并联的第一电位之间，用于在静电放电（ESD）事件期间减小MOS器件的栅氧化层上的电压差，从而保护 ESD损坏。

82. 发明申请

US20050280091A1 Semiconductor structure and method for ESD protection 有权
标题翻译：半导体结构和ESD保护方法
公开(公告)号：US20050280091A1
公开(公告)日：2005-12-22
申请号：US10887793
申请日：2004-07-09
申请人： Shao-Chang Huang , Jian-Hsing Lee
发明人： Shao-Chang Huang , Jian-Hsing Lee
IPC分类号： H01L23/62 , H01L27/02 , H01L27/08 , H01L29/06
CPC分类号： H01L27/0255 , H01L27/0814 , H01L29/0619
摘要： A semiconductor integrated circuit structure includes a plurality of diodes disposed in the substrate. These diodes are electrically coupled in series. At least one insertion region is disposed in the substrate between two of the diodes and a supply voltage node electrically coupled to the insertion region. Preferably, a guard ring surrounds the diodes.
摘要翻译：半导体集成电路结构包括设置在基板中的多个二极管。这些二极管串联电耦合。至少一个插入区域设置在两个二极管之间的衬底中，以及电耦合到插入区域的电源电压节点。优选地，保护环围绕二极管。

83. 发明授权

US06960811B2 Low capacitance ESD protection device, and integrated circuit including the same 有权
标题翻译：低电容ESD保护器件及集成电路包括相同
公开(公告)号：US06960811B2
公开(公告)日：2005-11-01
申请号：US10929735
申请日：2004-08-30
申请人： Yi-Hsun Wu , Jian-Hsing Lee
发明人： Yi-Hsun Wu , Jian-Hsing Lee
IPC分类号： H01L23/62 , H01L27/02
CPC分类号： H01L27/0266
摘要： A low capacitance ESD protection device. The device comprises a substrate, a well of a first conductivity type in the substrate, a first and second transistor of the first conductivity type respectively on two sides of the well, a guard ring of a second conductivity type in the substrate, surrounding the well, and the first and second transistor, and a doped region of the second conductivity type in the well, wherein profiles of a drain and source region of each of the first and second transistor are un-symmetrical, and an area of the drain region is smaller than that of the source region in each of the first and second transistor.
摘要翻译：低电容ESD保护器件。该器件包括衬底，衬底中的第一导电类型的阱，分别在阱的两侧上的第一导电类型的第一和第二晶体管，衬底中的第二导电类型的保护环，围绕阱以及所述第一和第二晶体管以及所述阱中的所述第二导电类型的掺杂区域，其中所述第一和第二晶体管中的每一个的漏极和源极区域的轮廓是不对称的，并且所述漏极区域的面积为小于第一和第二晶体管中的每一个中的源极区域。

84. 发明申请

US20050180071A1 Circuit and method for ESD protection 审中-公开
标题翻译：电路和ESD保护方法
公开(公告)号：US20050180071A1
公开(公告)日：2005-08-18
申请号：US10779341
申请日：2004-02-13
申请人： Yi-Hsun Wu , Jian-Hsing Lee , Tongehen Ong
发明人： Yi-Hsun Wu , Jian-Hsing Lee , Tongehen Ong
IPC分类号： H01L27/02 , H02H9/00
CPC分类号： H01L27/0266 , H01L27/0288
摘要： A circuit and a method for ESD protection are disclosed. The circuit includes an ESD protection circuit coupled to a pad. A device is coupled to the pad and an internal circuit. The device generates a voltage drop between the pad and the internal circuit, protecting thin oxide layers of the internal circuit from damage. The method comprises coupling an internal circuit to an ESD protection circuit and generating a voltage drop between a pad and the internal circuit to protect thin oxide layers of the internal circuit from damage when an ESD pulse is coupled to the pad.
摘要翻译：公开了一种用于ESD保护的电路和方法。电路包括耦合到焊盘的ESD保护电路。器件耦合到焊盘和内部电路。该器件在焊盘和内部电路之间产生电压降，保护内部电路的薄氧化物层免受损坏。该方法包括将内部电路耦合到ESD保护电路并且在衬垫和内部电路之间产生电压降，以在ESD脉冲耦合到衬垫时保护内部电路的薄氧化物层免受损坏。

85. 发明申请

US20050041346A1 Circuit and method for ESD protection 有权
标题翻译：电路和ESD保护方法
公开(公告)号：US20050041346A1
公开(公告)日：2005-02-24
申请号：US10644718
申请日：2003-08-20
申请人： Yi-Hsun Wu , Jian-Hsing Lee
发明人： Yi-Hsun Wu , Jian-Hsing Lee
IPC分类号： H01L23/60 , H01L27/02 , H02H9/00
CPC分类号： H01L27/0285
摘要： A sensor for electrostatic discharge (ESD) protection includes a voltage divider and a device coupled thereto. The sensor is coupled to an input terminal of the sensor, wherein a voltage drop occurs across the voltage divider and a high state voltage is generated at an output terminal of the sensor when an ESD voltage pulse is applied to the input terminal of the sensor. The device maintains the high state voltage at the output terminal of the sensor, while the ESD voltage pulse is applied to the input terminal of the sensor. A method for ESD protection includes the step of pulling down a gate terminal of a MOS transistor of an ESD circuit to a low state voltage when an ESD pulse is sensed.
摘要翻译：用于静电放电（ESD）保护的传感器包括分压器和与其耦合的装置。传感器耦合到传感器的输入端，其中在分压器上发生电压降，并且当ESD电压脉冲施加到传感器的输入端时，在传感器的输出端产生高的状态电压。该装置在传感器的输出端保持高状态电压，同时将ESD电压脉冲施加到传感器的输入端。 ESD保护的方法包括当感测到ESD脉冲时将ESD电路的MOS晶体管的栅极端子下拉到低状态电压的步骤。

86. 发明授权

US06653709B2 CMOS output circuit with enhanced ESD protection using drain side implantation 有权
公开(公告)号：US06653709B2
公开(公告)日：2003-11-25
申请号：US10213612
申请日：2002-08-07
申请人： Yi-Hsu Wu , Hung-Der Su , Jian-Hsing Lee , Boon-Khim Liew
发明人： Yi-Hsu Wu , Hung-Der Su , Jian-Hsing Lee , Boon-Khim Liew
IPC分类号： H01L2972
CPC分类号： H01L27/092 , H01L21/823814 , H01L27/0266
摘要： A new cascaded NMOS transistor output circuit with enhanced ESD protection is achieved. A driver PMOS transistor has the source connected to a voltage supply, the gate connected to the input signal, and the drain connected to the output pad. A dummy PMOS transistor has the source and the gate connected to the voltage supply, and the drain connected to the output pad. A driver NMOS cascaded stack comprises first and second NMOS transistors. The first NMOS transistor has the source connected to ground and the gate connected to the input signal. The second NMOS transistor has the gate connected to the voltage supply, the source connected to the first NMOS transistor drain, and the drain connected to the output pad. A p− implanted region underlies the n+ region of the drain but does not underlie the n+ region of the source. A dummy NMOS cascaded stack comprises third and fourth NMOS transistors. The third NMOS transistor has the gate and the source connected to ground. The fourth NMOS transistor has the gate connected to the voltage supply, the source connected to the third MOS transistor drain, and the drain connected to the output pad. A p− implanted region underlies the n+ region of the drain but does not underlie the n+ region of the source.

87. 发明授权

US06479872B1 Dynamic substrate-coupled electrostatic discharging protection circuit 有权
标题翻译：动态衬底耦合静电放电保护电路
公开(公告)号：US06479872B1
公开(公告)日：2002-11-12
申请号：US09221959
申请日：1998-12-28
申请人： Tao Cheng , Jian-Hsing Lee , Lin-June Wu
发明人： Tao Cheng , Jian-Hsing Lee , Lin-June Wu
IPC分类号： H01L2362
CPC分类号： H01L27/0266
摘要： A dynamic source coupled ESD protection circuit that dissipates an ESD voltage coupled to an electrical contact pad to protect internal circuits on an integrated circuits chip is described. The ESD protection circuit lowers the snapback voltage of the ESD protection circuit to allow a thinner gate oxide within the internal circuits of the integrated circuit chip. The dynamic substrate coupled electrostatic discharge protection circuit consists of a gated MOS transistor, a capacitor, and a resistor. The gated MOS transistor has a drain region connected to the electrical contact pad. The gate and source are connected to a power supply voltage source. The power supply voltage source will either be a substrate biasing voltage or ground reference point for a gated NMOS transistor. The power supply voltage source will be the power supply voltage source VDD for the gated PMOS transistor. The capacitor has a first plate connected to the electrical contact pad, and a second plate connected to said substrate bulk region of the MOS transistor. The resistor is a polycrystalline silicon resistor that is connected between the second plate of the capacitor and the power supply voltage source.
摘要翻译：描述了动态源耦合ESD保护电路，其消耗耦合到电接触焊盘的ESD电压以保护集成电路芯片上的内部电路。 ESD保护电路降低ESD保护电路的回跳电压，以便在集成电路芯片的内部电路内允许更薄的栅极氧化物。动态衬底耦合静电放电保护电路由门控MOS晶体管，电容器和电阻组成。门控MOS晶体管具有连接到电接触焊盘的漏极区域。栅极和源极连接到电源电压源。电源电压源将是门控NMOS晶体管的衬底偏置电压或接地参考点。电源电压源将是门控PMOS晶体管的电源电压源VDD。电容器具有连接到电接触焊盘的第一板和连接到MOS晶体管的所述衬底主体区域的第二板。电阻器是连接在电容器的第二板和电源电压源之间的多晶硅电阻器。

88. 发明授权

US5903499A Method to erase a flash EEPROM using negative gate source erase followed by a high negative gate erase 失效
标题翻译：使用负栅极源擦除后跟高负栅极擦除擦除闪存EEPROM的方法
公开(公告)号：US5903499A
公开(公告)日：1999-05-11
申请号：US928227
申请日：1997-09-12
申请人： Kuo-Reay Peng , Jian-Hsing Lee , Juang-Ke Yeh , Ming-Chou Ho
发明人： Kuo-Reay Peng , Jian-Hsing Lee , Juang-Ke Yeh , Ming-Chou Ho
IPC分类号： G11C16/14 , G11C16/04
CPC分类号： G11C16/14
摘要： A method to erase data from a flash EEPROM while electrical charges trapped in the tunneling oxide of a flash EEPROM are eliminated to maintain proper separation of the programmed threshold voltage and the erased threshold voltage after extended programming and erasing cycles. The method to erase a flash EEPROM cell begins by first applying a moderately high positive voltage pulse to the source of the EEPROM cell. Simultaneously, a first relatively large negative voltage is applied to the control gate. While a ground reference potential is applied to the semiconductor substrate. At this same time the drain is floating. The flash EEPROM cell is then detrapped by floating the source and drain and applying the ground reference potential to the semiconductor substrate. At the same time a second relatively large negative voltage pulse is applied to the control gate.
摘要翻译：一种在闪存EEPROM的隧道氧化物中捕获电荷的情况下从闪存EEPROM擦除数据的方法被消除，以便在扩展编程和擦除周期之后保持编程阈值电压和擦除阈值电压的适当分离。擦除快闪EEPROM单元的方法是首先向EEPROM单元的源极施加适度高的正电压脉冲。同时，向控制栅极施加第一相对较大的负电压。同时对半导体衬底施加接地参考电位。在同一时间，排水沟漂浮。然后通过漂浮源极和漏极并将接地参考电位施加到半导体衬底来去除快闪EEPROM单元。同时，向控制栅极施加第二相对大的负电压脉冲。

89. 发明授权

US5838618A Bi-modal erase method for eliminating cycling-induced flash EEPROM cell write/erase threshold closure 失效
标题翻译：用于消除循环感应闪速EEPROM单元写入/擦除阈值闭合的双模式擦除方法
公开(公告)号：US5838618A
公开(公告)日：1998-11-17
申请号：US927472
申请日：1997-09-11
申请人： Jian-Hsing Lee , Juang-Ker Yeh , Kuo-Reay Peng , Ming-Chou Ho
发明人： Jian-Hsing Lee , Juang-Ker Yeh , Kuo-Reay Peng , Ming-Chou Ho
IPC分类号： G11C16/14 , G11C16/04 , G11C7/00
CPC分类号： G11C16/14
摘要： A method to erase data from a flash EEPROM while electrical charges trapped in the tunneling oxide of a flash EEPROM are eliminated to maintain proper separation of the programmed threshold voltage and the erased threshold voltage after extended programming and erasing cycles. The method to erase a flash EEPROM cell begins by channel erasing to remove charge from the floating gate of the flash EEPROM cell. The channel erasing consists of applying a first relatively large negative voltage pulse to the control gate of said EEPROM cell and concurrently applying a first moderately large positive voltage pulse to a first diffusion well. At the same time a ground reference potential is applied to the semiconductor substrate, while the drain and a second diffusion well is allowed to float. The method to erase then proceeds with the source erasing to detrap the tunneling oxide of the flash EEPROM cell. The source erasing consists continued floating the drain and the second diffusion well and concurrently applying the ground reference potential to the semiconductor substrate and the first diffusion well. Concurrently a second relatively large negative voltage pulse is applied to the control gate, as a second moderately large positive voltage pulse is applied to said source.
摘要翻译：一种在闪存EEPROM的隧道氧化物中捕获电荷的情况下从闪存EEPROM擦除数据的方法被消除，以便在扩展编程和擦除周期之后保持编程阈值电压和擦除阈值电压的适当分离。擦除闪存EEPROM单元的方法是从通道擦除开始，以从闪存EEPROM单元的浮动栅极去除电荷。通道擦除包括将第一相对较大的负电压脉冲施加到所述EEPROM单元的控制栅并且同时向第一扩散阱施加第一适度大的正电压脉冲。同时，对半导体衬底施加接地参考电位，同时使漏极和第二扩散阱浮动。擦除的方法然后继续进行源擦除以去除快速EEPROM单元的隧穿氧化物。源擦除继续浮置漏极和第二扩散阱，同时将接地参考电位施加到半导体衬底和第一扩散阱。同时，向控制栅极施加第二相对较大的负电压脉冲，因为向所述源施加第二适度大的正电压脉冲。

90. 发明授权

US5565790A ESD protection circuit with field transistor clamp and resistor in the gate circuit of a clamp triggering FET 失效
标题翻译： ESD保护电路与场晶体管钳位和电阻在钳位触发FET的栅极电路中
公开(公告)号：US5565790A
公开(公告)日：1996-10-15
申请号：US387084
申请日：1995-02-13
申请人： Jian-Hsing Lee
发明人： Jian-Hsing Lee
IPC分类号： H01L27/02 , H02H9/04 , H01L23/62
CPC分类号： H01L27/0266 , H01L27/0251
摘要： An improved ESD protection circuit of the type having a field transistor connected as a clamp between ground and a pad to be protected and an FET trigger circuit that is connected between ground and a node where the protected circuits are connected. A resistor interconnects the pad and the node. The trigger FET turns on when a high ESD voltage causes avalanche breakdown and charge carriers from the trigger FET turn on the field transistor clamp. Before the field transistor clamp turns on, oxide breakdown in the gate oxide of the FET occurs. A resistor is connected between the gate electrode and ground to limit the current through the oxide during the time for the avalanche to develop and for the clamp to turn on.
摘要翻译：一种改进的ESD保护电路，其具有连接在接地和待保护的焊盘之间的钳位的场晶体管，以及连接在地和被保护电路连接的节点之间的FET触发电路。电阻器使焊盘和节点互连。当高ESD电压引起雪崩击穿时，触发FET导通，并且来自触发FET的电荷载流子导通场晶体管钳位。在场晶体管钳位导通之前，FET的栅极氧化物发生氧化物击穿。电阻器连接在栅电极和地之间以限制在雪崩发展的时间期间通过氧化物的电流，并且钳位器导通。

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