专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07518843B2 ESD protection circuit with low parasitic capacitance 有权
标题翻译：具有低寄生电容的ESD保护电路
公开(公告)号：US07518843B2
公开(公告)日：2009-04-14
申请号：US11134539
申请日：2005-05-19
申请人： Yi-Hsun Wu , Jian-Hsing Lee
发明人： Yi-Hsun Wu , Jian-Hsing Lee
IPC分类号： H02H9/00 , H02H3/22
CPC分类号： H01L27/0262
摘要： An ESD protection circuit includes a silicon controlled rectifier coupled between a circuit pad and ground for bypassing an ESD current from the circuit pad during an ESD event. An MOS transistor, having a source shared with the silicon controlled rectifier, is coupled between the pad and ground for reducing a trigger voltage of the silicon controlled rectifier during the ESD event. The silicon controlled rectifier has a first diode serially connected to a second diode in an opposite direction, between the pad and the shared source of the MOS transistor, for functioning as a bipolar transistor. In a layout view, a first area for placement of the first and second diodes is interposed between at least two separate sets of second areas for placement of the MOS transistor.
摘要翻译： ESD保护电路包括耦合在电路焊盘和地之间的可控硅整流器，用于在ESD事件期间旁路来自电路板的ESD电流。具有与可控硅整流器共享的源极的MOS晶体管耦合在焊盘和地之间，以在ESD事件期间降低可控硅整流器的触发电压。可控硅整流器具有在与MOS晶体管的焊盘和共享源之间的相反方向上串联连接到第二二极管的第一二极管，用作双极晶体管。在布局图中，用于放置第一和第二二极管的第一区域介于至少两个分开的第二区域组之间，用于放置MOS晶体管。

2. 发明授权

US07508639B2 Input/output devices with robustness of ESD protection 有权
标题翻译：具有ESD保护鲁棒性的输入/输出设备
公开(公告)号：US07508639B2
公开(公告)日：2009-03-24
申请号：US11305983
申请日：2005-12-19
申请人： Yi-Hsun Wu , Jian-Hsing Lee , Shui-Hung Chen
发明人： Yi-Hsun Wu , Jian-Hsing Lee , Shui-Hung Chen
IPC分类号： H02H9/00 , H02H3/22 , H02H1/00 , H02H1/04 , H02H9/06 , H01C7/12
CPC分类号： H01L27/0266 , H01L2924/0002 , H01L2924/00
摘要： Input/output devices with robustness of ESD protection are provided. An input/output device comprises an input/output pad, a first NMOS transistor, a second NMOS transistor and an ESD detector. The first NMOS transistor comprises a first drain, a first source and a first gate, wherein the first source and the first gate are coupled to a first ground power rail, and the first drain to the input/output pad. The second NMOS transistor comprises a second drain, a second source and a second gate, wherein the second source is coupled to the first ground power rail, the second drain to the input/output pad, and the second gate to a first pre-driver. When an ESD event is detected, the ESD detector makes the first pre-driver couple the second gate to the first ground power rail, thereby the first and second transistors evenly discharge ESD current.
摘要翻译：提供具有ESD保护鲁棒性的输入/输出设备。输入/输出装置包括输入/输出焊盘，第一NMOS晶体管，第二NMOS晶体管和ESD检测器。第一NMOS晶体管包括第一漏极，第一源极和第一栅极，其中第一源极和第一栅极耦合到第一接地电源轨，第一漏极耦合到输入/输出焊盘。第二NMOS晶体管包括第二漏极，第二源极和第二栅极，其中第二源极耦合到第一接地电源轨，第二漏极耦合到输入/输出焊盘，第二栅极耦合到第一预驱动器。当检测到ESD事件时，ESD检测器使第一预驱动器将第二栅极耦合到第一接地电源轨，由此第一和第二晶体管均匀地放电ESD电流。

3. 发明授权

US07465994B2 Layout structure for ESD protection circuits 有权
标题翻译： ESD保护电路的布局结构
公开(公告)号：US07465994B2
公开(公告)日：2008-12-16
申请号：US11512850
申请日：2006-08-29
申请人： Kuo-Feng Yu , Jian-Hsing Lee , Yi-Hsun Wu , C.S Tang
发明人： Kuo-Feng Yu , Jian-Hsing Lee , Yi-Hsun Wu , C.S Tang
IPC分类号： H01L23/62
CPC分类号： H01L27/0266
摘要： A layout structure for an ESD protection circuit includes a first MOS device area having a first and second doped regions of the same polarity disposed at two sides of a first conductive gate layer, and a third doped region disposed along the first doped region at one side of the first conductive gate layer. The third doped region has a polarity different from that of the first and second doped regions, such that the third doped region and the second doped region form a diode for enhancing dissipation of ESD current during a negative ESD event.
摘要翻译： ESD保护电路的布局结构包括：第一MOS器件区域，具有设置在第一导电栅极层的两侧的具有相同极性的第一和第二掺杂区域;以及第三掺杂区域，沿第一掺杂区域设置在一侧的第一导电栅极层。第三掺杂区域具有与第一和第二掺杂区域不同的极性，使得第三掺杂区域和第二掺杂区域形成用于在负ESD事件期间增强ESD电流的耗散的二极管。

4. 发明授权

US07154724B2 Output buffer ESD protection using parasitic SCR protection circuit for CMOS VLSI integrated circuits 有权
标题翻译：输出缓冲器ESD保护，使用CMOS VLSI集成电路的寄生SCR保护电路
公开(公告)号：US07154724B2
公开(公告)日：2006-12-26
申请号：US10812378
申请日：2004-03-29
申请人： Yi-Hsun Wu , Jian-Hsing Lee
发明人： Yi-Hsun Wu , Jian-Hsing Lee
IPC分类号： H02H9/04 , H01L23/62
CPC分类号： H01L27/0262
摘要： An input and output (I/O) circuit with an improved ESD protection is disclosed. The circuit has an output buffer having an NMOS transistor coupled to a PMOS transistor, an ESD protection circuit having a parasitic silicon controlled rectifier (SCR) integrated therein and coupled to the output buffer, and a diode string having a predetermined number of diodes coupled between a source node of the NMOS transistor and ground, wherein a voltage drop across the diode string increases the SCR gate holding voltage, thereby setting an ESD protection holding voltage for the ESD protection circuit.
摘要翻译：公开了具有改进的ESD保护的输入和输出（I / O）电路。电路具有输出缓冲器，其具有耦合到PMOS晶体管的NMOS晶体管，ESD保护电路具有集成在其中并耦合到输出缓冲器的寄生可控硅整流器（SCR），以及二极管串，其具有预定数量的二极管 NMOS晶体管的源节点并接地，其中二极管串上的电压降增加了SCR栅极保持电压，从而为ESD保护电路设置ESD保护保持电压。

5. 发明申请

US20060114629A1 Input/output devices with robustness of ESD protection 有权
公开(公告)号：US20060114629A1
公开(公告)日：2006-06-01
申请号：US11305983
申请日：2005-12-19
申请人： Yi-Hsun Wu , Jian-Hsing Lee , Shui-Hung Chen
发明人： Yi-Hsun Wu , Jian-Hsing Lee , Shui-Hung Chen
IPC分类号： H02H9/00
CPC分类号： H01L27/0266 , H01L2924/0002 , H01L2924/00
摘要： Input/output devices with robustness of ESD protection are provided. An input/output device comprises an input/output pad, a first NMOS transistor, a second NMOS transistor and an ESD detector. The first NMOS transistor comprises a first drain, a first source and a first gate, wherein the first source and the first gate are coupled to a first ground power rail, and the first drain to the input/output pad. The second NMOS transistor comprises a second drain, a second source and a second gate, wherein the second source is coupled to the first ground power rail, the second drain to the input/output pad, and the second gate to a first pre-driver. When an ESD event is detected, the ESD detector makes the first pre-driver couple the second gate to the first ground power rail, thereby the first and second transistors evenly discharge ESD current.

6. 发明申请

US20050254189A1 ESD protection circuit with low parasitic capacitance 审中-公开
标题翻译：具有低寄生电容的ESD保护电路
公开(公告)号：US20050254189A1
公开(公告)日：2005-11-17
申请号：US11091131
申请日：2005-03-28
申请人： Yi-Hsun Wu , Jian-Hsing Lee
发明人： Yi-Hsun Wu , Jian-Hsing Lee
IPC分类号： G01R27/02 , G11C17/16 , G11C17/18 , H01L27/02 , H01L29/00 , H01L29/74 , H02H9/00
CPC分类号： H01L27/0262 , G11C17/16 , G11C17/18 , H01L29/7436
摘要： An ESD protection circuit includes a silicon controlled rectifier coupled between a circuit pad and ground for bypassing an ESD current from the circuit pad during an ESD event. An MOS transistor, having a source shared with the silicon controlled rectifier, is coupled between the pad and ground for reducing a trigger voltage of the silicon controlled rectifier during the ESD event. The silicon controlled rectifier has a first diode serially connected to a second diode in an opposite direction, between the pad and the shared source of the MOS transistor, for functioning as a bipolar transistor. In a layout view, a first area for placement of the first and second diodes is interposed between at least two separate sets of second areas for placement of the MOS transistor.
摘要翻译： ESD保护电路包括耦合在电路焊盘和地之间的可控硅整流器，用于在ESD事件期间旁路来自电路板的ESD电流。具有与可控硅整流器共享的源极的MOS晶体管耦合在焊盘和地之间，以在ESD事件期间降低可控硅整流器的触发电压。可控硅整流器具有在与MOS晶体管的焊盘和共享源之间的相反方向上串联连接到第二二极管的第一二极管，用作双极晶体管。在布局图中，用于放置第一和第二二极管的第一区域介于至少两个分开的第二区域组之间，用于放置MOS晶体管。

7. 发明申请

US20050237682A1 Novel ESD protection scheme for core devices 审中-公开
标题翻译：核心器件的新型ESD保护方案
公开(公告)号：US20050237682A1
公开(公告)日：2005-10-27
申请号：US10831897
申请日：2004-04-26
申请人： Yi-Hsun Wu , Jian-Hsing Lee
发明人： Yi-Hsun Wu , Jian-Hsing Lee
IPC分类号： H01L27/02 , H02H9/00
CPC分类号： H01L27/0266
摘要： A circuit and a method for solving the general problem of protecting core devices in integrated circuits from electrostatic discharge damage is provided. This circuit and a method prevents ESD voltage breakdown of thin oxide field effect transistors which are directly connected to the core Vdd power supply. The embodiments of this invention use inverter buffers using a thick or thin oxide devices at the input to the core circuitry is to be protected. Other embodiments of this invention use pass transistor or transfer gates made with thick or thin oxide devices at the input to the core circuitry is to be protected.
摘要翻译：提供了解决集成电路中的核心器件保护静电放电损坏的一般问题的电路和方法。该电路和方法防止直接连接到核心Vdd电源的薄氧化物场效应晶体管的ESD电压击穿。使用在核心电路的输入端使用厚或薄的氧化物装置的逆变器缓冲器的保护。本发明的其它实施例使用传输晶体管或由厚或薄的氧化物器件制成的传输栅极在核心电路的输入端被保护。

8. 发明授权

US06784498B1 Low capacitance ESD protection device and integrated circuit including the same 有权
标题翻译：低电容ESD保护器件和集成电路包括相同
公开(公告)号：US06784498B1
公开(公告)日：2004-08-31
申请号：US10403976
申请日：2003-03-31
申请人： Jian-Hsing Lee , Yi-Hsun Wu
发明人： Jian-Hsing Lee , Yi-Hsun Wu
IPC分类号： H01L2362
CPC分类号： H01L27/0262 , H01L29/0692 , H01L29/87
摘要： A low capacitance ESD protection device. The device comprises a substrate, a well of a first conductivity type in the substrate, a first and second transistor of the first conductivity type respectively on two sides of the well, a guard ring of a second conductivity type in the substrate, surrounding the well, and the first and second transistor, and a doped region of the second conductivity type in the well, wherein profiles of a drain and source region of each of the first and second transistor are un-symmetrical.
摘要翻译：低电容ESD保护器件。该器件包括衬底，衬底中的第一导电类型的阱，分别在阱的两侧上的第一导电类型的第一和第二晶体管，衬底中的第二导电类型的保护环，围绕阱以及第一和第二晶体管，以及阱中的第二导电类型的掺杂区域，其中第一和第二晶体管中的每一个的漏极和源极区域的剖面是不对称的。

9. 发明授权

US06703663B1 CMOS device using additional implant regions to enhance ESD performance and device manufactured thereby 有权
标题翻译： CMOS器件使用额外的注入区域来增强ESD性能，并由此制造器件
公开(公告)号：US06703663B1
公开(公告)日：2004-03-09
申请号：US09655086
申请日：2000-09-05
申请人： Jian-Hsing Lee , Yi-Hsun Wu , Jian-Ren Shih
发明人： Jian-Hsing Lee , Yi-Hsun Wu , Jian-Ren Shih
IPC分类号： H01L2976
CPC分类号： H01L29/7833 , H01L21/823814 , H01L27/0266 , H01L29/1083
摘要： A method of forming a semiconductor memory device formed on a semiconductor substrate with an N-well and a P-well comprises the following steps. Form over a substrate the combination of a gate oxide layer and a gate layer patterned into gate stacks with sidewalls for an NMOS FET device over a P-well in the substrate and a PMOS FET device over an N-well. Form P− lightly doped S/D regions in the N-well and N− lightly doped S/D regions in the P-well. Form spacers on the sidewalls of the gate stacks. Thereafter form deep N− lightly doped S/D regions in the P-well, and form deep P− lightly doped S/D regions in the N-well. Form heavily doped P++ regions self-aligned with the gate below future P+ S/D sites to be formed self-aligned with the spacers in the N-well, and form heavily doped N++ regions self-aligned with the gate below future N+ S/D sites to be formed self-aligned with the spacers in the P-well.
摘要翻译：用N阱和P阱形成在半导体衬底上的半导体存储器件的形成方法包括以下步骤。在衬底上形成栅极氧化物层和栅极层的组合，栅极层与衬底中的P阱上的NMOS FET器件的侧壁和N阱上的PMOS FET器件构图成栅极堆叠。在P阱中的N阱和N-轻掺杂的S / D区中形成P-轻掺杂的S / D区。在栅极堆叠的侧壁上形成间隔物。然后在P阱中形成深N轻掺杂的S / D区，并在N阱中形成深P-轻掺杂的S / D区。形成与未来P + S / D位置下方的栅极自对准的重掺杂P ++区域，以与N阱中的间隔物自对准，并形成与未来N + S / D的栅极自对准的重掺杂N ++区域， D点与P阱中的间隔物自对准。

10. 发明授权

US06682993B1 Effective Vcc to Vss power ESD protection device 有权
标题翻译：有效Vcc至Vss电源ESD保护装置
公开(公告)号：US06682993B1
公开(公告)日：2004-01-27
申请号：US10161007
申请日：2002-05-31
申请人： Yi-Hsun Wu , Jian-Hsing Lee
发明人： Yi-Hsun Wu , Jian-Hsing Lee
IPC分类号： H01L2104
CPC分类号： H01L27/0266
摘要： The invention consists of an ESD protection discharging NMOS with a special drain dopant region that enables a lower voltage trigger point for Vcc to Vss ESD power protection. To enable this ESD protection, the NMOS source connected to a first voltage bus line, or Vcc, and the drain is connected to a second voltage bus line, or ground. The NMOS device gate is connected to ground through a difflused resistor assuring the device remains in an off state during normal operation. The unique invention special dopant region is located under and around the NMOS drain which lowers the drain to substrate breakdown voltage enabling the ESD protection current discharge to start at a lower voltage than otherwise. This feature reduces voltage stress on the gates of active devices being protected, and enables higher ESD current discharges at the same power level as for devices without the special drain dopant region.
摘要翻译：本发明包括具有特殊漏极掺杂剂区域的ESD保护放电NMOS，其能够实现用于Vcc至Vss ESD功率保护的较低电压触发点。为了实现该ESD保护，连接到第一电压总线或Vcc的NMOS源和漏极连接到第二电压总线或地。 NMOS器件栅极通过差分电阻器连接到地，确保器件在正常工作期间保持关断状态。独特的发明特殊掺杂剂区域位于NMOS漏极的下面和周围，这降低了漏极到衬底的击穿电压，使得ESD保护电流放电能够以比其他电压更低的电压开始。该特性降低了受保护的有源器件的栅极上的电压应力，并且能够实现与没有特殊漏极掺杂剂区域的器件相同功率电平的更高的ESD电流放电。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式