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1. 发明授权

US5903499A Method to erase a flash EEPROM using negative gate source erase followed by a high negative gate erase 失效
标题翻译：使用负栅极源擦除后跟高负栅极擦除擦除闪存EEPROM的方法
公开(公告)号：US5903499A
公开(公告)日：1999-05-11
申请号：US928227
申请日：1997-09-12
申请人： Kuo-Reay Peng , Jian-Hsing Lee , Juang-Ke Yeh , Ming-Chou Ho
发明人： Kuo-Reay Peng , Jian-Hsing Lee , Juang-Ke Yeh , Ming-Chou Ho
IPC分类号： G11C16/14 , G11C16/04
CPC分类号： G11C16/14
摘要： A method to erase data from a flash EEPROM while electrical charges trapped in the tunneling oxide of a flash EEPROM are eliminated to maintain proper separation of the programmed threshold voltage and the erased threshold voltage after extended programming and erasing cycles. The method to erase a flash EEPROM cell begins by first applying a moderately high positive voltage pulse to the source of the EEPROM cell. Simultaneously, a first relatively large negative voltage is applied to the control gate. While a ground reference potential is applied to the semiconductor substrate. At this same time the drain is floating. The flash EEPROM cell is then detrapped by floating the source and drain and applying the ground reference potential to the semiconductor substrate. At the same time a second relatively large negative voltage pulse is applied to the control gate.
摘要翻译：一种在闪存EEPROM的隧道氧化物中捕获电荷的情况下从闪存EEPROM擦除数据的方法被消除，以便在扩展编程和擦除周期之后保持编程阈值电压和擦除阈值电压的适当分离。擦除快闪EEPROM单元的方法是首先向EEPROM单元的源极施加适度高的正电压脉冲。同时，向控制栅极施加第一相对较大的负电压。同时对半导体衬底施加接地参考电位。在同一时间，排水沟漂浮。然后通过漂浮源极和漏极并将接地参考电位施加到半导体衬底来去除快闪EEPROM单元。同时，向控制栅极施加第二相对大的负电压脉冲。

2. 发明授权

US6049484A Erase method to improve flash EEPROM endurance by combining high voltage source erase and negative gate erase 有权
标题翻译：擦除方法通过组合高电压源擦除和负栅极擦除来提高闪存EEPROM的耐久性
公开(公告)号：US6049484A
公开(公告)日：2000-04-11
申请号：US150907
申请日：1998-09-10
申请人： Jian-Hsing Lee , Kuo-Reay Peng , Juang-Ke Yeh , Ming-Chou Ho
发明人： Jian-Hsing Lee , Kuo-Reay Peng , Juang-Ke Yeh , Ming-Chou Ho
IPC分类号： G11C16/14 , G11C16/04
CPC分类号： G11C16/14
摘要： A method to erase data from a flash EEPROM is disclosed. Electrical charges trapped in the tunneling oxide of a flash EEPROM are eliminated to maintain proper separation of the programmed threshold voltage and the erased threshold voltage after extended programming and erasing cycles. The method to erase a flash EEPROM cell begins by erasing the flash EEPROM cell by first applying a high positive voltage pulse to the source of the EEPROM cell. Simultaneously, a ground reference potential is applied to the semiconductor substrate and the control gate. At this same time the drain is floating. Floating the source and drain and applying the ground reference potential to the semiconductor substrate then detraps the flash EEPROM cell. At the same time, a relatively large negative voltage pulse is applied to the control gate.
摘要翻译：公开了一种从闪存EEPROM擦除数据的方法。消除了捕获在闪速EEPROM的隧穿氧化物中的电荷，以在扩展编程和擦除周期之后保持编程的阈值电压和擦除的阈值电压的适当分离。通过首先向EEPROM单元的源施加高正电压脉冲，擦除快闪EEPROM单元开始擦除快闪EEPROM单元的方法。同时，对半导体衬底和控制栅极施加接地参考电位。在同一时间，排水沟漂浮。将源极和漏极浮置并将接地参考电位施加到半导体衬底，然后去除快闪EEPROM单元。同时，向控制栅极施加相对较大的负电压脉冲。

3. 发明授权

US5726933A Clipped sine shaped waveform to reduce the cycling-induced electron trapping in the tunneling oxide of flash EEPROM 失效
标题翻译：剪切正弦波形，以减少快速EEPROM的隧道氧化物中的循环诱导电子捕获
公开(公告)号：US5726933A
公开(公告)日：1998-03-10
申请号：US857162
申请日：1997-05-15
申请人： Jian-Hsing Lee , Kuo-Reay Peng , Juang-Ke Yeh , Ming-Chou Ho
发明人： Jian-Hsing Lee , Kuo-Reay Peng , Juang-Ke Yeh , Ming-Chou Ho
IPC分类号： G11C16/10 , G11C16/14 , G11C16/06
CPC分类号： G11C16/14 , G11C16/10
摘要： The present invention provides method to erase and program flash EEPROMS devices using a clipped sine waveform (Vg). The clipped sine waveform reduces the tunneling oxide electric field between the floating gate and the source or drain region thereby reducing electron trapping. The method for the erase cycle comprises: applying a positive voltage to a source region; grounding a well region; floating the drain region; and simultaneously applying a negative clipped sine waveform voltage to a control gate during the erase cycle. The program cycle of the invention comprises: applying a voltage to a drain region; grounding a well region; floating a source region; and simultaneously applying a clipped sine waveform voltage to the control gate whereby the clipped sine waveforms reduce the electric field in a tunnel oxide layer which reduces the electron trapping.
摘要翻译：本发明提供了使用限幅正弦波形（Vg）擦除和编程闪存EEPROMS设备的方法。限幅正弦波形减少了浮动栅极和源极或漏极区域之间的隧道氧化物电场，从而减少了电子俘获。擦除周期的方法包括：向源极区域施加正电压; 接地井区; 漂浮漏极区; 并且在擦除周期期间同时向控制栅极施加负的限幅正弦波形电压。本发明的程序循环包括：向漏区施加电压; 接地井区; 浮动源区; 并且同时向限制栅极施加限幅正弦波形电压，由此限幅正弦波形减少隧道氧化物层中的电场，从而减少电子捕获。

4. 发明授权

US6055183A Erase method of flash EEPROM by using snapback characteristic 失效
标题翻译：通过使用快速恢复特性擦除闪存EEPROM的方法
公开(公告)号：US6055183A
公开(公告)日：2000-04-25
申请号：US957678
申请日：1997-10-24
申请人： Ming-Chou Ho , Jian-Hsing Lee , Kuo-Reay Peng , Juang-Ke Yeh
发明人： Ming-Chou Ho , Jian-Hsing Lee , Kuo-Reay Peng , Juang-Ke Yeh
IPC分类号： G11C16/16 , G11C16/04
CPC分类号： G11C16/16
摘要： A method to erase data from a flash EEPROM while electrical charges trapped in the tunneling oxide of a flash EEPROM are eliminated to maintain proper separation of the programmed threshold voltage and the erased threshold voltage after extended programming and erasing cycles, while preventing damage due to high field stress in the tunneling oxide. The method to erase a flash EEPROM cell begins by applying a relatively high positive voltage pulse to the source of the EEPROM cell. Simultaneously a ground reference voltage is applied to the drain and to the semiconductor substrate. At the same time a relatively large negative voltage pulse is applied to the control gate. This will cause a parasitic bipolar transistor to conduct and go into a snap back condition reducing the voltage field in the tunneling oxide.
摘要翻译：在快速EEPROM的隧道氧化物中捕获电荷的同时消除闪存EEPROM中的数据的方法，以便在扩展编程和擦除周期之后保持编程阈值电压和擦除阈值电压的适当分离，同时防止由于高隧道氧化物中的场应力。擦除快闪EEPROM单元的方法是通过向EEPROM单元的源极施加相对高的正电压脉冲开始的。同时，对漏极和半导体衬底施加接地参考电压。同时，向控制栅极施加相当大的负电压脉冲。这将导致寄生双极晶体管导通并进入快速恢复条件，从而减少隧道氧化物中的电压场。

5. 发明授权

US06303454B1 Process for a snap-back flash EEPROM cell 有权
标题翻译：闪存快闪EEPROM单元的处理
公开(公告)号：US06303454B1
公开(公告)日：2001-10-16
申请号：US09590849
申请日：2000-06-09
申请人： Juang-Ker Yeh , Jian-Hsing Lee , Kuo-Reay Peng , Ming-Chou Ho
发明人： Juang-Ker Yeh , Jian-Hsing Lee , Kuo-Reay Peng , Ming-Chou Ho
IPC分类号： H01L21336
CPC分类号： H01L29/66825 , G11C16/14 , H01L21/28273 , H01L29/7885
摘要： The present invention provides method to fabricate a snap-back flash EEPROMS device. The method begins by forming a gate structure 22 24 28 26 on a substrate. The gate structure comprises: a tunnel oxide layer 22, a floating gate 24, integrate dielectric layer 28, and a control gate 26. A drain 14 is formed adjacent to the gate structure by an masking 51 and ion implant process. Next, a source side doped region 18 is formed adjacent to and under a portion of the gate structure 22 24 28 26 by an masking and ion implant process. Spacers 32 are now formed on the sidewalls of the gate structure. A source 20 is formed overlapping portion of the side source doped region 18 and adjacent to the spacers 32. The side source doped region has a lower dopant concentration than the source 20. This method forms a snap-back memory cell wherein the side source doped region 18 is used to apply a high voltage to operate the EEPROM cell in a snap-back erase mode.
摘要翻译：本发明提供了制造快速闪存EEPROMS设备的方法。该方法开始于在衬底上形成栅极结构22 24 28 26。栅极结构包括：隧道氧化物层22，浮置栅极24，整合电介质层28和控制栅极26.漏极14通过掩模51和离子注入工艺邻近栅极结构形成。接下来，通过掩模和离子注入工艺在栅极结构22 24 28 26的一部分附近形成源极侧掺杂区18。隔板32现在形成在栅极结构的侧壁上。源极20形成在侧面源极掺杂区域18的重叠部分并且与间隔物32相邻。源极掺杂区域具有比源极20更低的掺杂剂浓度。该方法形成一个回写式存储器单元，其中侧面源掺杂区域18用于施加高电压以快速擦除模式操作EEPROM单元。

6. 发明授权

US5949717A Method to improve flash EEPROM cell write/erase threshold voltage closure 失效
标题翻译：快速EEPROM单元写/擦除阈值电压关闭的方法
公开(公告)号：US5949717A
公开(公告)日：1999-09-07
申请号：US928217
申请日：1997-09-12
申请人： Ming-Chou Ho , Juang-ker Yeh , Jian-Hsing Lee , Kuo-Reay Peng
发明人： Ming-Chou Ho , Juang-ker Yeh , Jian-Hsing Lee , Kuo-Reay Peng
IPC分类号： G11C16/16 , G11C16/04
CPC分类号： G11C16/16
摘要： A method to erase data from a flash EEPROM cell while electrical charges trapped in the tunnel oxide of a flash EEPROM cell are eliminated to maintain proper separation of the programmed threshold voltage and the erased threshold voltage after extended programming and erasing cycles. The method to erase a flash EEPROM cell begins by first applying a first relatively high positive voltage pulse to the source of the flash EEPROM cell. Simultaneously a ground reference voltage is applied to the control gate and to the semiconductor substrate. At this same time the drain is floating. The flash EEPROM cell is then detrapped by floating the source and drain and applying a second relatively high positive voltage pulse to the semiconductor substrate. At the same time a relatively large negative voltage pulse is applied to the control gate.
摘要翻译：在快速EEPROM单元的隧道氧化物中捕获电荷的同时消除闪存EEPROM单元中的数据的方法，以在扩展的编程和擦除周期之后保持编程的阈值电压和擦除的阈值电压的适当分离。擦除快闪EEPROM单元的方法首先是将第一相对较高的正电压脉冲施加到闪速EEPROM单元的源。同时，对控制栅极和半导体衬底施加接地参考电压。在同一时间，排水沟漂浮。然后通过漂浮源极和漏极并将第二相对高的正电压脉冲施加到半导体衬底来去除快闪EEPROM单元。同时，向控制栅极施加相当大的负电压脉冲。

7. 发明授权

US5838618A Bi-modal erase method for eliminating cycling-induced flash EEPROM cell write/erase threshold closure 失效
标题翻译：用于消除循环感应闪速EEPROM单元写入/擦除阈值闭合的双模式擦除方法
公开(公告)号：US5838618A
公开(公告)日：1998-11-17
申请号：US927472
申请日：1997-09-11
申请人： Jian-Hsing Lee , Juang-Ker Yeh , Kuo-Reay Peng , Ming-Chou Ho
发明人： Jian-Hsing Lee , Juang-Ker Yeh , Kuo-Reay Peng , Ming-Chou Ho
IPC分类号： G11C16/14 , G11C16/04 , G11C7/00
CPC分类号： G11C16/14
摘要： A method to erase data from a flash EEPROM while electrical charges trapped in the tunneling oxide of a flash EEPROM are eliminated to maintain proper separation of the programmed threshold voltage and the erased threshold voltage after extended programming and erasing cycles. The method to erase a flash EEPROM cell begins by channel erasing to remove charge from the floating gate of the flash EEPROM cell. The channel erasing consists of applying a first relatively large negative voltage pulse to the control gate of said EEPROM cell and concurrently applying a first moderately large positive voltage pulse to a first diffusion well. At the same time a ground reference potential is applied to the semiconductor substrate, while the drain and a second diffusion well is allowed to float. The method to erase then proceeds with the source erasing to detrap the tunneling oxide of the flash EEPROM cell. The source erasing consists continued floating the drain and the second diffusion well and concurrently applying the ground reference potential to the semiconductor substrate and the first diffusion well. Concurrently a second relatively large negative voltage pulse is applied to the control gate, as a second moderately large positive voltage pulse is applied to said source.
摘要翻译：一种在闪存EEPROM的隧道氧化物中捕获电荷的情况下从闪存EEPROM擦除数据的方法被消除，以便在扩展编程和擦除周期之后保持编程阈值电压和擦除阈值电压的适当分离。擦除闪存EEPROM单元的方法是从通道擦除开始，以从闪存EEPROM单元的浮动栅极去除电荷。通道擦除包括将第一相对较大的负电压脉冲施加到所述EEPROM单元的控制栅并且同时向第一扩散阱施加第一适度大的正电压脉冲。同时，对半导体衬底施加接地参考电位，同时使漏极和第二扩散阱浮动。擦除的方法然后继续进行源擦除以去除快速EEPROM单元的隧穿氧化物。源擦除继续浮置漏极和第二扩散阱，同时将接地参考电位施加到半导体衬底和第一扩散阱。同时，向控制栅极施加第二相对较大的负电压脉冲，因为向所述源施加第二适度大的正电压脉冲。

8. 发明授权

US5862078A Mixed mode erase method to improve flash eeprom write/erase threshold closure 失效
标题翻译：混合模式擦除方法来改善闪存eeprom写/擦除阈值关闭
公开(公告)号：US5862078A
公开(公告)日：1999-01-19
申请号：US907984
申请日：1997-08-11
申请人： Juang-Ker Yeh , Jian-Hsing Lee , Kuo-Reay Peng , Ming-Chou Ho
发明人： Juang-Ker Yeh , Jian-Hsing Lee , Kuo-Reay Peng , Ming-Chou Ho
IPC分类号： G11C16/14 , G11C16/34 , G11C16/04
CPC分类号： G11C16/14 , G11C16/349
摘要： A method to erase data from a flash EEPROM while electrical charges trapped in the tunneling oxide of a flash EEPROM are eliminated to maintain proper separation of the programmed threshold voltage and the erased threshold voltage after extended programming and erasing cycles. The method to erase a flash EEPROM cell begins by channel erasing to detrap the tunneling oxide of the flash EEPROM cell. The channel erasing consists floating the drain and the second diffusion well and concurrently applying the ground reference potential to the semiconductor substrate and the first diffusion well. Concurrently a first relatively large negative voltage pulse is applied to the control gate, as a first moderately large positive voltage pulse is applied to said source. The method to erase then proceeds with the source erasing to remove charges from the floating gate of the flash EEPROM cell. The source erasing consists of applying a second relatively large negative voltage pulse to the control gate of said EEPROM cell and concurrently applying a second moderately large positive voltage pulse to a first diffusion well. At the same time the ground reference potential continues to be applied to the semiconductor substrate, while the drain and a second diffusion well is allowed to float.
摘要翻译：一种在闪存EEPROM的隧穿氧化物中捕获电荷的情况下从闪存EEPROM擦除数据的方法被消除，以便在扩展编程和擦除周期之后保持编程阈值电压和擦除阈值电压的适当分离。擦除快闪EEPROM单元的方法是通过通道擦除来消除快速EEPROM单元的隧道氧化物。通道擦除包括使漏极和第二扩散阱浮置，同时将接地参考电位施加到半导体衬底和第一扩散阱。同时，第一相对较大的负电压脉冲施加到控制栅极，因为第一适度大的正电压脉冲被施加到所述源极。擦除方法随后进行源擦除以从快闪EEPROM单元的浮动栅极去除电荷。源擦除包括将第二相对较大的负电压脉冲施加到所述EEPROM单元的控制栅并且向第一扩散阱同时施加第二适度大的正电压脉冲。同时，接地参考电位继续施加到半导体衬底，同时漏极和第二扩散阱被允许浮动。

9. 发明申请

US20070296034A1 SILICON-ON-INSULATOR (SOI) MEMORY DEVICE 审中-公开
标题翻译：绝缘体绝缘体（SOI）存储器件
公开(公告)号：US20070296034A1
公开(公告)日：2007-12-27
申请号：US11759949
申请日：2007-06-08
申请人： Hsin-Ming Chen , Shih-Chen Wang , Ming-Chou Ho , Shih-Jye Shen
发明人： Hsin-Ming Chen , Shih-Chen Wang , Ming-Chou Ho , Shih-Jye Shen
IPC分类号： H01L27/12
CPC分类号： H01L27/1203 , H01L27/0207 , H01L27/115 , H01L27/11519 , H01L27/11521 , H01L27/11524 , H01L27/11558
摘要： A single-poly SOI memory cell includes a PMOS select transistor serially connected with a floating-gate PMOS transistor on an SOI substrate. The PMOS select transistor includes a select gate, a P+ source region and a P+ drain/source region. The floating-gate PMOS transistor includes a floating gate, a P+ drain region and the P+ drain/source region, wherein the P+ drain/source region is shared by the PMOS select transistor and the floating-gate PMOS transistor. A floating first N+ doping region is disposed within the P+ drain/source region. The first N+ doping region, which is adjacent to the floating gate, acts as a source-tie pick-up.
摘要翻译：单多晶硅存储单元包括与SOI衬底上的浮栅PMOS晶体管串联连接的PMOS选择晶体管。 PMOS选择晶体管包括选择栅极，P + SUP源极区和P + SUP漏极/源极区。浮置栅极PMOS晶体管包括浮置栅极，漏极和漏极区域，其中P + 漏极/源极区域由PMOS选择晶体管和浮置栅极PMOS晶体管共享。漂浮的第一N + +掺杂区域设置在漏极/源极区域内。与浮动栅极相邻的第一N + H + +掺杂区充当源极接头。

10. 发明申请

US20070296018A1 NONVOLATILE SINGLE-POLY MEMORY DEVICE 有权
标题翻译：非易失性单晶存储器件
公开(公告)号：US20070296018A1
公开(公告)日：2007-12-27
申请号：US11690861
申请日：2007-03-26
申请人： Hsin-Ming Chen , Shih-Chen Wang , Ming-Chou Ho , Shih-Jye Shen
发明人： Hsin-Ming Chen , Shih-Chen Wang , Ming-Chou Ho , Shih-Jye Shen
IPC分类号： H01L29/788
CPC分类号： H01L27/11521 , H01L27/115 , H01L27/11519 , H01L27/11558
摘要： A non-volatile single-poly memory device is disclosed. The non-volatile single-poly memory device includes two mirror symmetric unit cells, which is capable of providing improved data correctness. Further, the non-volatile single-poly memory device is operated at low voltages and is fully compatible with logic processes.
摘要翻译：公开了一种非易失性单多晶硅存储器件。非易失性单多晶硅存储器件包括两个镜像对称单元单元，其能够提供改进的数据正确性。此外，非易失性单多晶硅存储器件在低电压下操作并且与逻辑工艺完全兼容。

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