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81. 发明授权

US06825692B1 Input buffer for multiple differential I/O standards 有权
标题翻译：用于多个差分I / O标准的输入缓冲器
公开(公告)号：US06825692B1
公开(公告)日：2004-11-30
申请号：US10056367
申请日：2002-01-25
申请人： Jonathan Chung , In Whan Kim , Philip Pan , Chiakang Sung , Bonnie Wang , Xiaobao Wang , Yan Chong , Gopinath Rangan , Khai Nguyen , Tzung-Chin Chang , Joseph Huang
发明人： Jonathan Chung , In Whan Kim , Philip Pan , Chiakang Sung , Bonnie Wang , Xiaobao Wang , Yan Chong , Gopinath Rangan , Khai Nguyen , Tzung-Chin Chang , Joseph Huang
IPC分类号： H03K190175
CPC分类号： H03K19/018585
摘要： An input buffer circuit has a plurality of selectively enabled differential amplifier circuits, where each differential amplifier is configured for compatibility with a particular differential I/O standard and its corresponding input operating range. For example, the input buffer may have two differential amplifiers suitable for receiving LVDS differential input signals over a wide input operating range, and another differential amplifier suitable for receiving the PCML differential input signals. One or more control signals are provided to the input buffer, e.g., programmably, to selectively enable the required differential amplifier(s) for a given I/O standard.
摘要翻译：输入缓冲器电路具有多个选择性启用的差分放大器电路，其中每个差分放大器被配置为与特定差分I / O标准及其对应的输入工作范围兼容。例如，输入缓冲器可以具有适合于在宽输入工作范围内接收LVDS差分输入信号的两个差分放大器，以及适合于接收PCML差分输入信号的另一差分放大器。一个或多个控制信号例如可编程地提供给输入缓冲器，以选择性地启用给定的I / O标准所需的差分放大器。

82. 发明授权

US06747903B1 Configurable decoder for addressing a memory 有权
标题翻译：用于寻址存储器的可配置解码器
公开(公告)号：US06747903B1
公开(公告)日：2004-06-08
申请号：US10046939
申请日：2002-01-14
申请人： Philip Y. Pan , Chiakang Sung , Joseph Huang , Bonnie Wang , Khai Nguyen , Xiaobao Wang , Gopinath Rangan , In Whan Kim , Yan Chong , Tzung-Chin Chang
发明人： Philip Y. Pan , Chiakang Sung , Joseph Huang , Bonnie Wang , Khai Nguyen , Xiaobao Wang , Gopinath Rangan , In Whan Kim , Yan Chong , Tzung-Chin Chang
IPC分类号： G11C700
CPC分类号： H03K19/1776 , G11C8/16
摘要： Methods and apparatus for decoding addresses in a memory to provide mixed input and output data widths. A method includes receiving an address portion comprising a first number of bits. A second number of bits of the address portion are blocked, where the second number is less than the first number. A third number of bits are not blocked, and the third number plus the second number equal the first number. The third number of bits are decoded and a fourth number of memory cells are selected. The fourth number is equal to two to the power of the second number. A fourth number of data bits are received and multiplexed to the selected memory cells. The data bits are written to the selected memory cells.
摘要翻译：用于解码存储器中的地址以提供混合的输入和输出数据宽度的方法和装置。一种方法包括接收包括第一位数的地址部分。地址部分的第二位数被阻塞，其中第二个数字小于第一个数字。第三个位数不被阻塞，第三个数字加上第二个数字等于第一个数字。第三位数被解码，并且选择第四数量的存储单元。第四个数字等于第二个数字的两倍。接收第四数量的数据位并将其多路复用到选择的存储单元。数据位被写入选定的存储单元。

83. 发明授权

US06433579B1 Programmable logic integrated circuit devices with differential signaling capabilities 有权
标题翻译：具有差分信号功能的可编程逻辑集成电路器件
公开(公告)号：US06433579B1
公开(公告)日：2002-08-13
申请号：US09863143
申请日：2001-05-22
申请人： Bonnie I. Wang , Chiakang Sung , Yan Chong , Philip Pan , Khai Nguyen , Joseph Huang , Xiaobao Wang , In Whan Kim , Gopinath Rangan
发明人： Bonnie I. Wang , Chiakang Sung , Yan Chong , Philip Pan , Khai Nguyen , Joseph Huang , Xiaobao Wang , In Whan Kim , Gopinath Rangan
IPC分类号： H03K19177
CPC分类号： H03K19/17744 , H03K19/018521 , H03K19/1778 , H03K19/17784 , H03K19/17792
摘要： A programmable logic device is equipped for various differential signaling schemes by providing a differential output buffer on the device that can be configured according to the needs of the particular differential signaling schemes that may be used. The buffer includes a differential output driver, an adjustable current limiting circuit between the supply voltage and the differential output driver, and an adjustable current limiting circuit between the differential output driver and ground. By selectively adjusting the two current limiting circuits, the output impedance and current, as well as the common mode output voltage and the differential output voltage can be controlled.
摘要翻译：通过在设备上提供可根据可能使用的特定差分信令方案的需要进行配置的差分输出缓冲器，为各种差分信令方案配备了可编程逻辑器件。缓冲器包括差分输出驱动器，电源电压和差分输出驱动器之间的可调节限流电路，以及差分输出驱动器和地之间的可调电流限制电路。通过选择性地调节两个限流电路，可以控制输出阻抗和电流，以及共模输出电压和差分输出电压。

84. 发明授权

US07309906B1 Apparatus and methods for providing highly effective and area efficient decoupling capacitance in programmable logic devices 有权
标题翻译：用于在可编程逻辑器件中提供高效和区域有效的去耦电容的装置和方法
公开(公告)号：US07309906B1
公开(公告)日：2007-12-18
申请号：US11097503
申请日：2005-04-01
申请人： Jeffrey Tyhach , Bonnie I Wang , Yan Chong , Chiakang Sung
发明人： Jeffrey Tyhach , Bonnie I Wang , Yan Chong , Chiakang Sung
IPC分类号： H01L29/00 , H01L21/8242
CPC分类号： H01L29/94 , H01L27/0203
摘要： Improved decoupling capacitor designs and layout schemes are provided that generate high effective capacitance and high area efficiency at higher frequencies than that of previously known decoupling capacitor designs. The improved decoupling capacitor designs utilize transistor gates with shorter channel lengths to reduce the total parasitic resistance of the channel, thereby providing higher effective capacitance at higher frequencies. To enable higher area efficiency of this decoupling capacitor design, excess contacts are replaced with polysilicon in a grid or waffle pattern.
摘要翻译：提供了改进的去耦电容器设计和布局方案，其在比先前已知的去耦电容器设计更高的频率下产生高有效电容和高的面积效率。改进的去耦电容器设计利用具有较短沟道长度的晶体管栅极来减小沟道的总寄生电阻，从而在较高频率下提供更高的有效电容。为了实现该去耦电容器设计的更高的面积效率，多余的触点被以栅格或华夫饼形式的多晶硅替代。

85. 发明申请

US20060220703A1 Programmable high speed interface 有权
标题翻译：可编程高速接口
公开(公告)号：US20060220703A1
公开(公告)日：2006-10-05
申请号：US11446483
申请日：2006-06-02
申请人： Bonnie Wang , Chiakang Sung , Joseph Huang , Khai Nguyen , Philip Pan
发明人： Bonnie Wang , Chiakang Sung , Joseph Huang , Khai Nguyen , Philip Pan
IPC分类号： H03B1/00
CPC分类号： H03K19/17744 , H03K19/0175 , H03K19/017509 , H03K19/017581 , H03K19/1774 , H03K19/17788
摘要： Methods and apparatus for providing either high-speed, or lower-speed, flexible inputs and outputs. An input and output structure having a high-speed input, a high-speed output, a low or moderate speed input, and an low or moderate speed output is provided. One of the input and output circuits are selected and the others are deselected. The high-speed input and output circuits are comparatively simple, in one example having only a clear signal for a control line input, and are able to interface to lower speed circuitry inside the core of an integrated circuit. The low or moderate speed input and output circuits are more flexible, for example, having preset, enable, and clear as control line inputs, and are able to support JTAG boundary testing. These parallel high and lower speed circuits are user selectable such that the input output structure is optimized between speed and functionality depending on the requirements of the application.
摘要翻译：提供高速或低速灵活的输入和输出的方法和设备。提供具有高速输入，高速输出，低速或中速输入以及低速或中速输出的输入和输出结构。选择其中一个输入和输出电路，并取消选择其他电路。高速输入和输出电路相对简单，在一个示例中，仅具有用于控制线输入的清除信号，并且能够与集成电路的核心内的低速电路接口。低速或中速输入和输出电路比较灵活，例如具有预置，使能和清除作为控制线路输入，并且能够支持JTAG边界测试。这些并行高速和低速电路是用户可选择的，使得输入输出结构根据应用的要求在速度和功能之间进行优化。

86. 发明申请

US20050134332A1 Programmable high speed I/O interface 有权
标题翻译：可编程高速I / O接口
公开(公告)号：US20050134332A1
公开(公告)日：2005-06-23
申请号：US10886015
申请日：2004-07-06
申请人： Bonnie Wang , Chiakang Sung , Joseph Huang , Khai Nguyen , Philip Pan
发明人： Bonnie Wang , Chiakang Sung , Joseph Huang , Khai Nguyen , Philip Pan
IPC分类号： G06F3/00 , G06F13/38 , H03K19/0175 , H03K19/173 , H03K19/177 , H03K17/16
CPC分类号： H03K19/17744 , H03K19/0175 , H03K19/017509 , H03K19/017581 , H03K19/1774 , H03K19/17788
摘要： Methods and apparatus for providing either high-speed, or lower-speed, flexible inputs and outputs. An input and output structure having a high-speed input, a high-speed output, a low or moderate speed input, and an low or moderate speed output is provided. One of the input and output circuits are selected and the others are deselected. The high-speed input and output circuits are comparatively simple, in one example having only a clear signal for a control line input, and are able to interface to lower speed circuitry inside the core of an integrated circuit. The low or moderate speed input and output circuits are more flexible, for example, having preset, enable, and clear as control line inputs, and are able to support JTAG boundary testing. These parallel high and lower speed circuits are user selectable such that the input output structure is optimized between speed and functionality depending on the requirements of the application.
摘要翻译：提供高速或低速灵活的输入和输出的方法和设备。提供具有高速输入，高速输出，低速或中速输入以及低速或中速输出的输入和输出结构。选择其中一个输入和输出电路，并取消选择其他电路。高速输入和输出电路相对简单，在一个示例中，仅具有用于控制线输入的清除信号，并且能够与集成电路的核心内的低速电路接口。低速或中速输入和输出电路比较灵活，例如具有预置，使能和清除作为控制线路输入，并且能够支持JTAG边界测试。这些并行高速和低速电路是用户可选择的，使得输入输出结构根据应用的要求在速度和功能之间进行优化。

87. 再颁专利

USRE38651E1 Variable depth and width memory device 失效
标题翻译：可变深度和宽度的存储设备
公开(公告)号：USRE38651E1
公开(公告)日：2004-11-09
申请号：US09096917
申请日：1998-06-12
申请人： Chiakang Sung , Wanli Chang , Joseph Huang , Richard G. Cliff , L. Todd Cope , Cameron R. McClintock , William Leong , James A. Watson , Bahram Ahanin
发明人： Chiakang Sung , Wanli Chang , Joseph Huang , Richard G. Cliff , L. Todd Cope , Cameron R. McClintock , William Leong , James A. Watson , Bahram Ahanin
IPC分类号： G06F1200
CPC分类号： G11C8/12 , G01R31/318516
摘要： A programmable variable depth and width random-access memory circuit is provided. The memory circuit contains rows and columns of memory cells for storing data. A row decoder is used to address individual rows of the memory cells. Column address circuitry receives a column address signal and a width and depth selection signal. A column decoder within the column address circuitry addresses one or more columns of memory cells of the RAM array based on the selected width of the array. The output of the column decoder is routed to the appropriate column or columns of memory cells by a pattern of fixed connections and a group of programmable multiplexers. The number of data output lines to which data signals are provided is determined by the selected width of the RAM array. The output circuitry contains a group of programmable demultiplexers and a routing array having a pattern of fixed connections suitable for passing data signals from the RAM array to the selected number of data output lines.

88. 发明授权

US06535031B1 Programmable logic integrated circuit devices with low voltage differential signaling capabilities 有权
公开(公告)号：US06535031B1
公开(公告)日：2003-03-18
申请号：US10146438
申请日：2002-05-13
申请人： Khai Nguyen , Xiaobao Wang , In Whan Kim , Chiakang Sung , Richard G Cliff , Joseph Huang , Bonnie I Wang , Wayne Yeung
发明人： Khai Nguyen , Xiaobao Wang , In Whan Kim , Chiakang Sung , Richard G Cliff , Joseph Huang , Bonnie I Wang , Wayne Yeung
IPC分类号： H03K522
CPC分类号： H03K19/17744 , H03K19/018521 , H03K19/1778 , H03K19/17784
摘要： A programmable logic device is equipped for low voltage differential signaling (“LVDS”) by providing an LVDS input buffer and/or an LVDS output buffer on the device. I/O pins on the device that are used together in pairs for LVDS can alternatively be used individually for other types of signaling. The LVDS buffers are constructed to give good performance and to meet LVDS specifications despite variations due to temperature, manufacturing process inconsistency, and power supply changes.

89. 发明授权

US06384629B2 High-speed programmable interconnect 有权
标题翻译：高速可编程互连
公开(公告)号：US06384629B2
公开(公告)日：2002-05-07
申请号：US09738403
申请日：2000-12-15
申请人： Joseph Huang , Chiakang Sung , Bonnie I. Wang , Khai Nguyen , Xiaobao Wang , Richard G. Cliff
发明人： Joseph Huang , Chiakang Sung , Bonnie I. Wang , Khai Nguyen , Xiaobao Wang , Richard G. Cliff
IPC分类号： H01L2500
CPC分类号： H03K19/17736 , G01R31/318555 , G06F11/2273 , H03K19/17792
摘要： An improved interconnection between horizontal conductors and the input to logic elements. A signal regeneration circuit is provided in the path between the horizontal conductor and the logic element, thereby isolating and boosting the signal. This allows for faster switching operation. A path is provided allowing the selective routing of signals from the horizontal conductors to the vertical conductors, without passing through a logic element. Also, a path is provided to allow a horizontal conductors to be routed to any of a plurality of vertical conductors.
摘要翻译：水平导体与逻辑元件输入之间的互连改善。在水平导体和逻辑元件之间的路径中提供信号再生电路，从而隔离和升高信号。这允许更快的切换操作。提供路径，允许从水平导体到垂直导体的信号的选择性路由，而不通过逻辑元件。而且，提供了一种路径，以允许水平导体被路由到多个垂直导体中的任何一个。

90. 发明授权

US06246270B1 Innovated AC kicker for high speed low voltage swing differential output buffer with temperature compensation 有权
标题翻译：用于具有温度补偿功能的高速低电压摆幅差分输出缓冲器的创新交流踢枪
公开(公告)号：US06246270B1
公开(公告)日：2001-06-12
申请号：US09345434
申请日：1999-07-01
申请人： Bonnie Wang , Joseph Huang , Wayne Yeung , Chiakang Sung , Richard Cliff , Khai Nguyen , Xiaobao Wang , In Whan Kim
发明人： Bonnie Wang , Joseph Huang , Wayne Yeung , Chiakang Sung , Richard Cliff , Khai Nguyen , Xiaobao Wang , In Whan Kim
IPC分类号： H03K426
CPC分类号： H03K17/04206 , H03K17/6871
摘要： Disclosed is a current booster or kicker for an output amplifier of a programmable logic control or other integrated circuit. The current booster includes a control mechanism and an auxiliary voltage supply. When a change in output state is initiated, the control mechanism connects the auxiliary voltage supply to the output of the output amplifier. After a change in output state in completed, the control mechanism disconnects the auxiliary voltage supply from the output of the output amplifier. In this way, the output amplifier can drive a relatively high capacitance load at a relatively high slew rate.
摘要翻译：公开了用于可编程逻辑控制或其他集成电路的输出放大器的电流增压器或激光器。电流增压器包括控制机构和辅助电压源。当启动输出状态的变化时，控制机构将辅助电源连接到输出放大器的输出端。在完成输出状态改变后，控制机构将输出放大器的输出端的辅助电源断开。以这种方式，输出放大器可以以相对较高的转换速率驱动较高的电容负载。

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