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81. 发明授权

US06627924B2 Memory system capable of operating at high temperatures and method for fabricating the same 有权
公开(公告)号：US06627924B2
公开(公告)日：2003-09-30
申请号：US09845695
申请日：2001-04-30
申请人： Louis L. Hsu , Li-Kong Wang
发明人： Louis L. Hsu , Li-Kong Wang
IPC分类号： H01L2974
CPC分类号： H01L27/1027 , H01L21/8213 , H01L27/0605 , Y10S438/931
摘要： A memory system having a plurality of T-RAM cells arranged in an array is presented where each T-RAM cell has dual vertical devices and is fabricated over a SiC substrate. Each T-RAM cell has a vertical thyristor and a vertical transfer gate. The top surface of each thyristor is coplanar with the top surface of each transfer gate within the T-RAM array to provide a planar cell structure for the T-RAM array. A method is also presented for fabricating the T-RAM array having the vertical thyristors, the vertical transfer gates and the planar cell structure over the SiC substrate.

82. 发明授权

US06512683B2 System and method for increasing the speed of memories 有权
标题翻译：提高记忆速度的系统和方法
公开(公告)号：US06512683B2
公开(公告)日：2003-01-28
申请号：US09827071
申请日：2001-04-05
申请人： Louis L. Hsu , Li-Kong Wang , Toshiaki K. Kirihata
发明人： Louis L. Hsu , Li-Kong Wang , Toshiaki K. Kirihata
IPC分类号： G11C1500
CPC分类号： G06F12/0895 , G06F12/0846 , G11C7/1042
摘要： The speed of memories is increased by trading memory density (or area) for speed (or cycle time). An n by n memory array is used to reduce the memory cycle time by 1/n. For example, if an existing memory cycle time is 6 ns, in order to achieve a 3ns (or n=2) cycle time, a 2 by 2 memory array is used. Or, in order to achieve a 1ns cycle time (or n=6), then a 6 by 6 memory array is used.
摘要翻译：通过为速度（或循环时间）交易记忆密度（或面积）来提高记忆速度。 n n存储器阵列用于将存储器周期时间减少1 / n。例如，如果现有存储器周期时间为6ns，为了实现3ns（或n = 2）周期时间，则使用2乘2存储器阵列。或者，为了实现1ns周期时间（或n = 6），则使用6乘6存储器阵列。

83. 发明授权

US06426914B1 Floating wordline using a dynamic row decoder and bitline VDD precharge 有权
标题翻译：浮动字线使用动态行解码器和位线VDD预充电
公开(公告)号：US06426914B1
公开(公告)日：2002-07-30
申请号：US09839105
申请日：2001-04-20
申请人： Robert H. Dennard , Louis L. Hsu , Toshiaki K. Kirihata
发明人： Robert H. Dennard , Louis L. Hsu , Toshiaki K. Kirihata
IPC分类号： G11C800
CPC分类号： G11C8/08 , G11C7/22 , G11C8/10 , G11C11/4076 , G11C11/4085 , G11C11/4087
摘要： A short cycle DRAM use a floating wordline, dynamic row decoder and bitline VDD precharge, which improves the array efficiency of the short cycle DRAM (3-6 ns) without compromising its performance. A small size wordline driver circuit is provided to reduce the row size of the short cycle DRAM without compromising row access timing. A dynamic decoding operation is implemented which intentionally allows some of the deselected wordlines to float during row access. A Vdd bitline precharge/sensing technique avoids a detrimental (or positive) coupling effect to the floating wordlines during row accessing. A Vdd data-line (or DQ) precharge for a read operation, and control of incoming data timing avoids a detrimental (or positive) coupling effect for a write operation.
摘要翻译：短周期DRAM使用浮动字线，动态行解码器和位线VDD预充电，这提高了短周期DRAM（3-6ns）的阵列效率，而不损害其性能。提供了一种小尺寸字线驱动器电路，以减少短周期DRAM的行大小，而不会影响行访问时序。实现动态解码操作，其有意地允许一些未选择的字线在行访问期间浮动。 Vdd位线预充电/感测技术在行访问期间避免了对浮动字线的有害（或正）耦合效应。用于读取操作的Vdd数据线（或DQ）预充电以及输入数据时序的控制避免了写入操作的有害（或正）耦合效应。

84. 发明授权

US06410369B1 Soi-body selective link method and apparatus 失效
标题翻译：单体选择性联动方法及装置
公开(公告)号：US06410369B1
公开(公告)日：2002-06-25
申请号：US09591511
申请日：2000-06-12
申请人： Roy Childs Flaker , Louis L. Hsu , Fariborz Assaderaghi , Jack A. Mandelman
发明人： Roy Childs Flaker , Louis L. Hsu , Fariborz Assaderaghi , Jack A. Mandelman
IPC分类号： H01L2100
CPC分类号： H01L27/1104 , H01L27/1203
摘要： A silicon-on-insulator (SOI) structure and method of making the same includes an SOI wafer having a silicon layer of an original thickness dimension formed upon an isolation oxidation layer. At least two p-type bodies of at least two SOI field effect transistors (PFETs) are formed in the silicon layer. At least two n-type bodies of at least two SOI field effect transistors (NFETs) are also formed in the silicon layer. Lastly, an SOI body link is formed in the silicon layer of the SOI wafer adjacent the isolation oxidation layer for selectively connecting desired bodies of either the p-type SOI FETs or the n-type SOI FETs and for allowing the connected bodies to float.
摘要翻译：绝缘体上硅（SOI）结构及其制造方法包括具有形成在隔离氧化层上的原始厚度尺寸的硅层的SOI晶片。在硅层中形成至少两个至少两个SOI场效应晶体管（PFET）的p型体。在硅层中还形成至少两个至少两个SOI场效应晶体管（NFET）的n型体。最后，在隔离氧化层附近的SOI晶片的硅层中形成SOI本体连接，用于选择性地连接p型SOI FET或n型SOI FET的所需体，并允许连接体浮置。

85. 发明授权

US06307805B1 High performance semiconductor memory device with low power consumption 有权
标题翻译：高性能半导体存储器件，功耗低
公开(公告)号：US06307805B1
公开(公告)日：2001-10-23
申请号：US09745227
申请日：2000-12-21
申请人： John E. Andersen , Terence B. Hook , Louis L. Hsu , Wei Hwang , Stephen V. Kosonocky , Li-Kong Wang
发明人： John E. Andersen , Terence B. Hook , Louis L. Hsu , Wei Hwang , Stephen V. Kosonocky , Li-Kong Wang
IPC分类号： G11C700
CPC分类号： G11C8/08 , G11C11/418 , H01L27/11
摘要： A semiconductor memory device accessed with wordlines and bitlines has memory cells which operate at high performance with lower power consumption and have a high density. Each of the memory cells has pass transistors connected to a corresponding wordline and a corresponding pair of bitlines, and the pass transistors are gated by a signal of the corresponding wordline. The semiconductor memory device includes a wordline drive unit for selectively driving the wordlines in response to a row address. A wordline driver in the wordline drive unit boosts a corresponding wordline in a positive direction when the corresponding wordline is activated to access the memory cell and boosts the corresponding wordline in a negative direction when the corresponding wordline is inactive. By boosting the wordline in the positive direction, the performance of the memory cells is enhanced, and by boosting the wordline in the negative direction, a leakage current in the pass transistors with a low-threshold voltage is prevented.
摘要翻译：用字线和位线访问的半导体存储器件具有以较低的功耗以高密度工作的高性能的存储单元。每个存储单元具有连接到相应字线和相应的一对位线的传输晶体管，并且通过晶体管由相应字线的信号选通。半导体存储器件包括用于响应于行地址选择性地驱动字线的字线驱动单元。当对应的字线不活动时，字线驱动单元中的字线驱动器在相应的字线被激活以访问存储器单元并且在相反的方向上升高相应的字线时以正方向提升相应的字线。通过在正方向上升压字线，增强了存储单元的性能，并且通过在负方向上升高字线，防止具有低阈值电压的通过晶体管中的漏电流。

86. 发明授权

US06255712B1 Semi-sacrificial diamond for air dielectric formation 有权
标题翻译：用于空气电介质形成的半牺牲金刚石
公开(公告)号：US06255712B1
公开(公告)日：2001-07-03
申请号：US09374839
申请日：1999-08-14
申请人： Lawrence A Clevenger , Louis L. Hsu
发明人： Lawrence A Clevenger , Louis L. Hsu
IPC分类号： H01L2900
CPC分类号： H01L23/4821 , H01L21/764 , H01L21/7682 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： Disclosed is a structure and process for incorporating air or other gas as a permanent dielectric medium in a multilevel chip by providing CVD diamond as a semi-sacrificial interlevel and intralevel dielectric material. The semi-sacrificial dielectric is subsequently at least partially removed in an isotopic oxygen etch. A variation of the disclosure includes providing a final, permanent CVD diamond encapsulant to contain the gaseous dielectric medium within the chip.
摘要翻译：公开了一种通过提供CVD金刚石作为半牺牲层间和体内电介质材料将空气或其它气体作为永久介电介质并入多层芯片的结构和方法。随后在同位素氧蚀刻中至少部分去除半牺牲电介质。本公开的变体包括提供最终的永久CVD金刚石密封剂以容纳芯片内的气态电介质。

87. 发明授权

US06228745B1 Selective reduction of sidewall slope on isolation edge 失效
标题翻译：隔离边缘侧壁倾斜的选择性减小
公开(公告)号：US06228745B1
公开(公告)日：2001-05-08
申请号：US09460134
申请日：1999-12-13
申请人： Donald C. Wheeler , Louis L. Hsu , Jack A. Mandelman , Rebecca D. Mih
发明人： Donald C. Wheeler , Louis L. Hsu , Jack A. Mandelman , Rebecca D. Mih
IPC分类号： H01L2176
CPC分类号： H01L21/76232 , Y10S438/947
摘要： Disclosed is a semiconductor structure which comprises a transistor having a source implantation and a drain implantation formed in a semiconductor substrate. The transistor further comprises a gate electrode, a gate oxide, and an active area. The source implantation and drain implantation are situated on opposite sides of said active area, and said gate oxide and gate electrode are situated on top of said active region. The transistor further comprises two trench isolations adjacent to said active area, wherein said trench isolations are situated on opposite sides of said active area such that a sidewall of each trench serves as interface to said active area, at least one of said sidewalls of said trench isolations which serves as interface to said active area being sloped having a slope between 90° and 150°, said trench isolations and source implantation and drain implantation enclosing said active area on four sides.
摘要翻译：公开了一种半导体结构，其包括在半导体衬底中形成的源极注入和漏极注入的晶体管。晶体管还包括栅电极，栅极氧化物和有源区。源极注入和漏极注入位于所述有源区的相对侧，并且所述栅极氧化物和栅电极位于所述有源区的顶部。晶体管还包括与所述有源区相邻的两个沟槽隔离，其中所述沟槽隔离位于所述有源区的相对侧，使得每个沟槽的侧壁用作与所述有源区的界面，所述沟槽的至少一个侧壁用作与所述有源区的界面的隔离具有倾斜的90°至150°之间的斜率，所述沟槽隔离和源极注入和漏极注入在四个侧面上包围所述有源区。

88. 发明授权

US06222244B1 Electrically blowable fuse with reduced cross-sectional area 失效
标题翻译：具有减小横截面积的可电熔保险丝
公开(公告)号：US06222244B1
公开(公告)日：2001-04-24
申请号：US09093903
申请日：1998-06-08
申请人： Kenneth C. Arndt , Dureseti Chidambarrao , Louis L. Hsu , Jack A. Mandelman , Carl Radens
发明人： Kenneth C. Arndt , Dureseti Chidambarrao , Louis L. Hsu , Jack A. Mandelman , Carl Radens
IPC分类号： H01L2900
CPC分类号： H01L23/62 , H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor fuse is positioned between conductors for connecting wiring lines. The fuse comprises spacers positioned on adjacent ones of the conductors, and a fuse element positioned between the spacers and connected to the wiring lines. A space between the conductors comprises a first width comprising a smallest possible photolithographic width and the fuse element has a second width smaller than the first width.
摘要翻译：半导体保险丝位于用于连接布线的导体之间。保险丝包括位于相邻导体上的间隔物，以及定位在间隔件之间并连接到布线的熔丝元件。导体之间的空间包括包含尽可能小的光刻宽度的第一宽度，并且熔丝元件具有小于第一宽度的第二宽度。

89. 发明授权

US06144054A DRAM cell having an annular signal transfer region 有权
标题翻译： DRAM单元具有环形信号传送区域
公开(公告)号：US06144054A
公开(公告)日：2000-11-07
申请号：US205934
申请日：1998-12-04
申请人： Farid Agahi , Louis L. Hsu , Jack A. Mandelman
发明人： Farid Agahi , Louis L. Hsu , Jack A. Mandelman
IPC分类号： H01L21/8242 , H01L27/108 , H01L29/76 , H01L29/94 , H01L31/119
CPC分类号： H01L27/10864 , H01L27/10841
摘要： A memory device formed in a substrate having a trench with side walls formed in the substrate. The device includes a bit line conductor and a word line conductor. A signal storage node has a first electrode, a second electrode formed within the trench, and a node dielectric formed between the first and second electrodes. A signal transfer device has: (i) an annular signal transfer region with an outer surface adjacent the side walls of the trench, an inner surface, a first end, and a second end; (ii) a first diffusion region coupling the first end of the signal transfer region to the. second electrode of the signal storage node; (iii) a second diffusion region coupling the second end of the signal transfer region to the bit line conductor; (iv) a gate insulator coating the inner surface of the signal transfer region; and (v) a gate conductor coating the gate insulator and coupled to the word line. A conductive connecting member couples the signal transfer region to a reference voltage to reduce floating body effects.
摘要翻译：一种存储器件，形成在具有形成在衬底中的侧壁的沟槽的衬底中。该器件包括位线导体和字线导体。信号存储节点具有形成在沟槽内的第一电极，第二电极和形成在第一和第二电极之间的节点电介质。信号传递装置具有：（i）环形信号传递区域，其外表面邻近沟槽的侧壁，内表面，第一端和第二端; （ii）将信号传送区域的第一端耦合到第一扩散区域。信号存储节点的第二电极; （iii）将信号传输区域的第二端耦合到位线导体的第二扩散区域; （iv）涂覆信号传送区域的内表面的栅极绝缘体; 和（v）涂覆栅极绝缘体并耦合到字线的栅极导体。导电连接构件将信号传递区域耦合到参考电压以减少浮体效应。

90. 发明授权

US06015991A Asymmetrical field effect transistor 失效
标题翻译：非对称场效应晶体管
公开(公告)号：US06015991A
公开(公告)日：2000-01-18
申请号：US820401
申请日：1997-03-12
申请人： Donald C. Wheeler , Jeffrey P. Gambino , Louis L. Hsu , Jack A. Mandelman , Rebecca D. Mih
发明人： Donald C. Wheeler , Jeffrey P. Gambino , Louis L. Hsu , Jack A. Mandelman , Rebecca D. Mih
IPC分类号： H01L21/027 , H01L21/266 , H01L21/3213 , H01L21/336 , H01L21/8234 , H01L27/088 , H01L29/423 , H01L29/78 , H01L29/02
CPC分类号： H01L29/66598 , H01L21/266 , H01L21/32139 , H01L29/42376 , H01L29/66545 , H01L29/66659 , H01L29/7835 , H01L21/0274
摘要： Disclosed is an asymmetric field effect transistor which comprises a first region serving as source, a second region serving as drain, a thin gate oxide and a gate electrode. The gate electrode is asymmetric and one of its sidewalls is sloped. The second region extends underneath said sloped sidewall. The part of said second region which extends underneath said gate electrode is less doped than the remaining part of said second region. Furthermore, said second region has a sloped junction edge underneath said gate electrode.
摘要翻译：公开了一种非对称场效应晶体管，其包括用作源极的第一区域，用作漏极的第二区域，薄栅极氧化物和栅电极。栅电极是不对称的，其侧壁之一是倾斜的。第二区域在所述倾斜侧壁的下方延伸。在所述栅电极下方延伸的所述第二区域的部分比所述第二区域的剩余部分掺杂少。此外，所述第二区域在所述栅电极下方具有倾斜的接合边缘。

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