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1. 发明申请

US20090212341A1 SEMITUBULAR METAL-OXIDE-SEMICONDUCTOR FIELD EFFECT TRANSISTOR 有权
标题翻译：半导体金属氧化物半导体场效应晶体管
公开(公告)号：US20090212341A1
公开(公告)日：2009-08-27
申请号：US12034899
申请日：2008-02-21
申请人： Kangguo Cheng , Lawrence A. Clevenger , Timothy J. Dalton , Louis L. Hsu , Jack A. Mandelman
发明人： Kangguo Cheng , Lawrence A. Clevenger , Timothy J. Dalton , Louis L. Hsu , Jack A. Mandelman
IPC分类号： H01L29/788 , H01L21/336
CPC分类号： H01L27/108 , H01L27/10802 , H01L27/10826 , H01L29/66795 , H01L29/7841 , H01L29/7853
摘要： An epitaxial semiconductor layer or a stack of a silicon germanium alloy layer and an epitaxial strained silicon layer is formed on outer sidewalls of a porous silicon portion on a substrate. The porous silicon portion and any silicon germanium alloy material are removed and a semitubular epitaxial semiconductor structure in a three-walled configuration is formed. A semitubular field effect transistor comprising inner and outer gate dielectric layers, an inner gate electrode, an outer gate electrode, and source and drain regions is formed on the semitubular epitaxial semiconductor structure. The semitubular field effect transistor may operate as an SOI transistor with a tighter channel control through the inner and outer gate electrodes, or as a memory device storing electrical charges in the body region within the semitubular epitaxial semiconductor structure.
摘要翻译：在衬底上的多孔硅部分的外侧壁上形成硅锗合金层和外延应变硅层的外延半导体层或叠层。去除多孔硅部分和任何硅锗合金材料，并形成三壁结构的半管状外延半导体结构。在半管外延半导体结构上形成包括内栅电介质层和外栅电介质层，内栅电极，外栅电极以及源极和漏极区的半管场效应晶体管。半管场效应晶体管可以作为具有通过内部和外部栅极电极的更严格的沟道控制的SOI晶体管，或作为在半管外延半导体结构内的体区中存储电荷的存储器件。

2. 发明授权

US07092235B2 Method for adjusting capacitance of an on-chip capacitor 失效
标题翻译：调整片上电容器电容的方法
公开(公告)号：US07092235B2
公开(公告)日：2006-08-15
申请号：US11043760
申请日：2005-01-26
申请人： Lawrence A. Clevenger , Timothy J. Dalton , Louis L. Hsu , Carl Radens , Keith Kwong Hon Wong , Chih-Chao Yang
发明人： Lawrence A. Clevenger , Timothy J. Dalton , Louis L. Hsu , Carl Radens , Keith Kwong Hon Wong , Chih-Chao Yang
IPC分类号： H01G4/06
CPC分类号： H01G4/255 , H01L22/22 , H01L28/40
摘要： A method and apparatus, is herein disclosed, for adjusting capacitance of an on-chip capacitor formed on a substrate. A plurality of conductive layers is separated by a layer ofdielectric material. The dielectric material of the capacitor is exposed to an ion beam. The ion beam includes ions of at least one material to modify a dielectric constant of the dielectric material.
摘要翻译：本文公开了一种用于调节形成在衬底上的片上电容器的电容的方法和装置。多个导电层被一层电介质材料隔开。电容器的电介质材料暴露于离子束。离子束包括至少一种材料的离子，以改变介电材料的介电常数。

3. 发明授权

US07052937B2 Method and structure for providing improved thermal conduction for silicon semiconductor devices 失效
公开(公告)号：US07052937B2
公开(公告)日：2006-05-30
申请号：US10429758
申请日：2003-05-05
申请人： Lawrence A. Clevenger , Louis L. Hsu , Li-Kong Wang , Tsorng-Dih Yuan
发明人： Lawrence A. Clevenger , Louis L. Hsu , Li-Kong Wang , Tsorng-Dih Yuan
IPC分类号： H01L21/44
CPC分类号： H01L21/76264 , H01L21/76283 , H01L23/3677 , H01L23/3732 , H01L27/1203 , H01L2924/0002 , H01L2924/00
摘要： Thermal cooling structures of diamond or diamond-like materials are provided for conducting heat away from semiconductor devices. A first silicon-on-insulator embodiment comprises a plurality of thermal paths, formed after shallow trench and device fabrication steps are completed, which extend through the buried oxide and provide heat dissipation through to the underlying bulk silicon substrate. The thermal conduction path material is preferably diamond which has high thermal conductivity with low electrical conductivity. A second diamond trench cooling structure, formed after device fabrication has been completed, comprises diamond shallow trenches disposed between the devices and extending through the buried oxide layer. An alternative diamond thermal cooling structure includes a diamond insulation layer deposited over the semiconductor devices in either an SOI or bulk silicon structure. Yet another embodiment comprises diamond sidewalls formed along the device walls in thermal contact with the device junctions to provide heat dissipation through the device junctions to underlying cooling structures. It is also proposed that the foregoing structures, and combinations of the foregoing structures, could be used in conjunction with other known cooling schemes.

4. 发明授权

US07041552B2 Integrated metal-insulator-metal capacitor and metal gate transistor 失效
标题翻译：集成金属 - 绝缘体 - 金属电容器和金属栅极晶体管
公开(公告)号：US07041552B2
公开(公告)日：2006-05-09
申请号：US10787487
申请日：2004-02-26
申请人： Lawrence A. Clevenger , Louis L. Hsu , Kwong Hon Wong
发明人： Lawrence A. Clevenger , Louis L. Hsu , Kwong Hon Wong
IPC分类号： H01L21/8242
CPC分类号： H01L21/28194 , H01L21/28079 , H01L21/28088 , H01L21/28114 , H01L27/0629 , H01L27/10805 , H01L27/1085 , H01L27/10885 , H01L29/42376 , H01L29/495 , H01L29/4958 , H01L29/4966 , H01L29/51 , H01L29/517 , H01L29/66545
摘要： An integrated circuit structure is disclosed that comprises a pair of capacitors, each having metal plates separated by an insulator, and metal gate semiconductor transistors electrically connected to the capacitors. The metal gate of the transistors and one of the metal plates of each of the capacitors comprise the same metal level in the integrated circuit structure. More specifically, each of the capacitors comprise a vertical capacitor having an upper metal plate vertically over a lower metal plate and each metal gate of the transistors and each upper metal plate of the capacitors comprise the same metal level in the integrated circuit structure.
摘要翻译：公开了一种集成电路结构，其包括一对电容器，每个电容器具有由绝缘体分隔的金属板和与电容器电连接的金属栅极半导体晶体管。晶体管的金属栅极和每个电容器的金属板之一在集成电路结构中包括相同的金属电平。更具体地，每个电容器包括垂直电容器，其具有垂直于下金属板上的上金属板，并且晶体管的每个金属栅极和电容器的每个上金属板在集成电路结构中包括相同的金属电平。

5. 发明授权

US06933189B2 Integration system via metal oxide conversion 失效
标题翻译：集成系统通过金属氧化物转换
公开(公告)号：US06933189B2
公开(公告)日：2005-08-23
申请号：US10870382
申请日：2004-06-16
申请人： Lawrence A. Clevenger , Louis L. Hsu , Carl J. Radens , Joseph F. Shepard, Jr.
发明人： Lawrence A. Clevenger , Louis L. Hsu , Carl J. Radens , Joseph F. Shepard, Jr.
IPC分类号： H01L21/285 , H01L21/30 , H01L21/306 , H01L21/3205 , H01L21/336 , H01L21/768 , H01L21/8232 , H01L21/8234 , H01L29/49 , H01L29/76 , H01L29/78 , H01L29/84 , H01L31/062 , H01L31/107 , H01L31/113 , H01L31/119
CPC分类号： H01L29/4983 , H01L21/28194 , H01L21/28518 , H01L21/28568 , H01L21/3003 , H01L21/76823 , H01L21/76895 , H01L29/517 , H01L29/7833
摘要： A method and structure for a transistor device comprises forming a source, drain, and trench region in a substrate, forming a first insulator over the substrate, forming a gate electrode above the first insulator, forming a pair of insulating spacers adjoining the electrode, converting a portion of the first insulator into a metallic film, converting the metallic film into one of a silicide and a salicide film, forming an interconnect region above the trench region, forming an etch stop layer above the first insulator, the trench region, the gate electrode, and the pair of insulating spacers, forming a second insulator above the etch stop layer, and forming contacts in the second insulator. The first insulator comprises a metal oxide material, which comprises one of a HfOx and a ZrOx.
摘要翻译：晶体管器件的方法和结构包括在衬底中形成源极，漏极和沟槽区域，在衬底上形成第一绝缘体，在第一绝缘体之上形成栅电极，形成邻接电极的一对绝缘衬垫，转换将所述第一绝缘体的一部分转变为金属膜，将所述金属膜转化成硅化物和自对隔硅膜之一，在所述沟槽区上方形成互连区，在所述第一绝缘体上方形成蚀刻停止层，所述沟槽区，所述栅电极和一对绝缘间隔物，在蚀刻停止层上方形成第二绝缘体，并在第二绝缘体中形成接触。第一绝缘体包括金属氧化物材料，其包括HfO x x和ZrO x x之一。

6. 发明授权

US06869895B1 Method for adjusting capacitance of an on-chip capacitor 失效
标题翻译：调整片上电容器电容的方法
公开(公告)号：US06869895B1
公开(公告)日：2005-03-22
申请号：US10674719
申请日：2003-09-30
申请人： Lawrence A. Clevenger , Timothy J. Dalton , Louis L. Hsu , Carl Radens , Keith Kwong Hon Wong , Chih-Chao Yang
发明人： Lawrence A. Clevenger , Timothy J. Dalton , Louis L. Hsu , Carl Radens , Keith Kwong Hon Wong , Chih-Chao Yang
IPC分类号： H01G4/255 , H01L21/02 , H01L21/66 , H01L21/31
CPC分类号： H01G4/255 , H01L22/22 , H01L28/40
摘要： A method and apparatus for adjusting capacitance of an on-chip capacitor uses exposure of a dielectric material of the capacitor to an ion beam comprising ions of at least one material to modify a dielectric constant of the dielectric material.
摘要翻译：用于调整片上电容器的电容的方法和装置使用将电容器的电介质材料暴露于包含至少一种材料的离子的离子束，以改变介电材料的介电常数。

7. 发明授权

US06255712B1 Semi-sacrificial diamond for air dielectric formation 有权
标题翻译：用于空气电介质形成的半牺牲金刚石
公开(公告)号：US06255712B1
公开(公告)日：2001-07-03
申请号：US09374839
申请日：1999-08-14
申请人： Lawrence A Clevenger , Louis L. Hsu
发明人： Lawrence A Clevenger , Louis L. Hsu
IPC分类号： H01L2900
CPC分类号： H01L23/4821 , H01L21/764 , H01L21/7682 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： Disclosed is a structure and process for incorporating air or other gas as a permanent dielectric medium in a multilevel chip by providing CVD diamond as a semi-sacrificial interlevel and intralevel dielectric material. The semi-sacrificial dielectric is subsequently at least partially removed in an isotopic oxygen etch. A variation of the disclosure includes providing a final, permanent CVD diamond encapsulant to contain the gaseous dielectric medium within the chip.
摘要翻译：公开了一种通过提供CVD金刚石作为半牺牲层间和体内电介质材料将空气或其它气体作为永久介电介质并入多层芯片的结构和方法。随后在同位素氧蚀刻中至少部分去除半牺牲电介质。本公开的变体包括提供最终的永久CVD金刚石密封剂以容纳芯片内的气态电介质。

8. 发明授权

US07888729B2 Flash memory gate structure for widened lithography window 失效
标题翻译：用于加宽光刻窗的闪存门结构
公开(公告)号：US07888729B2
公开(公告)日：2011-02-15
申请号：US12198345
申请日：2008-08-26
申请人： Kangguo Cheng , Lawrence A. Clevenger , Timothy J. Dalton , Louis L. Hsu
发明人： Kangguo Cheng , Lawrence A. Clevenger , Timothy J. Dalton , Louis L. Hsu
IPC分类号： H01L21/336
CPC分类号： H01L29/7881 , H01L29/66825
摘要： A first portion of a semiconductor substrate belonging to a flash memory device region is recessed to a recess depth to form a recessed region, while a second portion of the semiconductor substrate belonging to a logic device region is protected with a masking layer. A first gate dielectric layer and a first gate conductor layer formed within the recessed region such that the first gate conductive layer is substantially coplanar with the top surfaces of the shallow trench isolation structures. A second gate dielectric layer, a second gate conductor layer, and a gate cap hard mask layer, each having a planar top surface, is subsequently patterned. The pattern of the gate structure in the flash memory device region is transferred into the first gate conductor layer and the first gate dielectric layer to form a floating gate and a first gate dielectric, respectively.
摘要翻译：属于闪存器件区域的半导体衬底的第一部分凹陷到凹陷深度以形成凹陷区域，而属于逻辑器件区域的半导体衬底的第二部分被掩蔽层保护。形成在凹陷区域内的第一栅介质层和第一栅极导体层，使得第一栅极导电层与浅沟槽隔离结构的顶表面基本共面。随后对第二栅介质层，第二栅极导体层和栅帽硬掩模层进行构图，每个具有平坦的顶表面。闪存器件区域中的栅极结构的图案被转移到第一栅极导体层和第一栅极介电层中，以分别形成浮置栅极和第一栅极电介质。

9. 发明授权

US07041525B2 Three-dimensional island pixel photo-sensor 有权
公开(公告)号：US07041525B2
公开(公告)日：2006-05-09
申请号：US10751205
申请日：2004-01-02
申请人： Lawrence A. Clevenger , Louis L. Hsu , Carl J. Radens , Li-Kong Wang , Kwong Hon Wong
发明人： Lawrence A. Clevenger , Louis L. Hsu , Carl J. Radens , Li-Kong Wang , Kwong Hon Wong
IPC分类号： H01L21/66 , H01L21/00
CPC分类号： H01L27/14634 , H01L27/1463 , H01L27/14643
摘要： A method and structure for a photodiode array comprising a plurality of photodiode cores, light sensing sidewalls along an exterior of the cores, logic circuitry above the cores, trenches separating the cores, and a transparent material in the trenches is disclosed. With the invention, the sidewalls are perpendicular to the surface of the photodiode that receives incident light. The light sensing sidewalls comprise a junction region that causes electron transfer when struck with light. The sidewalls comprise four vertical sidewalls around each island core. The logic circuitry blocks light from the core so light is primarily only sensed by the sidewalls.

10. 发明授权

US06638681B2 X-ray printing personalization technique 失效
标题翻译： X射线印刷个性化技术
公开(公告)号：US06638681B2
公开(公告)日：2003-10-28
申请号：US10281677
申请日：2002-10-28
申请人： Lawrence A. Clevenger , David B. Goland , Louis L. Hsu , Joseph F. Shepard, Jr. , Subhash L. Shinde
发明人： Lawrence A. Clevenger , David B. Goland , Louis L. Hsu , Joseph F. Shepard, Jr. , Subhash L. Shinde
IPC分类号： G03F700
CPC分类号： H05K3/02 , B32B2310/085 , B32B2311/04 , B32B2311/12 , B32B2311/22 , C04B2237/40 , C04B2237/403 , C04B2237/405 , G03F7/2039 , H05K1/0306 , H05K1/092 , H05K3/207 , H05K2203/0514 , Y10S430/168 , Y10T428/24926
摘要： A method and structure to form a conductive pattern on a ceramic sheet deposits a photosensitive conductive material on a carrier and exposes a pattern of x-ray energy on the material and sinters the carrier and the material to the ceramic sheet so that only the conductive pattern of the material remains on the ceramic sheet. The structure has a conductive patterned material which includes a photosensitive agent.
摘要翻译：在陶瓷片上形成导电图案的方法和结构将感光导电材料沉积在载体上并在材料上暴露出x射线能量的图案，并将载体和材料烧结到陶瓷片上，使得只有导电图案的材料残留在陶瓷片上。该结构具有包括感光剂的导电图案化材料。

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