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81. 发明授权

US08359414B2 Retry mechanism 有权
标题翻译：重试机制
公开(公告)号：US08359414B2
公开(公告)日：2013-01-22
申请号：US13165235
申请日：2011-06-21
申请人： James B. Keller , Sridhar P. Subramanian , Ramesh Gunna
发明人： James B. Keller , Sridhar P. Subramanian , Ramesh Gunna
IPC分类号： G06F3/00 , G06F15/167
CPC分类号： G06F12/0831 , G06F13/362 , G06F13/4213 , Y02D10/13 , Y02D10/14 , Y02D10/151
摘要： An interface unit may comprise a buffer configured to store requests that are to be transmitted on an interconnect and a control unit coupled to the buffer. In one embodiment, the control unit is coupled to receive a retry response from the interconnect during a response phase of a first transaction for a first request stored in the buffer. The control unit is configured to record an identifier supplied on the interconnect with the retry response that identifies a second transaction that is in progress on the interconnect. The control unit is configured to inhibit reinitiation of the first transaction at least until detecting a second transmission of the identifier. In another embodiment, the control unit is configured to assert a retry response during a response phase of a first transaction responsive to a snoop hit of the first transaction on a first request stored in the buffer for which a second transaction is in progress on the interconnect. The control unit is further configured to provide an identifier of the second transaction with the retry response.
摘要翻译：接口单元可以包括被配置为存储要在互连上发送的请求的缓冲器和耦合到缓冲器的控制单元。在一个实施例中，控制单元被耦合以在对于存储在缓冲器中的第一请求的第一事务的响应阶段期间从互连接收重试响应。控制单元被配置为记录在互连上提供的标识符，该重试响应标识互连上正在进行的第二事务。控制单元被配置为至少在检测到标识符的第二次传输之前禁止第一事务的重新发起。在另一个实施例中，控制单元被配置为在第一事务的响应阶段响应第一事务的窥探命中在存储在第二事务在互连上的第二事务的缓冲器中的第一请求时断言重试响应。控制单元还被配置为提供具有重试响应的第二事务的标识符。

82. 发明授权

US08219758B2 Block-based non-transparent cache 有权
标题翻译：基于块的不透明缓存
公开(公告)号：US08219758B2
公开(公告)日：2012-07-10
申请号：US12500810
申请日：2009-07-10
申请人： James Wang , Zongjian Chen , James B. Keller , Timothy J. Millet
发明人： James Wang , Zongjian Chen , James B. Keller , Timothy J. Millet
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28
CPC分类号： G06F12/0802 , G06F12/0223 , G06F12/08 , G06F2212/2515 , Y02D10/13
摘要： In an embodiment, a non-transparent memory unit is provided which includes a non-transparent memory and a control circuit. The control circuit may manage the non-transparent memory as a set of non-transparent memory blocks. Software executing on one or more processors may request a non-transparent memory block in which to process data. The control circuit may allocate a first block, and may return an address (or other indication) of the allocated block so that the software can access the block. The control circuit may also provide automatic data movement between the non-transparent memory and a main memory system to which the non-transparent memory unit is coupled. For example, the automatic data movement may include filling data from the main memory system to the allocated block, or flushing the data in the allocated block to the main memory system after the processing of the allocated block is complete.
摘要翻译：在一个实施例中，提供了一种非透明存储器单元，其包括非透明存储器和控制电路。控制电路可以将非透明存储器作为一组非透明存储器块进行管理。在一个或多个处理器上执行的软件可以请求处理数据的非透明存储器块。控制电路可以分配第一块，并且可以返回所分配的块的地址（或其他指示），使得软件可以访问块。控制电路还可以在非透明存储器与非透明存储器单元耦合到的主存储器系统之间提供自动数据移动。例如，自动数据移动可以包括在分配的块的处理完成之后从主存储器系统填充数据到所分配的块，或者将分配的块中的数据刷新到主存储器系统。

83. 发明授权

US08171326B2 L1 flush mechanism to flush cache for power down and handle coherence during flush and/or after power down 有权
标题翻译： L1冲洗机构刷新缓存以断电并处理冲水和/或断电后的一致性
公开(公告)号：US08171326B2
公开(公告)日：2012-05-01
申请号：US12785842
申请日：2010-05-24
申请人： James B. Keller , Tse-Yu Yeh , Ramesh Gunna , Brian J. Campbell
发明人： James B. Keller , Tse-Yu Yeh , Ramesh Gunna , Brian J. Campbell
IPC分类号： G06F1/32
CPC分类号： G06F1/3203 , G06F1/3237 , Y02D10/128 , Y02D50/20
摘要： In one embodiment, a processor comprises a data cache configured to store a plurality of cache blocks and a control unit coupled to the data cache. The control unit is configured to flush the plurality of cache blocks from the data cache responsive to an indication that the processor is to transition to a low power state in which one or more clocks for the processor are inhibited.
摘要翻译：在一个实施例中，处理器包括被配置为存储多个高速缓存块的数据高速缓存和耦合到数据高速缓存的控制单元。控制单元被配置为响应于处理器将转换到其中禁止用于处理器的一个或多个时钟的低功率状态的指示，从数据高速缓冲存储器中刷新多个高速缓存块。

84. 发明授权

US08086915B2 Memory controller with loopback test interface 有权
标题翻译：带环回测试接口的内存控制器
公开(公告)号：US08086915B2
公开(公告)日：2011-12-27
申请号：US12909073
申请日：2010-10-21
申请人： Luka Bodrozic , Sukalpa Biswas , Hao Chen , Sridhar P. Subramanian , James B. Keller
发明人： Luka Bodrozic , Sukalpa Biswas , Hao Chen , Sridhar P. Subramanian , James B. Keller
IPC分类号： G01R31/28 , G11C29/00 , G06F11/00
CPC分类号： G01R31/31716
摘要： In one embodiment, an apparatus comprises an interconnect; at least one processor coupled to the interconnect; and at least one memory controller coupled to the interconnect. The memory controller is programmable by the processor into a loopback test mode of operation and, in the loopback test mode, the memory controller is configured to receive a first write operation from the processor over the interconnect. The memory controller is configured to route write data from the first write operation through a plurality of drivers and receivers connected to a plurality of data pins that are capable of connection to one or more memory modules. The memory controller is further configured to return the write data as read data on the interconnect for a first read operation received from the processor on the interconnect.
摘要翻译：在一个实施例中，一种装置包括互连; 耦合到所述互连的至少一个处理器; 以及耦合到所述互连的至少一个存储器控制器。存储器控制器可由处理器编程为环回测试操作模式，并且在环回测试模式中，存储器控制器被配置为通过互连从处理器接收第一写入操作。存储器控制器被配置为将来自第一写入操作的写入数据路由到连接到能够连接到一个或多个存储器模块的多个数据引脚的多个驱动器和接收器。所述存储器控制器还被配置为将所述写入数据作为所述互连上的读取数据返回，用于从所述互连处从所述处理器接收的第一读取操作。

85. 发明申请

US20110035560A1 Memory Controller with Loopback Test Interface 有权
标题翻译：带环回测试接口的内存控制器
公开(公告)号：US20110035560A1
公开(公告)日：2011-02-10
申请号：US12909073
申请日：2010-10-21
申请人： Luka Bodrozic , Sukalpa Biswas , Hao Chen , Sridhar P. Subramanian , James B. Keller
发明人： Luka Bodrozic , Sukalpa Biswas , Hao Chen , Sridhar P. Subramanian , James B. Keller
IPC分类号： G06F12/00 , G06F3/00
CPC分类号： G01R31/31716
摘要： In one embodiment, an apparatus comprises an interconnect; at least one processor coupled to the interconnect; and at least one memory controller coupled to the interconnect. The memory controller is programmable by the processor into a loopback test mode of operation and, in the loopback test mode, the memory controller is configured to receive a first write operation from the processor over the interconnect. The memory controller is configured to route write data from the first write operation through a plurality of drivers and receivers connected to a plurality of data pins that are capable of connection to one or more memory modules. The memory controller is further configured to return the write data as read data on the interconnect for a first read operation received from the processor on the interconnect.
摘要翻译：在一个实施例中，一种装置包括互连; 耦合到所述互连的至少一个处理器; 以及耦合到所述互连的至少一个存储器控制器。存储器控制器可由处理器编程为环回测试操作模式，并且在环回测试模式中，存储器控制器被配置为通过互连从处理器接收第一写入操作。存储器控制器被配置为将来自第一写入操作的写入数据路由到连接到能够连接到一个或多个存储器模块的多个数据引脚的多个驱动器和接收器。所述存储器控制器还被配置为将所述写入数据作为所述互连上的读取数据返回，用于从所述互连处从所述处理器接收的第一读取操作。

86. 发明申请

US20110035518A1 Digital Phase Relationship Lock Loop 有权
标题翻译：数字相位锁定环路
公开(公告)号：US20110035518A1
公开(公告)日：2011-02-10
申请号：US12908605
申请日：2010-10-20
申请人： James Wang , Zongjian Chen , James B. Keller
发明人： James Wang , Zongjian Chen , James B. Keller
IPC分类号： G06F5/00
CPC分类号： G06F5/14
摘要： In one embodiment, an apparatus comprises a first clocked storage device operable in a first clock domain corresponding to a first clock signal. The first clocked storage device has an input coupled to receive one or more bits transmitted on the input from a second clock domain corresponding to a second clock signal. The apparatus further comprises control circuitry configured to ensure that a change in a value of the one or more bits transmitted on the input meets setup and hold time requirements of the first clocked storage device. The control circuitry is responsive to a sample history of one of the first clock signal or the second clock signal to detect a phase relationship between the first clock signal and the second clock signal on each clock cycle to ensure the change meets the setup and hold time requirements.
摘要翻译：在一个实施例中，一种装置包括可在对应于第一时钟信号的第一时钟域中操作的第一时钟存储装置。第一时钟存储设备具有耦合以接收从对应于第二时钟信号的第二时钟域在输入上发送的一个或多个位的输入。该装置还包括控制电路，其被配置为确保在输入上传输的一个或多个位的值的变化满足第一时钟存储设备的建立和保持时间要求。控制电路响应于第一时钟信号或第二时钟信号之一的采样历史，以在每个时钟周期上检测第一时钟信号和第二时钟信号之间的相位关系，以确保改变满足建立和保持时间要求。

87. 发明授权

US07596148B2 Receiving data from virtual channels 失效
标题翻译：从虚拟通道接收数据
公开(公告)号：US07596148B2
公开(公告)日：2009-09-29
申请号：US11786275
申请日：2007-04-11
申请人： Manu Gulati , Laurent R. Moll , James B. Keller
发明人： Manu Gulati , Laurent R. Moll , James B. Keller
IPC分类号： H04L12/28
CPC分类号： G06F13/4247
摘要： A method for receiving data from a plurality of virtual channels begins by storing a stream of data as a plurality of data segments, wherein the stream of data includes multiplexed data fragments from at least one of the plurality of virtual channels, and wherein a data segment of the plurality of data segments corresponds to one of the multiplexed data fragments. The method continues by decoding at least one of the plurality of data segments in accordance with one of a plurality of data transmission protocols to produce at least one decoded data segment. The method continues by storing the at least one decoded data segment, in a generic format, to reassemble at least a portion of a packet provided by the at least one of the plurality of virtual channels. The method continues by routing the at least one decoded data segment as at least part of the reassembled packet to one of a plurality of destinations in accordance with the at least one of the plurality of virtual channels.
摘要翻译：用于从多个虚拟频道接收数据的方法开始于将数据流存储为多个数据段，其中数据流包括来自多个虚拟通道中的至少一个的多路复用数据片段，并且其中数据段所述多个数据段对应于所述多路复用数据片段中的一个。该方法通过根据多个数据传输协议之一对多个数据段中的至少一个解码以产生至少一个解码的数据段来继续。该方法通过以通用格式存储至少一个解码的数据段来重新组合由多个虚拟通道中的至少一个提供的分组的至少一部分来继续。该方法通过根据多个虚拟信道中的至少一个将至少一个解码的数据段作为至少部分重新组装的分组路由到多个目的地之一来继续。

88. 发明授权

US07529866B2 Retry mechanism in cache coherent communication among agents 有权
标题翻译：代理之间缓存一致通信中的重试机制
公开(公告)号：US07529866B2
公开(公告)日：2009-05-05
申请号：US11282037
申请日：2005-11-17
申请人： James B. Keller , Sridhar P. Subramanian , Ramesh Gunna
发明人： James B. Keller , Sridhar P. Subramanian , Ramesh Gunna
IPC分类号： G06F13/00 , G06F15/163
CPC分类号： G06F12/0831 , G06F13/362 , G06F13/4213 , Y02D10/13 , Y02D10/14 , Y02D10/151
摘要： An interface unit may comprise a buffer configured to store requests that are to be transmitted on an interconnect and a control unit coupled to the buffer. In one embodiment, the control unit is coupled to receive a retry response from the interconnect during a response phase of a first transaction for a first request stored in the buffer. The control unit is configured to record an identifier supplied on the interconnect with the retry response that identifies a second transaction that is in progress on the interconnect. The control unit is configured to inhibit reinitiation of the first transaction at least until detecting a second transmission of the identifier. In another embodiment, the control unit is configured to assert a retry response during a response phase of a first transaction responsive to a snoop hit of the first transaction on a first request stored in the buffer for which a second transaction is in progress on the interconnect. The control unit is further configured to provide an identifier of the second transaction with the retry response.
摘要翻译：接口单元可以包括被配置为存储要在互连上发送的请求的缓冲器和耦合到缓冲器的控制单元。在一个实施例中，控制单元被耦合以在对于存储在缓冲器中的第一请求的第一事务的响应阶段期间从互连接收重试响应。控制单元被配置为记录在互连上提供的标识符，该重试响应标识互连上正在进行的第二事务。控制单元被配置为至少在检测到标识符的第二次传输之前禁止第一事务的重新发起。在另一个实施例中，控制单元被配置为在第一事务的响应阶段响应第一事务的窥探命中在存储在第二事务在互连上的第二事务的缓冲器中的第一请求时断言重试响应。控制单元还被配置为提供具有重试响应的第二事务的标识符。

89. 发明授权

US07426601B2 Segmented interconnect for connecting multiple agents in a system 有权
标题翻译：用于连接系统中多个代理的分段互连
公开(公告)号：US07426601B2
公开(公告)日：2008-09-16
申请号：US11832841
申请日：2007-08-02
申请人： Sridhar P. Subramanian , James B. Keller , George Kong Yiu , Ruchi Wadhawan
发明人： Sridhar P. Subramanian , James B. Keller , George Kong Yiu , Ruchi Wadhawan
IPC分类号： G06F13/00 , G06F13/36
CPC分类号： G06F13/364 , G06F13/4022 , Y02D10/14 , Y02D10/151
摘要： In various embodiments, an apparatus comprises a plurality of agents and an interconnect. In one embodiment, the plurality of agents includes first through fourth agents. The interconnect comprises a plurality of segments that are switchable (e.g. using a plurality of selection circuits) to form communication paths between the agents, and a first segment is included in a first communication path from the first agent to the second agent, and is also included in a second communication path from the third agent to the fourth agent. In another embodiment, each segment is driven by a selection circuit. At least one selection circuit has at least one segment and an output from at least one agent as inputs. In yet another embodiment, an arbiter is configured to determine a communication path on the interconnect for each requesting agent to the destination agent over the segments. The arbiter is configured to arbitrate among a subset of requests for which each segment in the corresponding communication path is available.
摘要翻译：在各种实施例中，装置包括多个代理和互连。在一个实施方案中，多种试剂包括第一至第四试剂。互连包括可切换的多个段（例如，使用多个选择电路）以形成代理之间的通信路径，并且第一段包括在从第一代理到第二代理的第一通信路径中，并且还包括在从第三代理到第四代理的第二通信路径中。在另一实施例中，每个段由选择电路驱动。至少一个选择电路具有至少一个段和来自至少一个代理的输出作为输入。在另一个实施例中，仲裁器被配置为确定每个请求代理在该互连上的通信路径到该段上的目的地代理。仲裁器被配置为在对应的通信路径中的每个段可用的请求的子集之间进行仲裁。

90. 发明申请

US20080086622A1 Replay reduction for power saving 有权
标题翻译：节电减重
公开(公告)号：US20080086622A1
公开(公告)日：2008-04-10
申请号：US11546223
申请日：2006-10-10
申请人： Po-Yung Chang , Wei-Han Lien , Jesse Pan , Ramesh Gunna , Tse-Yu Yeh , James B. Keller
发明人： Po-Yung Chang , Wei-Han Lien , Jesse Pan , Ramesh Gunna , Tse-Yu Yeh , James B. Keller
IPC分类号： G06F9/30
CPC分类号： G06F9/3842
摘要： In one embodiment, a processor comprises a scheduler configured to issue a first instruction operation to be executed and an execution core coupled to the scheduler. Configured to execute the first instruction operation, the execution core comprises a plurality of replay sources configured to cause a replay of the first instruction operation responsive to detecting at least one of a plurality of replay cases. The scheduler is configured to inhibit issuance of the first instruction operation subsequent to the replay for a subset of the plurality of replay cases. The scheduler is coupled to receive an acknowledgement indication corresponding to each of the plurality of replay cases in the subset, and is configured to inhibit issuance of the first instruction operation until the acknowledge indication is asserted that corresponds to an identified replay case of the subset.
摘要翻译：在一个实施例中，处理器包括被配置为发出要执行的第一指令操作和耦合到调度器的执行核心的调度器。配置为执行第一指令操作，执行核心包括被配置为响应于检测多个重放情况中的至少一个而使第一指令操作重放的多个重放源。调度器被配置为禁止在多个重放情况的子集的重放之后发出第一指令操作。调度器被耦合以接收对应于子集中的多个重播案例中的每一个的确认指示，并且被配置为禁止发出第一指令操作，直到确认对应于所识别的该子集的重放情况为止的确认指示为止。

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