专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

81. 发明授权

US07217964B1 Method and apparatus for coupling to a source line in a memory device 有权
标题翻译：用于耦合到存储器件中的源极线的方法和装置
公开(公告)号：US07217964B1
公开(公告)日：2007-05-15
申请号：US10658937
申请日：2003-09-09
申请人： Richard M. Fastow , Kuo-Tung Chang
发明人： Richard M. Fastow , Kuo-Tung Chang
IPC分类号： H01L27/10
CPC分类号： H01L21/28273 , H01L27/115 , H01L27/11521 , H01L29/42324
摘要： A method and apparatus for coupling to a source line. Specifically, embodiments of the present invention disclose a memory device comprising an array of flash memory cells with a source line connection that facilitates straight word lines, and a method for producing the same. The array is comprised of a plurality of non-intersecting shallow trench isolation (STI) regions that isolate a plurality of memory cell columns. A source column implanted with n-type dopants is also isolated between an adjoining pair of STI regions. The source column is coupled to a plurality of common source lines that are coupled to a plurality of source regions in the array. A source contact is coupled to the source column for providing electrical coupling with the plurality of source regions. The source contact is located along a row of drain contacts that are coupled to drain regions of a row of memory cells.
摘要翻译：一种用于耦合到源极线的方法和装置。具体地，本发明的实施例公开了一种包括具有促进直线字线的源极线连接的闪存单元阵列的存储器件及其制造方法。阵列由隔离多个存储单元列的多个不相交的浅沟槽隔离（STI）区域组成。植入n型掺杂剂的源极柱也在相邻的一对STI区域之间隔离。源极列耦合到耦合到阵列中的多个源极区域的多个公共源极线。源极触点耦合到源极列，以提供与多个源极区域的电耦合。源极触点沿着一排漏极触点排列，这些漏极触点被耦合到一行存储器单元的漏极区域。

82. 发明授权

US07170130B2 Memory cell with reduced DIBL and Vss resistance 有权
标题翻译：具有降低的DIBL和Vss电阻的存储单元
公开(公告)号：US07170130B2
公开(公告)日：2007-01-30
申请号：US10915771
申请日：2004-08-11
申请人： Shenqing Fang , Kuo-Tung Chang , Pavel Fastenko , Zhigang Wang
发明人： Shenqing Fang , Kuo-Tung Chang , Pavel Fastenko , Zhigang Wang
IPC分类号： H01L29/788
CPC分类号： H01L29/66825
摘要： According to one exemplary embodiment, a method for fabricating a floating gate memory cell on substrate comprises a step of forming a spacer adjacent to a source sidewall of a stacked gate structure, where the stacked gate structure is situated over a channel region in substrate. The method further comprises forming a high energy implant doped region adjacent to the spacer in the source region of substrate. The method further comprises forming a recess in a source region of the substrate, where the recess has a sidewall, a bottom, and a depth, and where the sidewall of the recess is situated adjacent to a source of the floating gate memory cell. According to this exemplary embodiment, the spacer causes the source to have a reduced lateral straggle and diffusion in the channel region, which causes a reduction in drain induced barrier lowering (DIBL) in the floating gate memory cell.
摘要翻译：根据一个示例性实施例，用于在衬底上制造浮动栅极存储器单元的方法包括形成与层叠栅极结构的源极侧壁相邻的间隔物的步骤，其中堆叠的栅极结构位于衬底中的沟道区域之上。该方法还包括在衬底的源区中形成与间隔物相邻的高能注入掺杂区。该方法还包括在衬底的源极区域中形成凹部，其中凹部具有侧壁，底部和深度，并且凹部的侧壁位于与浮动栅极存储单元的源极相邻的位置。根据该示例性实施例，间隔件导致源极在通道区域中具有减小的横向偏移和扩散，这导致浮动栅极存储单元中的漏极感应势垒降低（DIBL）的减小。

83. 发明申请

US20060286750A1 Method and system for forming straight word lines in a flash memory array 有权
公开(公告)号：US20060286750A1
公开(公告)日：2006-12-21
申请号：US11155707
申请日：2005-06-17
申请人： Shenqing Fang , Hiroyuki Ogawa , Kuo-Tung Chang , Pavel Fastenko , Kazuhiro Mizutani , Zhigang Wang
发明人： Shenqing Fang , Hiroyuki Ogawa , Kuo-Tung Chang , Pavel Fastenko , Kazuhiro Mizutani , Zhigang Wang
IPC分类号： H01L21/336
CPC分类号： H01L29/7883 , H01L21/2652 , H01L27/115 , H01L27/11521 , H01L29/66825
摘要： Embodiments of the present invention disclose a memory device having an array of flash memory cells with source contacts that facilitate straight word lines, and a method for producing the same. The array is comprised of a plurality of non-intersecting shallow trench isolation (STI) regions that isolate a plurality of memory cell columns. A source column is implanted with n-type dopants after the formation of a tunnel oxide layer and a first polysilicon layer. The implanted source column is coupled to a plurality of common source lines that are coupled to a plurality of source regions associated with memory cells in the array. A source contact is coupled to the implanted source column for providing electrical coupling with the plurality of source regions. The source contact is collinear with a row of drain contacts that are coupled to drain regions associated with a row of memory cells. The arrangement of source contacts collinear with the row of drain contacts allows for straight word line formation.

84. 发明授权

US07151027B1 Method and device for reducing interface area of a memory device 有权
标题翻译：用于减少存储器件的接口面积的方法和装置
公开(公告)号：US07151027B1
公开(公告)日：2006-12-19
申请号：US10859369
申请日：2004-06-01
申请人： Hiroyuki Ogawa , Yider Wu , Kuo-Tung Chang , Yu Sun
发明人： Hiroyuki Ogawa , Yider Wu , Kuo-Tung Chang , Yu Sun
IPC分类号： H01L21/336
CPC分类号： H01L27/105 , H01L27/11526 , H01L27/11536 , H01L27/11548
摘要： A method and device for reducing interface area of a memory device. A poly-2 layer is formed above a substrate at an interface between a memory array and a periphery of the memory device. The poly-2 layer is etched proximate to the memory array. The poly-2 layer is etched proximate to the periphery such that a portion of the poly-2 layer remains at the interface.
摘要翻译：一种用于减少存储器件的接口面积的方法和装置。在存储器阵列和存储器件的外围之间的界面处，在衬底上形成多晶硅层2。聚二层蚀刻到存储器阵列附近。聚二层被蚀刻到外围附近，使得多2层的一部分保留在界面处。

85. 发明授权

US06919247B1 Method of fabricating a floating gate 失效
标题翻译：制造浮栅的方法
公开(公告)号：US06919247B1
公开(公告)日：2005-07-19
申请号：US10655936
申请日：2003-09-04
申请人： Yider Wu , Kuo-Tung Chang
发明人： Yider Wu , Kuo-Tung Chang
IPC分类号： H01L21/28 , H01L21/8247
CPC分类号： H01L21/28273
摘要： A method of fabricating a floating gate for a semiconductor device is disclosed and provided. According to this method, an undoped polycrystalline silicon layer is deposited on a tunnel oxide layer. The undoped polycrystalline silicon layer has a first thickness. Moreover, a doped polycrystalline silicon layer is deposited on the undoped polycrystalline silicon layer. The doped polycrystalline silicon layer has a second thickness. The undoped polycrystalline silicon layer and the doped polycrystalline silicon layer form the floating gate having a third thickness. In an embodiment, the semiconductor device is a flash memory device.
摘要翻译：公开并提供了制造用于半导体器件的浮栅的方法。根据该方法，在隧道氧化物层上沉积未掺杂的多晶硅层。未掺杂的多晶硅层具有第一厚度。此外，掺杂的多晶硅层沉积在未掺杂的多晶硅层上。掺杂多晶硅层具有第二厚度。未掺杂多晶硅层和掺杂多晶硅层形成具有第三厚度的浮动栅极。在一个实施例中，半导体器件是闪存器件。

86. 发明申请

US20050151265A1 Efficient use of wafer area with device under the pad approach 审中-公开
标题翻译：利用垫片方式下的设备有效利用晶圆区域
公开(公告)号：US20050151265A1
公开(公告)日：2005-07-14
申请号：US10758148
申请日：2004-01-14
申请人： Nian Yang , Hiroyuki Ogawa , Yider Wu , Kuo-Tung Chang , Yu Sun , Darlene Hamilton
发明人： Nian Yang , Hiroyuki Ogawa , Yider Wu , Kuo-Tung Chang , Yu Sun , Darlene Hamilton
IPC分类号： G06F17/50 , H01L23/485 , H01L27/02 , H01L23/48 , H01L21/44
CPC分类号： H01L27/0203 , H01L24/05 , H01L24/06 , H01L2224/02166 , H01L2224/05093 , H01L2224/05096 , H01L2224/05556 , H01L2224/05624 , H01L2224/05639 , H01L2224/05644 , H01L2224/05647 , H01L2224/05684 , H01L2924/01013 , H01L2924/01014 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01074 , H01L2924/01079 , H01L2924/14 , H01L2924/19043 , H01L2924/00014
摘要： More efficient use of silicon area is achieved by incorporating an active device beneath a pad area of a semiconductor structure. The pad area includes a substrate having a first metal layer above it. A second metal layer is below the first metal layer. The active device resides in the substrate below the second metal layer. A layer of dielectric separates the first and second metal layers. A via within the dielectric layer electrically couples the first and second metal layers. A via connects to the active component. Subsequent metal layers can be arranged between the first and second metal layers.
摘要翻译：通过在半导体结构的焊盘区域的下方并入有源器件来实现硅面积的更有效的使用。焊盘区域包括在其上方具有第一金属层的基板。第二金属层位于第一金属层的下方。有源器件位于第二金属层下方的衬底中。电介质层分离第一和第二金属层。电介质层内的通孔电耦合第一和第二金属层。 A通道连接到活动组件。随后的金属层可以布置在第一和第二金属层之间。

87. 发明授权

US06545310B2 Non-volatile memory with a serial transistor structure with isolated well and method of operation 失效
公开(公告)号：US06545310B2
公开(公告)日：2003-04-08
申请号：US09845117
申请日：2001-04-30
申请人： Chi Nan Brian Li , Kuo-Tung Chang
发明人： Chi Nan Brian Li , Kuo-Tung Chang
IPC分类号： H01L2976
CPC分类号： H01L27/115 , G11C16/0483 , G11C16/10 , Y10S257/905 , Y10S257/909
摘要： A first plurality of memory cells (32, 33) connected in series lies within a first well (47) that is separated and electrically isolated (42) from a second plurality of memory cells (36 et al.) connected in series lying within a second well (46). In one embodiment, the first and second wells (46, 47) are doped p-type and are contained within an n-well (48) and a substrate (49). Applying a negative voltage to its corresponding bit line and a positive voltage to its corresponding word line programs a predetermined memory cell within the first plurality. A lesser positive voltage than that applied to the predetermined memory cell's word line is applied to all other bit lines and word lines of non-selected memory cells. By utilizing a negative voltage while programming a memory cell, the magnitude of programming voltages is reduced, thereby, removing the need for an elaborate charge pump to generate a much higher programming voltage.

88. 发明授权

US5969383A Split-gate memory device and method for accessing the same 失效
标题翻译：分闸存储器件及其访问方法
公开(公告)号：US5969383A
公开(公告)日：1999-10-19
申请号：US876576
申请日：1997-06-16
申请人： Kuo-Tung Chang , Ko-Min Chang , Wei-Ming Chen , Keith Forbes , Douglas R. Roberts
发明人： Kuo-Tung Chang , Ko-Min Chang , Wei-Ming Chen , Keith Forbes , Douglas R. Roberts
IPC分类号： G11C16/04 , H01L21/28 , H01L21/8247 , H01L27/115 , H01L29/423 , H01L29/788 , H01L29/792
CPC分类号： H01L21/28282 , H01L29/42324 , H01L29/7885 , H01L29/792
摘要： An EEPROM device includes a split-gate FET (10) having a source (36), a drain (22), a select gate (16) adjacent the drain (22), and a control gate (32) adjacent the source (36). When programming the split-gate FET (10), electrons are accelerated in a portion of a channel region (38) between the select gate (16) and the control gate (32), and then injected into a nitride layer (24) of an ONO stack (25) underlying the control gate (32). The split-gate FET (10) is erased by injecting holes from the channel region (38) into the charge nitride layer (24). When reading data from the split-gate FET (10), a reading voltage is applied to the drain (22) adjacent the select gate (16). Data is then read from the split-gate FET (10) by sensing a current flowing in a bit line coupled to the drain (22).
摘要翻译： EEPROM器件包括具有源极（36），漏极（22），与漏极（22）相邻的选择栅极（16））和邻近源极（36）的控制栅极（32）的分离栅极FET（10））。当对分离栅极FET（10）进行编程时，在选择栅极（16）和控制栅极（32）之间的沟道区域（38）的一部分中电子被加速，然后注入氮化物层（24）位于控制门（32）下方的ONO堆叠（25）。通过从沟道区（38）将空穴注入到电荷氮化物层（24）中，分裂栅FET（10）被擦除。当从分离栅极FET（10）读取数据时，读取电压被施加到与选择栅极（16）相邻的漏极（22）。然后通过感测在耦合到漏极（22）的位线中流动的电流，从分离栅极FET（10）读取数据。

89. 发明授权

US5471422A EEPROM cell with isolation transistor and methods for making and operating the same 失效
标题翻译：具有隔离晶体管的EEPROM单元及其制造和操作的方法
公开(公告)号：US5471422A
公开(公告)日：1995-11-28
申请号：US225868
申请日：1994-04-11
申请人： Ko-Min Chang , Danny P. Shum , Kuo-Tung Chang
发明人： Ko-Min Chang , Danny P. Shum , Kuo-Tung Chang
IPC分类号： G11C17/00 , G11C16/04 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792 , G11C11/34 , H01L29/68
CPC分类号： H01L27/115 , H01L29/7883
摘要： An EEPROM cell (40) includes a floating gate transistor (47) and an isolation transistor (45). Both a floating gate (48) and an isolation gate (46) are formed on a tunnel dielectric (44) within the cell. The isolation gate is coupled to a doped source region (52) of the floating gate transistor. The isolation transistor is not biased during a program operation of the cell, enabling a thin tunnel dielectric (less than 120 angstroms) to be used beneath all portions of both gates within the cell. Thus, the need for both a conventional tunnel dielectric and a gate dielectric is eliminated. The cell tolerates over-erasure, can be programmed at low programming voltages, and has good current drive due to the thin tunnel dielectric throughout the cell.
摘要翻译： EEPROM单元（40）包括浮栅晶体管（47）和隔离晶体管（45）。浮动栅极（48）和隔离栅极（46）均形成在电池内的隧道电介质（44）上。隔离栅极耦合到浮栅晶体管的掺杂源极区（52）。在单元的编程操作期间，隔离晶体管不被偏置，使得能够在单元内的两个栅极的所有部分之下使用薄的隧道电介质（小于120埃）。因此，消除了对常规隧道电介质和栅极电介质的需要。电池容忍过度擦除，可以在低编程电压下编程，并且由于整个电池中的薄隧道电介质而具有良好的电流驱动。

90. 发明授权

US5429969A Process for forming electrically programmable read-only memory cell with a merged select/control gate 失效
标题翻译：用于形成具有合并的选择/控制门的电可编程只读存储器单元的处理
公开(公告)号：US5429969A
公开(公告)日：1995-07-04
申请号：US251162
申请日：1994-05-31
申请人： Kuo-Tung Chang
发明人： Kuo-Tung Chang
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/423
CPC分类号： H01L27/11521 , H01L27/115 , H01L29/42324 , Y10S257/90
摘要： Flash EEPROM cells having merged select/control gates may be formed, so that the portions of the channel regions that correspond to select transistors are formed after spacers are formed but prior to patterning a merged select/control gate layer. Because the portions of the channel regions that correspond to the select transistors are not determined by the patterning of the merged select/control gate layer, misalignment of the mask used to pattern the merged select/control gate layer does not affect the size of the select transistor portion of the channel region. The spacers may be left on over the substrate in the finished devices thereby saving at least one processing step. The memory structure may also be used in other EPROM-type memory cells, such as individually erasable EEPROMs and EPROMs that are not electrically erasable.
摘要翻译：可以形成具有合并的选择/控制栅极的闪速EEPROM单元，使得对应于选择晶体管的沟道区域的部分在形成间隔物之后但在构图合并的选择/控制栅极层之前形成。由于与选择晶体管相对应的沟道区域的部分不是通过合并选择/控制栅极层的构图来确定的，所以用于对合并的选择/控制栅极层进行图案化的掩模的未对准不会影响选择晶体管部分。间隔物可以留在成品装置中的衬底上，从而节省至少一个处理步骤。存储器结构也可以用于其它EPROM型存储单元，例如不可电擦除的单独可擦除EEPROM和EPROM。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式