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1. 发明授权

US07851306B2 Method for forming a flash memory device with straight word lines 有权
标题翻译：用于形成具有直线字线的闪速存储器件的方法
公开(公告)号：US07851306B2
公开(公告)日：2010-12-14
申请号：US12327641
申请日：2008-12-03
申请人： Shenqing Fang , Hiroyuki Ogawa , Kuo-Tung Chang , Pavel Fastenko , Kazuhiro Mizutani , Zhigang Wang
发明人： Shenqing Fang , Hiroyuki Ogawa , Kuo-Tung Chang , Pavel Fastenko , Kazuhiro Mizutani , Zhigang Wang
IPC分类号： H01L21/336
CPC分类号： H01L29/7883 , H01L21/2652 , H01L27/115 , H01L27/11521 , H01L29/66825
摘要： Embodiments of the present invention disclose a memory device having an array of flash memory cells with source contacts that facilitate straight word lines, and a method for producing the same. The array is comprised of a plurality of non-intersecting shallow trench isolation (STI) regions that isolate a plurality of memory cell columns. A source column is implanted with n-type dopants after the formation of a tunnel oxide layer and a first polysilicon layer. The implanted source column is coupled to a plurality of common source lines that are coupled to a plurality of source regions associated with memory cells in the array. A source contact is coupled to the implanted source column for providing electrical coupling with the plurality of source regions. The source contact is collinear with a row of drain contacts that are coupled to drain regions associated with a row of memory cells. The arrangement of source contacts collinear with the row of drain contacts allows for straight word line formation.
摘要翻译：本发明的实施例公开了一种存储器件，其具有具有促进直线字线的源极触点的闪存单元阵列及其制造方法。阵列由隔离多个存储单元列的多个不相交的浅沟槽隔离（STI）区域组成。在形成隧道氧化物层和第一多晶硅层之后，源极列注入n型掺杂剂。植入的源极柱耦合到耦合到与阵列中的存储器单元相关联的多个源极区域的多个公共源极线。源极触点耦合到植入源极柱，用于提供与多个源极区域的电耦合。源触点与一排漏极触点共线，该排触点耦合到与一行存储器单元相关联的漏极区。与漏极触点排共线的源触点的布置允许直线字线形成。

2. 发明授权

US07488657B2 Method and system for forming straight word lines in a flash memory array 有权
标题翻译：用于在闪存阵列中形成直线字线的方法和系统
公开(公告)号：US07488657B2
公开(公告)日：2009-02-10
申请号：US11155707
申请日：2005-06-17
申请人： Shenqing Fang , Hiroyuki Ogawa , Kuo-Tung Chang , Pavel Fastenko , Kazuhiro Mizutani , Zhigang Wang
发明人： Shenqing Fang , Hiroyuki Ogawa , Kuo-Tung Chang , Pavel Fastenko , Kazuhiro Mizutani , Zhigang Wang
IPC分类号： H01L21/336
CPC分类号： H01L29/7883 , H01L21/2652 , H01L27/115 , H01L27/11521 , H01L29/66825
摘要： Embodiments of the present invention disclose a memory device having an array of flash memory cells with source contacts that facilitate straight word lines, and a method for producing the same. The array is comprised of a plurality of non-intersecting shallow trench isolation (STI) regions that isolate a plurality of memory cell columns. A source column is implanted with n-type dopants after the formation of a tunnel oxide layer and a first polysilicon layer. The implanted source column is coupled to a plurality of common source lines that are coupled to a plurality of source regions associated with memory cells in the array. A source contact is coupled to the implanted source column for providing electrical coupling with the plurality of source regions. The source contact is collinear with a row of drain contacts that are coupled to drain regions associated with a row of memory cells. The arrangement of source contacts collinear with the row of drain contacts allows for straight word line formation.
摘要翻译：本发明的实施例公开了一种存储器件，其具有具有促进直线字线的源极触点的闪存单元阵列及其制造方法。阵列由隔离多个存储单元列的多个不相交的浅沟槽隔离（STI）区域组成。在形成隧道氧化物层和第一多晶硅层之后，源极列注入n型掺杂剂。植入的源极柱耦合到耦合到与阵列中的存储器单元相关联的多个源极区域的多个公共源极线。源极触点耦合到植入源极柱，用于提供与多个源极区域的电耦合。源触点与一排漏极触点共线，该排触点耦合到与一行存储器单元相关联的漏极区。与漏极触点排共线的源触点的布置允许直线字线形成。

3. 发明申请

US20060286750A1 Method and system for forming straight word lines in a flash memory array 有权
公开(公告)号：US20060286750A1
公开(公告)日：2006-12-21
申请号：US11155707
申请日：2005-06-17
申请人： Shenqing Fang , Hiroyuki Ogawa , Kuo-Tung Chang , Pavel Fastenko , Kazuhiro Mizutani , Zhigang Wang
发明人： Shenqing Fang , Hiroyuki Ogawa , Kuo-Tung Chang , Pavel Fastenko , Kazuhiro Mizutani , Zhigang Wang
IPC分类号： H01L21/336
CPC分类号： H01L29/7883 , H01L21/2652 , H01L27/115 , H01L27/11521 , H01L29/66825
摘要： Embodiments of the present invention disclose a memory device having an array of flash memory cells with source contacts that facilitate straight word lines, and a method for producing the same. The array is comprised of a plurality of non-intersecting shallow trench isolation (STI) regions that isolate a plurality of memory cell columns. A source column is implanted with n-type dopants after the formation of a tunnel oxide layer and a first polysilicon layer. The implanted source column is coupled to a plurality of common source lines that are coupled to a plurality of source regions associated with memory cells in the array. A source contact is coupled to the implanted source column for providing electrical coupling with the plurality of source regions. The source contact is collinear with a row of drain contacts that are coupled to drain regions associated with a row of memory cells. The arrangement of source contacts collinear with the row of drain contacts allows for straight word line formation.

4. 发明授权

US07151028B1 Memory cell with plasma-grown oxide spacer for reduced DIBL and Vss resistance and increased reliability 有权
标题翻译：具有等离子体生长氧化物间隔物的存储单元用于降低DIBL和Vss电阻并增加可靠性
公开(公告)号：US07151028B1
公开(公告)日：2006-12-19
申请号：US10981174
申请日：2004-11-04
申请人： Shenqing Fang , Rinji Sugino , Kuo-Tung Chang , Zhigang Wang , Kazuhiro Mizutani , Pavel Fastenko
发明人： Shenqing Fang , Rinji Sugino , Kuo-Tung Chang , Zhigang Wang , Kazuhiro Mizutani , Pavel Fastenko
IPC分类号： H01L21/26
CPC分类号： H01L29/66636 , H01L29/1037 , H01L29/66659 , H01L29/66825 , H01L29/7881
摘要： According to one exemplary embodiment, a method for fabricating a floating gate memory cell on a substrate comprises a step of forming a first spacer adjacent to a source sidewall of a stacked gate structure, where the stacked gate structure is situated over a channel region in the substrate. The method further comprises forming a high energy implant doped region adjacent to the first spacer in a source region of the substrate. The method further comprises forming a recess in the source region, where a sidewall of the recess is situated adjacent to a source of the floating gate memory cell, and where forming the recess comprises removing the first spacer. The method further comprises forming a second spacer adjacent to the source sidewall of the stacked gate structure, where the second spacer extends to a bottom of the recess, and where the second spacer comprises plasma-grown oxide.
摘要翻译：根据一个示例性实施例，用于在衬底上制造浮动栅极存储器单元的方法包括形成邻近层叠栅极结构的源极侧壁的第一间隔物的步骤，其中堆叠的栅极结构位于基质。该方法还包括在衬底的源区中形成与第一间隔物相邻的高能注入掺杂区。该方法还包括在源极区域中形成凹部，其中凹部的侧壁位于与浮动栅极存储单元的源极相邻处，并且其中形成凹槽包括移除第一间隔物。该方法还包括形成邻近层叠栅极结构的源极侧壁的第二间隔物，其中第二间隔物延伸到凹部的底部，并且其中第二间隔物包括等离子体生长的氧化物。

5. 发明申请

US20060035431A1 Memory cell with reduced DIBL and Vss resistance 有权
标题翻译：具有降低的DIBL和Vss电阻的存储单元
公开(公告)号：US20060035431A1
公开(公告)日：2006-02-16
申请号：US10915771
申请日：2004-08-11
申请人： Shenqing Fang , Kuo-Tung Chang , Pavel Fastenko , Zhigang Wang
发明人： Shenqing Fang , Kuo-Tung Chang , Pavel Fastenko , Zhigang Wang
IPC分类号： H01L21/336
CPC分类号： H01L29/66825
摘要： According to one exemplary embodiment, a method for fabricating a floating gate memory cell on substrate comprises a step of forming a spacer adjacent to a source sidewall of a stacked gate structure, where the stacked gate structure is situated over a channel region in substrate. The method further comprises forming a high energy implant doped region adjacent to the spacer in the source region of substrate. The method further comprises forming a recess in a source region of the substrate, where the recess has a sidewall, a bottom, and a depth, and where the sidewall of the recess is situated adjacent to a source of the floating gate memory cell. According to this exemplary embodiment, the spacer causes the source to have a reduced lateral straggle and diffusion in the channel region, which causes a reduction in drain induced barrier lowering (DIBL) in the floating gate memory cell.
摘要翻译：根据一个示例性实施例，用于在衬底上制造浮动栅极存储器单元的方法包括形成与层叠栅极结构的源极侧壁相邻的间隔物的步骤，其中堆叠的栅极结构位于衬底中的沟道区域之上。该方法还包括在衬底的源区中形成与间隔物相邻的高能注入掺杂区。该方法还包括在衬底的源极区域中形成凹部，其中凹部具有侧壁，底部和深度，并且凹部的侧壁位于与浮动栅极存储单元的源极相邻的位置。根据该示例性实施例，间隔件导致源极在通道区域中具有减小的横向偏移和扩散，这导致浮动栅极存储单元中的漏极感应势垒降低（DIBL）的减小。

6. 发明授权

US07170130B2 Memory cell with reduced DIBL and Vss resistance 有权
标题翻译：具有降低的DIBL和Vss电阻的存储单元
公开(公告)号：US07170130B2
公开(公告)日：2007-01-30
申请号：US10915771
申请日：2004-08-11
申请人： Shenqing Fang , Kuo-Tung Chang , Pavel Fastenko , Zhigang Wang
发明人： Shenqing Fang , Kuo-Tung Chang , Pavel Fastenko , Zhigang Wang
IPC分类号： H01L29/788
CPC分类号： H01L29/66825
摘要： According to one exemplary embodiment, a method for fabricating a floating gate memory cell on substrate comprises a step of forming a spacer adjacent to a source sidewall of a stacked gate structure, where the stacked gate structure is situated over a channel region in substrate. The method further comprises forming a high energy implant doped region adjacent to the spacer in the source region of substrate. The method further comprises forming a recess in a source region of the substrate, where the recess has a sidewall, a bottom, and a depth, and where the sidewall of the recess is situated adjacent to a source of the floating gate memory cell. According to this exemplary embodiment, the spacer causes the source to have a reduced lateral straggle and diffusion in the channel region, which causes a reduction in drain induced barrier lowering (DIBL) in the floating gate memory cell.
摘要翻译：根据一个示例性实施例，用于在衬底上制造浮动栅极存储器单元的方法包括形成与层叠栅极结构的源极侧壁相邻的间隔物的步骤，其中堆叠的栅极结构位于衬底中的沟道区域之上。该方法还包括在衬底的源区中形成与间隔物相邻的高能注入掺杂区。该方法还包括在衬底的源极区域中形成凹部，其中凹部具有侧壁，底部和深度，并且凹部的侧壁位于与浮动栅极存储单元的源极相邻的位置。根据该示例性实施例，间隔件导致源极在通道区域中具有减小的横向偏移和扩散，这导致浮动栅极存储单元中的漏极感应势垒降低（DIBL）的减小。

7. 发明授权

US08896048B1 Apparatus and method for source side implantation after spacer formation to reduce short channel effects in metal oxide semiconductor field effect transistors 有权
标题翻译：间隔物形成后源侧注入的装置和方法，以减少金属氧化物半导体场效应晶体管的短沟道效应
公开(公告)号：US08896048B1
公开(公告)日：2014-11-25
申请号：US10861581
申请日：2004-06-04
申请人： Richard Fastow , Zhigang Wang , Yue-Song He , Kazuhiro Mizutani , Pavel Fastenko
发明人： Richard Fastow , Zhigang Wang , Yue-Song He , Kazuhiro Mizutani , Pavel Fastenko
IPC分类号： H01L29/76
CPC分类号： H01L29/66659 , H01L29/66825 , H01L29/7881
摘要： The present invention provides an apparatus and method for a metal oxide semiconductor field effect transistor (MOSFET) fabricated to reduce short channel effects. The MOSFET includes a semiconductor substrate, a gate stack formed above the semiconductor substrate, a drain side sidewall spacer formed on a drain side of the gate stack, a source side sidewall spacer formed on a source side of the gate stack, and source and drain regions. The source region is formed in the semiconductor substrate on the source side, and is aligned by the source side sidewall spacer to extend an effective channel length between the source region and drain region. The drain region is formed on the drain side in the semiconductor substrate, and is aligned by drain side sidewall spacer to further extend the effective channel length.
摘要翻译：本发明提供一种制造用于减少短沟道效应的金属氧化物半导体场效应晶体管（MOSFET）的装置和方法。 MOSFET包括半导体衬底，形成在半导体衬底上方的栅极堆叠，形成在栅极堆叠的漏极侧的漏极侧壁间隔物，形成在栅极堆叠的源极侧的源极侧壁隔离物，以及源极和漏极地区。源极区域形成在源极侧的半导体衬底中，并且通过源极侧壁间隔物对齐以在源极区域和漏极区域之间延伸有效沟道长度。漏极区域形成在半导体衬底的漏极侧，并且通过漏极侧壁间隔物排列以进一步延长有效沟道长度。

8. 发明授权

US06576487B1 Method to distinguish an STI outer edge current component with an STI normal current component 失效
标题翻译：区分STI外缘电流分量与STI正常电流分量的方法
公开(公告)号：US06576487B1
公开(公告)日：2003-06-10
申请号：US10126363
申请日：2002-04-19
申请人： Zhigang Wang , Harpreet Kaur Sachar , Kuo-Tung Chang
发明人： Zhigang Wang , Harpreet Kaur Sachar , Kuo-Tung Chang
IPC分类号： G01R3126
CPC分类号： H01L22/34 , H01L21/76229 , H01L21/76232
摘要： The present invention details a method which characterizes an STI fabrication process, and more particularly provides information relating to a variation in the STI sidewall profile between trenches in a middle portion of an array and a trench on an outer portion thereof. The method comprises forming two STI arrays with an STI fabrication process, forming a conductive layer over each array, biasing each conductive layer and determining a current associated therewith. The two current are then utilized to ascertain the variation of interest.
摘要翻译：本发明详细描述了一种表征STI制造工艺的方法，并且更具体地提供了与阵列的中间部分中的沟槽和其外部部分上的沟槽之间的STI侧壁轮廓变化有关的信息。该方法包括用STI制造工艺形成两个STI阵列，在每个阵列上形成导电层，偏置每个导电层并确定与之相关联的电流。然后利用两个电流来确定兴趣的变化。

9. 发明授权

US06987696B1 Method of improving erase voltage distribution for a flash memory array having dummy wordlines 有权
标题翻译：提高具有虚拟字线的闪存阵列的擦除电压分布的方法
公开(公告)号：US06987696B1
公开(公告)日：2006-01-17
申请号：US10885268
申请日：2004-07-06
申请人： Zhigang Wang , Nian Yang , Shenqing Fang
发明人： Zhigang Wang , Nian Yang , Shenqing Fang
IPC分类号： G11C16/00
CPC分类号： G11C16/16 , G11C16/0491 , H01L27/115
摘要： Techniques for erasing memory devices of a flash memory array having a plurality of operative wordlines and at least one dummy wordline adjacent an end one of the operative wordlines are disclosed. Erasing the memory devices can include applying a gate voltage to the wordlines and applying a bias voltage to the dummy wordlines. In one arrangement, an electrical connection is established between the dummy wordline and the end one of the operative wordlines.
摘要翻译：公开了一种用于擦除具有多个操作字线的闪速存储器阵列的存储器件以及与操作字线的末端相邻的至少一个伪字线的技术。擦除存储器件可以包括将栅极电压施加到字线并将偏置电压施加到伪字线。在一种布置中，在伪字线和操作字线的末端之间建立电连接。

10. 发明申请

US20070037371A1 Method of forming gate electrode structures 审中-公开
标题翻译：形成栅电极结构的方法
公开(公告)号：US20070037371A1
公开(公告)日：2007-02-15
申请号：US11201042
申请日：2005-08-10
申请人： Zhigang Wang , Nian Yang , Shenqing Fang
发明人： Zhigang Wang , Nian Yang , Shenqing Fang
IPC分类号： H01L21/3205
CPC分类号： H01L21/32139 , H01L21/28123
摘要： In one example, the method includes forming a patterned hard mask feature above a layer of gate electrode material, the hard mask feature having a photoresist feature formed thereabove and the hard mask feature having a critical dimension. The method further includes performing an etching process on the patterned hard mask feature to produce a reduced hard mask feature having a critical dimension that is less than the critical dimension of the patterned hard mask feature and performing an anisotropic etching process on the layer of gate electrode material using the reduced hard mask feature as a mask to define a gate electrode.
摘要翻译：在一个示例中，该方法包括在栅电极材料层之上形成图案化的硬掩模特征，硬掩模特征具有形成在其上的光致抗蚀剂特征以及具有临界尺寸的硬掩模特征。该方法还包括对图案化的硬掩模特征进行蚀刻处理以产生具有小于图案化硬掩模特征的临界尺寸的临界尺寸并且在栅电极层上执行各向异性蚀刻工艺的减小的硬掩模特征使用减少的硬掩模特征作为掩模的材料来限定栅电极。

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