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81. 发明授权

US5905285A Ultra short trench transistors and process for making same 失效
标题翻译：超短沟槽晶体管及其制造方法
公开(公告)号：US5905285A
公开(公告)日：1999-05-18
申请号：US31570
申请日：1998-02-26
申请人： Mark I. Gardner , Fred N. Hause
发明人： Mark I. Gardner , Fred N. Hause
IPC分类号： H01L21/336 , H01L29/78 , H01L27/088
CPC分类号： H01L29/66621 , H01L29/7834 , Y10S257/90
摘要： A field effect transistor comprising a semiconductor substrate having a transistor trench extending downward from an upper surface of the semiconductor substrate. The trench extends to a trench depth below an upper surface of the semiconductor substrate. The transistor further includes a gate dielectric layer that is formed on a floor of the transistor trench over a channel region of the semiconductor substrate. A conductive gate structure is formed above and in contact with the gate dielectric layer. A source/drain impurity distribution is formed within a source/drain region of the semiconductor substrate. The source/drain region is laterally disposed on either side of the channel region of the semiconductor substrate. In a preferred embodiment, the trench depth is between 1,000-5,000 angstroms and a thickness of the conductive gate structure is less than 5,000 angstroms such that an upper surface of the conductive gate structure is level with or below an upper surface of the semiconductor substrate. The gate dielectric layer suitably comprises a thermal oxide having a thickness of approximately 20-200 angstroms. In a lightly doped drain (LDD) embodiment, the source/drain impurity distribution includes a lightly doped region and a heavily doped region. The lightly doped region extends laterally from the channel region of the transistor to the heavily doped region. In the preferred embodiment, a lateral dimension of the channel region of the transistor is approximately 100-300 nm.
摘要翻译：一种场效应晶体管，包括具有从半导体衬底的上表面向下延伸的晶体管沟槽的半导体衬底。沟槽延伸到半导体衬底的上表面下方的沟槽深度。晶体管还包括形成在半导体衬底的沟道区上的晶体管沟槽的底板上的栅介质层。导电栅极结构形成在栅介电层的上方并与其接触。源极/漏极杂质分布形成在半导体衬底的源极/漏极区域内。源极/漏极区域横向地设置在半导体衬底的沟道区域的任一侧上。在优选实施例中，沟槽深度在1,000-5,000埃之间，并且导电栅极结构的厚度小于5000埃，使得导电栅极结构的上表面与半导体衬底的上表面平行或低于半导体衬底的上表面。栅介质层适当地包括厚度约为20-200埃的热氧化物。在轻掺杂漏极（LDD）实施例中，源极/漏极杂质分布包括轻掺杂区域和重掺杂区域。轻掺杂区域从晶体管的沟道区域横向延伸到重掺杂区域。在优选实施例中，晶体管的沟道区的横向尺寸约为100-300nm。

82. 发明授权

US5885887A Method of making an igfet with selectively doped multilevel polysilicon gate 失效
标题翻译：用选择性掺杂多电平多晶硅栅极制造igfet的方法
公开(公告)号：US5885887A
公开(公告)日：1999-03-23
申请号：US847752
申请日：1997-04-21
申请人： Frederick N. Hause , Robert Dawson , H. Jim Fulford Jr. , Mark I. Gardner , Mark W. Michael , Bradley T. Moore , Derick J. Wristers
发明人： Frederick N. Hause , Robert Dawson , H. Jim Fulford Jr. , Mark I. Gardner , Mark W. Michael , Bradley T. Moore , Derick J. Wristers
IPC分类号： H01L21/28 , H01L21/336 , H01L21/8238 , H01L29/423 , H01L21/38
CPC分类号： H01L29/6659 , H01L21/28114 , H01L21/823842 , H01L29/42376
摘要： A method of making an IGFET with a selectively doped multilevel polysilicon gate that includes upper and lower polysilicon gate levels is disclosed. The method includes providing a semiconductor substrate with an active region, forming a gate insulator on the active region, forming a a lower polysilicon layer on the gate insulator, forming a first masking layer over the lower polysilicon layer, etching the lower polysilicon layer through openings in the first masking layer using the first masking layer as an etch mask for a portion of the lower polysilicon layer that forms the lower polysilicon gate level over the active region, removing the first masking layer, forming the upper polysilicon gate level on the lower polysilicon gate level after removing the first masking layer, introducing a dopant into the upper polysilicon gate level without introducing the dopant into the substrate, diffusing the dopant from the upper polysilicon gate level into the lower polysilicon gate level, and forming a source and drain in the active region. Advantageously, the lower polysilicon gate level has both an accurately defined length to provide the desired channel length and a well-controlled doping concentration to provide the desired threshold voltage.
摘要翻译：公开了一种制造具有选择性掺杂多电平多晶硅栅极的IGFET的方法，其包括上和下多晶硅栅极电平。该方法包括提供具有有源区的半导体衬底，在有源区上形成栅极绝缘体，在栅极绝缘体上形成下部多晶硅层，在下部多晶硅层上形成第一掩蔽层，通过下部多晶硅层的开口蚀刻下部多晶硅层所述第一掩模层使用所述第一掩模层作为用于在所述有源区上形成所述下多晶硅栅极电平的所述下多晶硅层的一部分的蚀刻掩模，去除所述第一掩模层，在所述下多晶硅栅极上形成所述上多晶硅栅极电平在去除第一掩模层之后，将掺杂剂引入上多晶硅栅极级，而不将掺杂剂引入衬底中，将掺杂剂从上多晶硅栅极级扩散到下多晶硅栅极电平，并在活性层中形成源极和漏极地区。有利地，下多晶硅栅极电平具有精确限定的长度以提供期望的沟道长度和良好控制的掺杂浓度以提供期望的阈值电压。

83. 发明授权

US5882973A Method for forming an integrated circuit having transistors of dissimilarly graded junction profiles 失效
标题翻译：用于形成具有不同分级结型材的晶体管的集成电路的方法
公开(公告)号：US5882973A
公开(公告)日：1999-03-16
申请号：US789549
申请日：1997-01-27
申请人： Mark I. Gardner , Fred N. Hause , H. Jim. Fulford, Jr.
发明人： Mark I. Gardner , Fred N. Hause , H. Jim. Fulford, Jr.
IPC分类号： H01L21/8234 , H01L21/8238 , H01L21/336
CPC分类号： H01L21/823468 , H01L21/823864
摘要： An integrated circuit is provided having a plurality of transistors either NMOS transistors, or PMOS transistors, or both NMOS and PMOS transistors. The transistors are formed having dissimilarly sized spacers. The spacers can be made larger in lateral areas on transistors designated as lower performing transistors than smaller spacers used on transistors which are higher performing. The dissimilarly sized spacers produce correspondingly sized lightly doped drain (LDD) areas. Accordingly, the present integrated circuit includes on a single monolithic substrate both high and low performance transistors based upon formation of dissimilarly sized spacers at sidewall surfaces of select transistor gate conductors.
摘要翻译：提供了具有多个晶体管的集成电路，NMOS晶体管或PMOS晶体管，或NMOS晶体管和PMOS晶体管。晶体管形成为具有不同尺寸的间隔物。在表现较高的晶体管上使用的间隔物可以比被称为低性能晶体管的晶体管的横向区域更大。不同尺寸的间隔件产生相应尺寸的轻掺杂漏极（LDD）区域。因此，本集成电路基于在选择晶体管栅极导体的侧壁表面处形成不同尺寸的间隔物，在单个单片基板上包括高性能和低性能晶体管。

84. 发明授权

US5882959A Multi-level transistor fabrication method having an inverted, upper level transistor which shares a gate conductor with a non-inverted, lower level transistor 失效
公开(公告)号：US5882959A
公开(公告)日：1999-03-16
申请号：US729810
申请日：1996-10-08
申请人： Daniel Kadosh , Mark I. Gardner
发明人： Daniel Kadosh , Mark I. Gardner
IPC分类号： H01L21/822 , H01L27/06 , H01L21/00
CPC分类号： H01L21/8221 , H01L27/0688 , Y10S257/905
摘要： A process is provided for producing active and passive devices on various levels of a semiconductor topography. As such, the present process can achieve device formation in three dimensions to enhance the overall density at which an integrated circuit is formed. The multi-level fabrication process not only adds to the overall circuit density but does so with emphasis placed on interconnection between devices on separate levels. Thus, high performance interconnect is introduced whereby the interconnect is made as short as possible between features within one transistor level to features within another transistor level. The interconnect achieves lower resistivity and capacitance by forming a single gate conductor which is shared by an upper level transistor and a lower level transistor. The shared gate conductor is interposed between a pair of gate dielectrics and each gate dielectric is configured between the single gate conductor and a respective substrate. Thus, the upper level transistor is inverted relative to the lower level transistor. The upper level transistor includes a substrate and junction region formed within and opening of an interlevel dielectric. The opening serves to receive the substrate material, but also to demarcate the formation of a pre-existing gate dielectric prior to substrate deposition. Sharing a single gate conductor among two transistors not only minimizes the overall routing between transistor inputs, but also is particularly attuned to inverter formation.

85. 发明授权

US5877050A Method of making N-channel and P-channel devices using two tube anneals and two rapid thermal anneals 失效
标题翻译：使用两个管退火和两个快速热退火来制造N沟道和P沟道器件的方法
公开(公告)号：US5877050A
公开(公告)日：1999-03-02
申请号：US711956
申请日：1996-09-03
申请人： Mark I. Gardner , Derick J. Wristers , H. Jim Fulford, Jr.
发明人： Mark I. Gardner , Derick J. Wristers , H. Jim Fulford, Jr.
IPC分类号： H01L21/8238
CPC分类号： H01L21/823814
摘要： A method of making N-channel and P-channel IGFETs is disclosed. The method includes, in sequence, the steps of partially doping a first source and a first drain in a first active region of a semiconductor substrate, applying a first tube anneal while a second active region of the semiconductor substrate is devoid of source/drain doping, partially doping a second source and a second drain in the second active region, applying a second tube anneal, fully doping the first source and the first drain, applying a first rapid thermal anneal, fully doping the second source and the second drain, and applying a second rapid thermal anneal. Advantageously, the first and second tube anneals provide control over the channel junction locations, and the first and second rapid thermal anneals provide rapid drive-in for subsequent source/drain doping spaced from the channel junctions.
摘要翻译：公开了制造N沟道和P沟道IGFET的方法。该方法依次包括在半导体衬底的第一有源区域中部分地掺杂第一源极和第一漏极的步骤，施加第一管退火，而半导体衬底的第二有源区域没有源极/漏极掺杂在第二有源区中部分地掺杂第二源极和第二漏极，施加第二管退火，完全掺杂第一源极和第一漏极，施加第一快速热退火，完全掺杂第二源极和第二漏极，以及应用第二快速热退火。有利地，第一和第二管退火提供对通道结位置的控制，并且第一和第二快速热退火为与通道结隔开的后续源极/漏极掺杂提供快速驱动。

86. 发明授权

US5869879A CMOS integrated circuit having a sacrificial metal spacer for producing graded NMOS source/drain junctions dissimilar from PMOS source/drain junctions 失效
公开(公告)号：US5869879A
公开(公告)日：1999-02-09
申请号：US761399
申请日：1996-12-06
申请人： H. Jim Fulford, Jr. , Mark I. Gardner , Derick J. Wristers
发明人： H. Jim Fulford, Jr. , Mark I. Gardner , Derick J. Wristers
IPC分类号： H01L21/8238 , H01L29/78 , H01L29/00
CPC分类号： H01L29/7833 , H01L21/823814 , Y10S257/90
摘要： An integrated circuit is formed whereby junction of NMOS transistors are formed dissimilar to junctions of PMOS transistors. The NMOS transistors include an LDD area, an MDD area and a heavy concentration source/drain area. Conversely, the PMOS transistor include an LDD area and a source/drain area. The NMOS transistor junction is formed dissimilar from the PMOS transistor junction to take into account the less mobile nature of the junction dopants relative to the PMOS dopants. Thus, a lessening of the LDD area and the inclusion of an MDD area provide lower source/drain resistance and higher ohmic connectivity in the NMOS device. The PMOS junction includes a relatively large LDD area so as to draw the highly mobile, heavy concentration boron atoms away from the PMOS channel.

87. 发明授权

US5866934A Parallel and series-coupled transistors having gate conductors formed on sidewall surfaces of a sacrificial structure 失效
公开(公告)号：US5866934A
公开(公告)日：1999-02-02
申请号：US879504
申请日：1997-06-20
申请人： Daniel Kadosh , Mark I. Gardner , Jon D. Cheek
发明人： Daniel Kadosh , Mark I. Gardner , Jon D. Cheek
IPC分类号： H01L21/28 , H01L21/336 , H01L21/8234 , H01L27/088 , H01L29/417 , H01L29/423 , H01L27/11
CPC分类号： H01L29/66659 , H01L21/28114 , H01L21/2815 , H01L21/823437 , H01L27/088 , H01L29/41775 , H01L29/42376 , Y10S257/904 , Y10S438/947
摘要： An improved series and/or parallel connection of transistors within a logic gate is presented. The improved connection is brought about by a sacrificial structure on which gate conductors are formed adjacent sidewall surfaces of the sacrificial structure. The sacrificial structure thereby provides spacing between the series-connected or parallel-connected transistors. Upon removal of each sacrificial structure, a pair of transistors can be formed by implanting dopant species into the substrate on opposite sides of the spaced conductors. Beneath what was once a sacrificial structure is a shared implant area to which two transistors are coupled either in series or in parallel. By depositing the gate conductor material and then anisotropically removing the material except adjacent the vertical sidewall surfaces, an ultra short gate conductor can be formed concurrent with other gate conductors within a logic gate.

88. 发明授权

US5854115A Formation of an etch stop layer within a transistor gate conductor to provide for reduction of channel length 失效
标题翻译：在晶体管栅极导体内形成蚀刻停止层以提供沟道长度的减小
公开(公告)号：US5854115A
公开(公告)日：1998-12-29
申请号：US979042
申请日：1997-11-26
申请人： Mark I. Gardner , Daniel Kadosh , Michael P. Duane
发明人： Mark I. Gardner , Daniel Kadosh , Michael P. Duane
IPC分类号： H01L21/28 , H01L21/336 , H01L21/8234 , H01L21/8238 , H01L29/51
CPC分类号： H01L29/518 , H01L21/28052 , H01L21/28176 , H01L21/823456 , H01L21/823828 , H01L21/82385 , H01L29/665 , H01L29/6659 , H01L29/66598 , Y10S438/97
摘要： A process is provided for forming a transistor gate conductor having an etch stop arranged at a depth below its upper surface such that the lateral width of the gate conductor above the etch stop may be exclusively narrowed to provide for reduction of transistor channel length. A masking layer, i.e., photoresist, patterned above the gate conductor is isotropically etched so as to minimize its lateral width prior to etching the gate conductor. Portions of the gate conductor not protected by the photoresist may be etched from above the etch stop to define a new pair of opposed sidewall surfaces for the upper portion of the gate conductor. The lateral width of the upper portion of the gate conductor thus may be reduced to a smaller dimension than that of conventional gate conductors. The gate conductor is subjected to an anisotropic etch in which portions of the gate conductor not protected by the narrowed photoresist are etched down to the etch stop. The presence of the etch stop ensures that substantial portions of the etch stop and underlying portions of the gate conductor are not removed before etching is completely terminated. As a result, a lower portion of the multi-layered gate conductor is wider than an upper portion of the gate conductor.
摘要翻译：提供了一种用于形成晶体管栅极导体的工艺，该晶体管栅极导体具有布置在其上表面下方的深度处的蚀刻停止，使得蚀刻停止点之上的栅极导体的横向宽度可以专门变窄以提供晶体管沟道长度的减小。在栅极导体上形成图案的掩模层，即光致抗蚀剂被各向同性蚀刻，以便在蚀刻栅极导体之前将其横向宽度最小化。未被光致抗蚀剂保护的栅极导体的部分可以从蚀刻停止点的上方蚀刻，以限定用于栅极导体的上部的新的一对相对的侧壁表面。因此，栅极导体的上部的横向宽度可以减小到比常规栅极导体更小的尺寸。对栅极导体进行各向异性蚀刻，其中不被变窄的光致抗蚀剂保护的栅极导体的部分被蚀刻到蚀刻停止点。蚀刻停止的存在确保蚀刻停止的大部分和栅极导体的下面的部分在蚀刻完全终止之前不被去除。结果，多层栅极导体的下部比栅极导体的上部宽。

89. 发明授权

US5851921A Semiconductor device and method for forming the device using a dual layer, self-aligned silicide to enhance contact performance 失效
标题翻译：用于使用双层自对准硅化物形成器件以提高接触性能的半导体器件和方法
公开(公告)号：US5851921A
公开(公告)日：1998-12-22
申请号：US832747
申请日：1997-04-04
申请人： Mark I. Gardner , Fred N. Hause
发明人： Mark I. Gardner , Fred N. Hause
IPC分类号： H01L21/336 , H01L21/44
CPC分类号： H01L29/665
摘要： An integrated circuit is formed by a process which can produce highly conductive contact structures. The contact structures result from a dual layer of titanium and cobalt reacted upon silicon-rich source/drain junctions and gate conductor upper surfaces. Reaction on the silicon-rich regions occur concurrent with one another using a self-aligned salicidation process, whereby the titanium layer can consume relatively large amounts of native oxide formed on the silicon-rich regions. In addition to interdiffusion of titanium, cobalt placed upon the titanium enhances the overall conductivity of the contact while providing some barrier properties against undue, additional interdiffusion of titanium and underlying silicon.
摘要翻译：通过可产生高导电性接触结构的工艺形成集成电路。接触结构是由在富含硅的源极/漏极结和栅极导体上表面上反应的钛和钴的双层产生的。在富含硅的区域上的反应使用自对准的盐析过程彼此并发，由此钛层可以消耗相对大量在富硅区域上形成的天然氧化物。除了钛的相互扩散之外，放置在钛上的钴增强了触点的整体电导率，同时提供了一些屏障性能，防止钛和下面的硅的不适当的额外相互扩散。

90. 发明授权

US5851883A High density integrated circuit process 失效
标题翻译：高密度集成电路工艺
公开(公告)号：US5851883A
公开(公告)日：1998-12-22
申请号：US844975
申请日：1997-04-23
申请人： Mark I. Gardner , Daniel Kadosh , Fred N. Hause
发明人： Mark I. Gardner , Daniel Kadosh , Fred N. Hause
IPC分类号： H01L21/8234
CPC分类号： H01L21/823437 , Y10S438/947
摘要： A semiconductor process in which a dielectric layer is formed on an upper surface of a semiconductor substrate which includes a silicon base layer. Thereafter, an upper silicon layer is formed on an upper surface of the dielectric layer. The dielectric layer and the upper silicon layer are then patterned to form first and second silicon-dielectric stacks on the upper surface of the base silicon layer. The first and second silicon-dielectric stacks are laterally displaced on either side of a channel region of the silicon substrate and each include a proximal sidewall and a distal sidewall. The proximal sidewalls are approximately coincident with respective boundaries of the channel region. Thereafter, proximal and distal spacer structures are formed on the proximal and distal sidewalls respectively of the first and second silicon-dielectric stacks. A gate dielectric layer is then formed on exposed portions of the silicon base layer over a channel region of the base silicon layer. Portions of the first and second silicon-dielectric stacks located over respective source/drain regions of the base silicon layer are then selectively removed. Silicon is then deposited to fill first and second voids created by the selected removal of the stacks. The silicon deposition also fills a silicon gate region above the gate dielectric over the channel region. Thereafter, an impurity distribution is introduced into the deposited silicon. The deposited silicon is then planarized to physically isolate the silicon within the gate region from the silicon within the first and second voids resulting in the formation of a transistor including a silicon gate structure and first and second source/drain structures.
摘要翻译：在包括硅基层的半导体衬底的上表面上形成介电层的半导体工艺。此后，在电介质层的上表面上形成上硅层。然后对电介质层和上硅层进行构图以在基底硅层的上表面上形成第一和第二硅 - 电介质叠层。第一和第二硅 - 电介质堆叠在硅衬底的沟道区域的任一侧上横向移位，并且每个包括近侧壁和远侧壁。近侧侧壁与通道区域的各个边界大致重合。此后，分别在第一和第二硅 - 电介质堆叠的近侧和远侧壁上形成近端和远端间隔结构。然后在硅基层的暴露部分上在基底硅层的沟道区上形成栅极电介质层。然后选择性地去除位于基底硅层的相应源极/漏极区域之上的第一和第二硅 - 电介质叠层的部分。然后沉积硅以填充由所选择的堆叠移除产生的第一和第二空隙。硅沉积还在沟道区域上填充栅极电介质上方的硅栅极区域。此后，将杂质分布引入沉积的硅中。沉积的硅然后被平坦化以物理地隔离第一和第二空隙内的栅极区域内的硅，从而形成包括硅栅极结构和第一和第二源极/漏极结构的晶体管。

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