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81. 发明授权

US06933189B2 Integration system via metal oxide conversion 失效
标题翻译：集成系统通过金属氧化物转换
公开(公告)号：US06933189B2
公开(公告)日：2005-08-23
申请号：US10870382
申请日：2004-06-16
申请人： Lawrence A. Clevenger , Louis L. Hsu , Carl J. Radens , Joseph F. Shepard, Jr.
发明人： Lawrence A. Clevenger , Louis L. Hsu , Carl J. Radens , Joseph F. Shepard, Jr.
IPC分类号： H01L21/285 , H01L21/30 , H01L21/306 , H01L21/3205 , H01L21/336 , H01L21/768 , H01L21/8232 , H01L21/8234 , H01L29/49 , H01L29/76 , H01L29/78 , H01L29/84 , H01L31/062 , H01L31/107 , H01L31/113 , H01L31/119
CPC分类号： H01L29/4983 , H01L21/28194 , H01L21/28518 , H01L21/28568 , H01L21/3003 , H01L21/76823 , H01L21/76895 , H01L29/517 , H01L29/7833
摘要： A method and structure for a transistor device comprises forming a source, drain, and trench region in a substrate, forming a first insulator over the substrate, forming a gate electrode above the first insulator, forming a pair of insulating spacers adjoining the electrode, converting a portion of the first insulator into a metallic film, converting the metallic film into one of a silicide and a salicide film, forming an interconnect region above the trench region, forming an etch stop layer above the first insulator, the trench region, the gate electrode, and the pair of insulating spacers, forming a second insulator above the etch stop layer, and forming contacts in the second insulator. The first insulator comprises a metal oxide material, which comprises one of a HfOx and a ZrOx.
摘要翻译：晶体管器件的方法和结构包括在衬底中形成源极，漏极和沟槽区域，在衬底上形成第一绝缘体，在第一绝缘体之上形成栅电极，形成邻接电极的一对绝缘衬垫，转换将所述第一绝缘体的一部分转变为金属膜，将所述金属膜转化成硅化物和自对隔硅膜之一，在所述沟槽区上方形成互连区，在所述第一绝缘体上方形成蚀刻停止层，所述沟槽区，所述栅电极和一对绝缘间隔物，在蚀刻停止层上方形成第二绝缘体，并在第二绝缘体中形成接触。第一绝缘体包括金属氧化物材料，其包括HfO x x和ZrO x x之一。

82. 发明授权

US06869895B1 Method for adjusting capacitance of an on-chip capacitor 失效
标题翻译：调整片上电容器电容的方法
公开(公告)号：US06869895B1
公开(公告)日：2005-03-22
申请号：US10674719
申请日：2003-09-30
申请人： Lawrence A. Clevenger , Timothy J. Dalton , Louis L. Hsu , Carl Radens , Keith Kwong Hon Wong , Chih-Chao Yang
发明人： Lawrence A. Clevenger , Timothy J. Dalton , Louis L. Hsu , Carl Radens , Keith Kwong Hon Wong , Chih-Chao Yang
IPC分类号： H01G4/255 , H01L21/02 , H01L21/66 , H01L21/31
CPC分类号： H01G4/255 , H01L22/22 , H01L28/40
摘要： A method and apparatus for adjusting capacitance of an on-chip capacitor uses exposure of a dielectric material of the capacitor to an ion beam comprising ions of at least one material to modify a dielectric constant of the dielectric material.
摘要翻译：用于调整片上电容器的电容的方法和装置使用将电容器的电介质材料暴露于包含至少一种材料的离子的离子束，以改变介电材料的介电常数。

83. 发明授权

US06775736B2 Embedded DRAM system having wide data bandwidth and data transfer data protocol 有权
标题翻译：具有宽数据带宽和数据传输数据协议的嵌入式DRAM系统
公开(公告)号：US06775736B2
公开(公告)日：2004-08-10
申请号：US10062812
申请日：2002-01-31
申请人： Louis L. Hsu , Rajiv J. Joshi , Jeremy K. Stephens , Daniel W. Storaska
发明人： Louis L. Hsu , Rajiv J. Joshi , Jeremy K. Stephens , Daniel W. Storaska
IPC分类号： G06F1200
CPC分类号： G11C7/1048 , G06F13/4243 , G11C5/063 , G11C11/4096 , G11C29/846 , G11C2207/104
摘要： A self-timed data communication system for a wide data width semiconductor memory system having a plurality of data paths. The data communication system includes a plurality of data banks configured for storing data, wherein a corresponding data bank of the plurality of data banks is connected to a respective one data path of the plurality of data paths. The data communication system further includes circuitry for controlling the respective one data path in accordance with receipt of a monitor signal indicating that a data transfer operation has been initiated for transfer of data to or from the respective one data path. The circuitry for controlling includes circuitry for generating a control signal for controlling resetting of the respective one data path after data is transferred for preparation of a subsequent data transfer operation.
摘要翻译：一种具有多个数据路径的宽数据宽度半导体存储器系统的自定时数据通信系统。数据通信系统包括被配置为存储数据的多个数据库，其中多个数据库中的相应数据库连接到多个数据路径中相应的一个数据路径。数据通信系统还包括用于根据接收到指示数据传送操作已被启动以用于将数据传送到相应的一个数据路径或从相应的一个数据路径传送数据的监视信号来控制相应的一个数据路径的电路。用于控制的电路包括用于产生控制信号的电路，该控制信号用于在传送数据以准备随后的数据传送操作之后控制相应的一个数据路径的复位。

84. 发明授权

US06683805B2 Suppression of leakage currents in VLSI logic and memory circuits 有权
标题翻译： VLSI逻辑和存储器电路中泄漏电流的抑制
公开(公告)号：US06683805B2
公开(公告)日：2004-01-27
申请号：US10067411
申请日：2002-02-05
申请人： Rajiv V. Joshi , Louis L. Hsu , Azeez J. Bhavnagarwala
发明人： Rajiv V. Joshi , Louis L. Hsu , Azeez J. Bhavnagarwala
IPC分类号： G11C11413
CPC分类号： G11C11/412
摘要： An SRAM system is provided having an array of SRAM cells including at least one circuit receiving a first power voltage and a power control circuit for supplying a second power voltage to at least one selected circuit of the at least one circuit. The system is one of a memory array and a logic system, and a circuit of the at least one circuit is one of a memory cell of the memory array, a sense amplifier of the memory array and a path of the logic system. A method is also provided for providing a power supply voltage to at least one circuit of a system.
摘要翻译：提供一种SRAM系统，其具有包括至少一个接收第一电源电压的电池的SRAM单元阵列和用于向至少一个电路的至少一个选定电路提供第二电源电压的功率控制电路。该系统是存储器阵列和逻辑系统之一，并且至少一个电路的电路是存储器阵列的存储单元，存储器阵列的读出放大器和逻辑系统的路径之一。还提供了一种用于向系统的至少一个电路提供电源电压的方法。

85. 发明授权

US06617702B2 Semiconductor device utilizing alignment marks for globally aligning the front and back sides of a semiconductor substrate 有权
标题翻译：半导体器件利用对准标记来全面对准半导体衬底的正面和背面
公开(公告)号：US06617702B2
公开(公告)日：2003-09-09
申请号：US09769080
申请日：2001-01-25
申请人： Louis L. Hsu , Rajiv V. Joshi , Carl Radens , Jack A. Mandelman , Tsorng-Dih Yuan
发明人： Louis L. Hsu , Rajiv V. Joshi , Carl Radens , Jack A. Mandelman , Tsorng-Dih Yuan
IPC分类号： H01L23544
CPC分类号： H01L23/48 , H01L21/8221 , H01L23/544 , H01L24/48 , H01L24/73 , H01L27/0694 , H01L2223/54473 , H01L2224/05599 , H01L2224/16225 , H01L2224/45099 , H01L2224/48091 , H01L2224/48227 , H01L2224/73257 , H01L2224/85399 , H01L2924/00014 , H01L2924/01039 , H01L2924/01077 , H01L2924/12041 , H01L2924/12042 , H01L2924/14 , Y10T29/49133 , Y10T29/49155 , H01L2924/00 , H01L2224/45015 , H01L2924/207
摘要： The present invention provides for globally aligning microelectronic circuit systems, such as communication devices and chips, fabricated on or bonded to the front and back sides of one or more substrates to provide for wireless communications between the circuit systems through the one or more substrates. In one embodiment, two circuit systems situated on opposite sides of a substrate are aligned to provide for wireless communications between the two circuit systems through the substrate. In another embodiment, communication devices situated on one or more substrates are aligned to provide for wireless communications between the communication devices through the one or more substrates. In another embodiment, two chips situated on opposite sides of a transparent substrate are aligned to provide for wireless communications between the two chips through the transparent substrate.
摘要翻译：本发明提供了在一个或多个基板的正面和背面上制造或结合到其上的微电子电路系统，例如通信设备和芯片，以提供通过一个或多个基板的电路系统之间的无线通信。在一个实施例中，位于衬底的相对侧上的两个电路系统被对准以提供通过衬底的两个电路系统之间的无线通信。在另一个实施例中，位于一个或多个基板上的通信设备被对准以通过一个或多个基板来提供通信设备之间的无线通信。在另一个实施例中，位于透明基板的相对侧上的两个芯片被对准以提供通过透明基板的两个芯片之间的无线通信。

86. 发明授权

US06410369B1 Soi-body selective link method and apparatus 失效
标题翻译：单体选择性联动方法及装置
公开(公告)号：US06410369B1
公开(公告)日：2002-06-25
申请号：US09591511
申请日：2000-06-12
申请人： Roy Childs Flaker , Louis L. Hsu , Fariborz Assaderaghi , Jack A. Mandelman
发明人： Roy Childs Flaker , Louis L. Hsu , Fariborz Assaderaghi , Jack A. Mandelman
IPC分类号： H01L2100
CPC分类号： H01L27/1104 , H01L27/1203
摘要： A silicon-on-insulator (SOI) structure and method of making the same includes an SOI wafer having a silicon layer of an original thickness dimension formed upon an isolation oxidation layer. At least two p-type bodies of at least two SOI field effect transistors (PFETs) are formed in the silicon layer. At least two n-type bodies of at least two SOI field effect transistors (NFETs) are also formed in the silicon layer. Lastly, an SOI body link is formed in the silicon layer of the SOI wafer adjacent the isolation oxidation layer for selectively connecting desired bodies of either the p-type SOI FETs or the n-type SOI FETs and for allowing the connected bodies to float.
摘要翻译：绝缘体上硅（SOI）结构及其制造方法包括具有形成在隔离氧化层上的原始厚度尺寸的硅层的SOI晶片。在硅层中形成至少两个至少两个SOI场效应晶体管（PFET）的p型体。在硅层中还形成至少两个至少两个SOI场效应晶体管（NFET）的n型体。最后，在隔离氧化层附近的SOI晶片的硅层中形成SOI本体连接，用于选择性地连接p型SOI FET或n型SOI FET的所需体，并允许连接体浮置。

87. 发明授权

US06255712B1 Semi-sacrificial diamond for air dielectric formation 有权
标题翻译：用于空气电介质形成的半牺牲金刚石
公开(公告)号：US06255712B1
公开(公告)日：2001-07-03
申请号：US09374839
申请日：1999-08-14
申请人： Lawrence A Clevenger , Louis L. Hsu
发明人： Lawrence A Clevenger , Louis L. Hsu
IPC分类号： H01L2900
CPC分类号： H01L23/4821 , H01L21/764 , H01L21/7682 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： Disclosed is a structure and process for incorporating air or other gas as a permanent dielectric medium in a multilevel chip by providing CVD diamond as a semi-sacrificial interlevel and intralevel dielectric material. The semi-sacrificial dielectric is subsequently at least partially removed in an isotopic oxygen etch. A variation of the disclosure includes providing a final, permanent CVD diamond encapsulant to contain the gaseous dielectric medium within the chip.
摘要翻译：公开了一种通过提供CVD金刚石作为半牺牲层间和体内电介质材料将空气或其它气体作为永久介电介质并入多层芯片的结构和方法。随后在同位素氧蚀刻中至少部分去除半牺牲电介质。本公开的变体包括提供最终的永久CVD金刚石密封剂以容纳芯片内的气态电介质。

88. 发明授权

US06228745B1 Selective reduction of sidewall slope on isolation edge 失效
标题翻译：隔离边缘侧壁倾斜的选择性减小
公开(公告)号：US06228745B1
公开(公告)日：2001-05-08
申请号：US09460134
申请日：1999-12-13
申请人： Donald C. Wheeler , Louis L. Hsu , Jack A. Mandelman , Rebecca D. Mih
发明人： Donald C. Wheeler , Louis L. Hsu , Jack A. Mandelman , Rebecca D. Mih
IPC分类号： H01L2176
CPC分类号： H01L21/76232 , Y10S438/947
摘要： Disclosed is a semiconductor structure which comprises a transistor having a source implantation and a drain implantation formed in a semiconductor substrate. The transistor further comprises a gate electrode, a gate oxide, and an active area. The source implantation and drain implantation are situated on opposite sides of said active area, and said gate oxide and gate electrode are situated on top of said active region. The transistor further comprises two trench isolations adjacent to said active area, wherein said trench isolations are situated on opposite sides of said active area such that a sidewall of each trench serves as interface to said active area, at least one of said sidewalls of said trench isolations which serves as interface to said active area being sloped having a slope between 90° and 150°, said trench isolations and source implantation and drain implantation enclosing said active area on four sides.
摘要翻译：公开了一种半导体结构，其包括在半导体衬底中形成的源极注入和漏极注入的晶体管。晶体管还包括栅电极，栅极氧化物和有源区。源极注入和漏极注入位于所述有源区的相对侧，并且所述栅极氧化物和栅电极位于所述有源区的顶部。晶体管还包括与所述有源区相邻的两个沟槽隔离，其中所述沟槽隔离位于所述有源区的相对侧，使得每个沟槽的侧壁用作与所述有源区的界面，所述沟槽的至少一个侧壁用作与所述有源区的界面的隔离具有倾斜的90°至150°之间的斜率，所述沟槽隔离和源极注入和漏极注入在四个侧面上包围所述有源区。

89. 发明授权

US06222244B1 Electrically blowable fuse with reduced cross-sectional area 失效
标题翻译：具有减小横截面积的可电熔保险丝
公开(公告)号：US06222244B1
公开(公告)日：2001-04-24
申请号：US09093903
申请日：1998-06-08
申请人： Kenneth C. Arndt , Dureseti Chidambarrao , Louis L. Hsu , Jack A. Mandelman , Carl Radens
发明人： Kenneth C. Arndt , Dureseti Chidambarrao , Louis L. Hsu , Jack A. Mandelman , Carl Radens
IPC分类号： H01L2900
CPC分类号： H01L23/62 , H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor fuse is positioned between conductors for connecting wiring lines. The fuse comprises spacers positioned on adjacent ones of the conductors, and a fuse element positioned between the spacers and connected to the wiring lines. A space between the conductors comprises a first width comprising a smallest possible photolithographic width and the fuse element has a second width smaller than the first width.
摘要翻译：半导体保险丝位于用于连接布线的导体之间。保险丝包括位于相邻导体上的间隔物，以及定位在间隔件之间并连接到布线的熔丝元件。导体之间的空间包括包含尽可能小的光刻宽度的第一宽度，并且熔丝元件具有小于第一宽度的第二宽度。

90. 发明授权

US06144054A DRAM cell having an annular signal transfer region 有权
标题翻译： DRAM单元具有环形信号传送区域
公开(公告)号：US06144054A
公开(公告)日：2000-11-07
申请号：US205934
申请日：1998-12-04
申请人： Farid Agahi , Louis L. Hsu , Jack A. Mandelman
发明人： Farid Agahi , Louis L. Hsu , Jack A. Mandelman
IPC分类号： H01L21/8242 , H01L27/108 , H01L29/76 , H01L29/94 , H01L31/119
CPC分类号： H01L27/10864 , H01L27/10841
摘要： A memory device formed in a substrate having a trench with side walls formed in the substrate. The device includes a bit line conductor and a word line conductor. A signal storage node has a first electrode, a second electrode formed within the trench, and a node dielectric formed between the first and second electrodes. A signal transfer device has: (i) an annular signal transfer region with an outer surface adjacent the side walls of the trench, an inner surface, a first end, and a second end; (ii) a first diffusion region coupling the first end of the signal transfer region to the. second electrode of the signal storage node; (iii) a second diffusion region coupling the second end of the signal transfer region to the bit line conductor; (iv) a gate insulator coating the inner surface of the signal transfer region; and (v) a gate conductor coating the gate insulator and coupled to the word line. A conductive connecting member couples the signal transfer region to a reference voltage to reduce floating body effects.
摘要翻译：一种存储器件，形成在具有形成在衬底中的侧壁的沟槽的衬底中。该器件包括位线导体和字线导体。信号存储节点具有形成在沟槽内的第一电极，第二电极和形成在第一和第二电极之间的节点电介质。信号传递装置具有：（i）环形信号传递区域，其外表面邻近沟槽的侧壁，内表面，第一端和第二端; （ii）将信号传送区域的第一端耦合到第一扩散区域。信号存储节点的第二电极; （iii）将信号传输区域的第二端耦合到位线导体的第二扩散区域; （iv）涂覆信号传送区域的内表面的栅极绝缘体; 和（v）涂覆栅极绝缘体并耦合到字线的栅极导体。导电连接构件将信号传递区域耦合到参考电压以减少浮体效应。

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