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81. 发明申请

US20090058457A1 REDUNDANT CRITICAL PATH CIRCUITS TO MEET PERFORMANCE REQUIREMENT 失效
标题翻译：冗余关键路径满足性能要求
公开(公告)号：US20090058457A1
公开(公告)日：2009-03-05
申请号：US11848278
申请日：2007-08-31
申请人： Kenneth J. Goodnow , Stephen G. Shuma , Peter A. Twombly
发明人： Kenneth J. Goodnow , Stephen G. Shuma , Peter A. Twombly
IPC分类号： H03K19/003 , G06F17/50 , H01L21/66
CPC分类号： G06F17/505
摘要： Method, system, IC and design structure for meeting a performance requirement using redundant critical path circuits, are disclosed. In one embodiment, the IC includes a plurality of redundant critical path circuits, wherein at least one of the plurality of redundant critical path circuits meeting a performance requirement is operational and the others are non-operational.
摘要翻译：公开了使用冗余关键路径电路满足性能要求的方法，系统，IC和设计结构。在一个实施例中，IC包括多个冗余关键路径电路，其中满足性能要求的多个冗余关键路径电路中的至少一个是可操作的，而其他冗余关键路径电路是不可操作的。

82. 发明申请

US20090044054A1 DYNAMIC CRITICAL PATH DETECTOR FOR DIGITAL LOGIC CIRCUIT PATHS 有权
标题翻译： DIGITAL LOGIC CIRCUIT PATHS的动态关键路径探测器
公开(公告)号：US20090044054A1
公开(公告)日：2009-02-12
申请号：US11834110
申请日：2007-08-06
申请人： Serafino Bueti , Kenneth J. Goodnow , Todd E. Leonard , Gregory J. Mann , Peter A. Sandon , Peter A. Twombly , Charles S. Woodruff
发明人： Serafino Bueti , Kenneth J. Goodnow , Todd E. Leonard , Gregory J. Mann , Peter A. Sandon , Peter A. Twombly , Charles S. Woodruff
IPC分类号： G01R31/28
CPC分类号： G06F17/5031 , G01R31/3187 , G06F11/1608 , G06F11/1695 , G06F2217/84
摘要： Method for correcting timing failures in an integrated circuit and device for monitoring an integrated circuit. The method includes placing a first and second latch near a critical path. The first latch has an input comprising a data value on the critical path. The method further includes generating a delayed data value from the data value, latching the delayed data value in the second latch, comparing the data value with the delayed data value to determine whether the critical path comprises a timing failure condition, and executing a predetermined corrective measure for the critical path.
摘要翻译：用于校正集成电路中的定时故障的方法和用于监视集成电路的装置。该方法包括将第一和第二闩锁放置在关键路径附近。第一锁存器具有包括关键路径上的数据值的输入。该方法还包括从数据值产生延迟的数据值，将延迟的数据值锁存在第二锁存器中，将数据值与延迟的数据值进行比较，以确定关键路径是否包括定时失败状态，以及执行预定的校正衡量关键路径。

83. 发明申请

US20080215945A1 System and method for system-on-chip interconnect verification 有权
标题翻译：系统级芯片互连验证的系统和方法
公开(公告)号：US20080215945A1
公开(公告)日：2008-09-04
申请号：US11819748
申请日：2007-06-28
申请人： Serafino Bueti , Adam Courchesne , Kenneth J. Goodnow , Gregory J. Mann , Jason M. Norman , Stanley B. Stanski , Scott T. Vento
发明人： Serafino Bueti , Adam Courchesne , Kenneth J. Goodnow , Gregory J. Mann , Jason M. Norman , Stanley B. Stanski , Scott T. Vento
IPC分类号： G01R31/3177 , G06F13/00 , G06F11/25
CPC分类号： G06F11/261 , G01R31/31717 , G01R31/318513 , G06F11/2236 , G06F17/5022
摘要： A system and method for verifying system-on-chip interconnect includes a first linear feedback shift register coupled to an output interface of a first system-on-chip component, a second linear feedback shift register instantiated in a second system-on-chip component, and a comparator coupled to the second linear feedback shift register and the input interface of the second system-on-chip. Another method for verifying includes generating a pseudo-random number sequence with the first linear feedback shift register and the second linear feedback shift register using an identical first initial state, and comparing an output of the first linear feedback shift register with an output of the second linear feedback shift register and reporting a miss-compare.
摘要翻译：一种用于验证片上系统互连的系统和方法包括：第一线性反馈移位寄存器，其耦合到第一片上系统分量的输出接口;第二线性反馈移位寄存器，其在第二片上系统组件以及耦合到第二线性反馈移位寄存器和第二片上系统的输入接口的比较器。另一种验证方法包括使用第一线性反馈移位寄存器和第二线性反馈移位寄存器使用相同的第一初始状态来产生伪随机数序列，并且将第一线性反馈移位寄存器的输出与第二线性反馈移位寄存器的输出进行比较线性反馈移位寄存器和报告错误比较。

84. 发明申请

US20080127216A1 TASK BASED DEBUGGER (TRANSACATION-EVENT-JOB-TRIGGER) 失效
标题翻译：基于任务调度器（交易活动 - 工作触发器）
公开(公告)号：US20080127216A1
公开(公告)日：2008-05-29
申请号：US11461793
申请日：2006-08-02
申请人： Serafino Bueti , Kenneth J. Goodnow , Todd E. Leonard , Grogory J. Mann , Charles S. Woodruff
发明人： Serafino Bueti , Kenneth J. Goodnow , Todd E. Leonard , Grogory J. Mann , Charles S. Woodruff
IPC分类号： G06F3/00
CPC分类号： G06F17/5022 , G06F15/7842 , G06F2217/14
摘要： The embodiments of the invention provide an apparatus, method, etc. for a task based debugger (transaction-event-job-trigger). More specifically, an integrated event monitor for a SOC comprises functional cores each having a functional debug logic element. The cores are connected to an interconnect structure that links the functional debug logic elements. Each functional debug logic element is specifically dedicated to a function of its corresponding core, wherein the functional debug logic elements generate a table of function-specific system events. The system events are function-specific with respect to an associated core, wherein the system events include transaction events, controller events, processor events, interconnect structure arbiter events, interconnect interface core events, high speed serial link core events, and/or codec events.
摘要翻译：本发明的实施例提供了一种用于基于任务的调试器（事务 - 事件 - 作业触发）的装置，方法等。更具体地，SOC的集成事件监视器包括各自具有功能调试逻辑元件的功能核心。核心连接到链接功能调试逻辑元件的互连结构。每个功能调试逻辑元件专门用于其相应核心的功能，其中功能调试逻辑元件产生功能特定系统事件表。系统事件相对于相关联的核心是特定于功能的，其中系统事件包括交易事件，控制器事件，处理器事件，互连结构仲裁器事件，互连接口核心事件，高速串行链路核心事件和/或编解码器事件。

85. 发明授权

US07308668B2 Apparatus and method for implementing an integrated circuit IP core library architecture 有权
标题翻译：用于实现集成电路IP核心库架构的装置和方法
公开(公告)号：US07308668B2
公开(公告)日：2007-12-11
申请号：US11160609
申请日：2005-06-30
申请人： Serafino Bueti , Adam J. Courchesne , Kenneth J. Goodnow , Gregory J. Mann , Stanley B. Stanski
发明人： Serafino Bueti , Adam J. Courchesne , Kenneth J. Goodnow , Gregory J. Mann , Stanley B. Stanski
IPC分类号： G06F17/50 , G06F9/45
CPC分类号： G06F17/5045
摘要： An integrated circuit (IC) architecture includes a library of intellectual property (IP) cores configured to provide a plurality of individual circuit functions. The IP cores arranged in a manner compatible with a customized, functional selection of individual ones of the IP cores, wherein individually selected cores are accessible through a communication structure included within the library.
摘要翻译：集成电路（IC）架构包括被配置为提供多个单独电路功能的知识产权（IP）核心库。所述IP核以与所述IP核中的各个IP核的定制功能选择相兼容的方式布置，其中通过包括在所述库内的通信结构来访问单独选择的核。

86. 发明授权

US07302605B2 Method and structure for replacing faulty operating code contained in a ROM for a processor 有权
标题翻译：用于替换处理器的ROM中包含的错误操作代码的方法和结构
公开(公告)号：US07302605B2
公开(公告)日：2007-11-27
申请号：US10692193
申请日：2003-10-23
申请人： Kenneth J. Goodnow
发明人： Kenneth J. Goodnow
IPC分类号： G06F11/00
CPC分类号： G06F9/268 , G06F8/66 , G06F9/328 , G06F12/0638
摘要： The invention provides replacement operation code for specific defective lines of operation code contained in a ROM often on an ASIC chip which code is used in a processor. ROM memory constitutes the best use of chip space and is the most economical to manufacture of all of the various options. ROM memory is not changeable after it is set in ROM and, hence, if there is any change in the code (hereinafter sometimes faulty code) required after the code has been incorporated in the ROM memory, such change cannot be made in the ROM itself without replacing the entire ROM. The present invention allows change in any specific lines of faulty contained in ROM without replacing the entire ROM, and provides for changing only the faulty lines of code. It also allows the new code to have the same, more, or fewer lines than the faulty code.
摘要翻译：本发明通常在ASIC芯片上经常包含在ROM中的特定的有缺陷的操作代码行的替代操作代码，该代码用于处理器。 ROM存储器构成了芯片空间的最佳使用，并且是制造所有各种选项最经济的。 ROM存储器在ROM中被设置之后不可改变，因此，如果代码已被并入ROM存储器中之后所需的代码（以下有时是有缺陷的代码）有任何变化，则不能在ROM本身中进行这种改变而不用替换整个ROM。本发明允许在ROM中包含的任何特定的故障线路中的更改，而不需要更换整个ROM，并且仅提供错误的代码行。它还允许新代码与故障代码具有相同，多或少的行。

87. 发明授权

US06802033B1 Low-power critical error rate communications controller 失效
标题翻译：低功率关键错误率通信控制器
公开(公告)号：US06802033B1
公开(公告)日：2004-10-05
申请号：US09286855
申请日：1999-04-06
申请人： Claude L. Bertin , Alvar A. Dean , Kenneth J. Goodnow , Scott W. Gould , Patrick E. Perry , Wilbur D. Pricer , William R. Tonti
发明人： Claude L. Bertin , Alvar A. Dean , Kenneth J. Goodnow , Scott W. Gould , Patrick E. Perry , Wilbur D. Pricer , William R. Tonti
IPC分类号： G06F1100
CPC分类号： G06F11/10 , H04L1/0053
摘要： A way of dynamically modifying error recovery on a communications controller to operate at the lowest power mode allowed by current error rate conditions. When operating conditions are good and a small number of errors are detected, a low power error detection/correction mode is entered saving battery life. The low power error correction mechanism runs at a slower frequency and lower power than the high power mechanism and maintains the same data rate for the controller, thus saving power. Selecting the controller error (power) mode may be externally, such as by a person using a control dial on a cellular telephone when the voice data gets too noisy. Alternatively, the selection can be automatic, a critical error level detector internally making the selection.
摘要翻译：一种在通信控制器上动态修改错误恢复的方式，以在当前错误率条件允许的最低功耗模式下工作。当操作条件良好并且检测到少量错误时，输入低功率错误检测/校正模式，从而节省电池寿命。低功率误差校正机构运行频率较低，功率低于大功率机构，并为控制器保持相同的数据速率，从而节省功耗。选择控制器错误（电源）模式可以是外部的，例如当语音数据太嘈杂时，人们在蜂窝电话上使用控制拨盘。或者，选择可以是自动的，在内部进行选择的关键误差电平检测器。

88. 发明授权

US06532520B1 Method and apparatus for allocating data and instructions within a shared cache 失效
标题翻译：用于在共享缓存内分配数据和指令的方法和装置
公开(公告)号：US06532520B1
公开(公告)日：2003-03-11
申请号：US09394965
申请日：1999-09-10
申请人： Alvar A. Dean , Marc R. Faucher , John W. Goetz , Kenneth J. Goodnow , Paul T. Gutwin , Stephen W. Mahin , Wilbur D. Pricer
发明人： Alvar A. Dean , Marc R. Faucher , John W. Goetz , Kenneth J. Goodnow , Paul T. Gutwin , Stephen W. Mahin , Wilbur D. Pricer
IPC分类号： G06F1200
CPC分类号： G06F12/121 , G06F12/127 , G06F2212/1021 , G06F2212/6042
摘要： A method and apparatus are provided for managing cache allocation for a plurality of data types in a unified cache having dynamically allocable lines for first type data and for second type data. Cache allocation is managed by counting misses to first type data and misses to second type data in the unified cache, and by determining when a difference between a number of first type data misses and a number of second type data misses crosses a preselected threshold. A replacement algorithm of the unified cache then is adjusted in response to the detected crossing of the preselected threshold, the adjusting step including increasing a replacement priority of the first type data lines in the cache. The replacement algorithm preferably is an LRU algorithm wherein the adjusting step includes incrementing an age indication of the first type data lines. Hardware for implementing the inventive cache allocation management method comprises a miss counter configured to increment its count in response to a miss to first type data signal on a first counter input and to output a first logic state on a first counter output when the counter's count exceeds a first predetermined count. A priority adjustment circuit coupled to the first counter output increases the replacement priority of the first type data relative to the replacement priority of the second type data in response to the first logic state output by the miss counter.
摘要翻译：提供了一种方法和装置，用于管理具有用于第一类型数据和第二类型数据的动态可分配行的统一高速缓存中的多个数据类型的高速缓存分配。高速缓存分配通过对统一高速缓存中的第一类型数据和第二类型数据的丢失进行计数，并且通过确定多个第一类型数据丢失与多个第二类型数据丢失之间的差异何时穿过预选阈值来管理高速缓存分配。然后，响应于检测到的预选阈值的交叉，调整统一高速缓存的替换算法，该调整步骤包括增加高速缓存中的第一类型数据线的替换优先级。替换算法优选地是LRU算法，其中调整步骤包括递增第一类型数据线的年龄指示。用于实现本发明的高速缓存分配管理方法的硬件包括错误计数器，其配置为响应于第一计数器输入上的第一类型数据信号的未命中而增加其计数，并且当计数器的计数超过时，在第一计数器输出上输出第一逻辑状态第一预定计数。耦合到第一计数器输出的优先级调整电路响应于未命中计数器输出的第一逻辑状态，增加第一类型数据相对于第二类型数据的替换优先级的替换优先级。

89. 发明授权

US08549335B2 Secondary power utilization during peak power times 有权
标题翻译：峰值功率时间的次要功率利用率
公开(公告)号：US08549335B2
公开(公告)日：2013-10-01
申请号：US13593837
申请日：2012-08-24
申请人： Kenneth J. Goodnow , Stephen G. Shuma , Peter A. Twombly
发明人： Kenneth J. Goodnow , Stephen G. Shuma , Peter A. Twombly
IPC分类号： G06F1/26 , G06F1/32
CPC分类号： G06F1/263
摘要： Systems and methods for selectively utilizing secondary power sources during peak power times are provided for. The method includes receiving a notification of a peak power time, and discontinuing use of a primary power supply and beginning use of a secondary power supply based upon the notification.
摘要翻译：提供了用于在峰值功率时间期间选择性地利用次级电源的系统和方法。该方法包括接收峰值功率时间的通知，以及停止使用主电源并基于该通知开始使用次级电源。

90. 发明授权

US08436638B2 Switch to perform non-destructive and secure disablement of IC functionality utilizing MEMS and method thereof 有权
标题翻译：切换使用MEMS及其方法执行IC功能的无损和安全的禁用
公开(公告)号：US08436638B2
公开(公告)日：2013-05-07
申请号：US12964764
申请日：2010-12-10
申请人： Jonathan Ebbers , Kenneth J. Goodnow , Stephen G. Shuma , Peter A. Twombly
发明人： Jonathan Ebbers , Kenneth J. Goodnow , Stephen G. Shuma , Peter A. Twombly
IPC分类号： H03K19/00
CPC分类号： G06F21/87
摘要： Structures and methods are provided for performing non-destructive and secure disablement of integrated circuit (IC) functionality. A structure for enabling non-destructive and secure disablement and re-enablement of the IC includes a micro-electrical mechanical structure (MEMS) initially set to a chip enable state. The structure also includes an activation circuit operable to set the MEMS device to an error state based on a detected predetermined condition of the IC. The IC is disabled when the MEMS device is in the error state.
摘要翻译：提供了用于执行集成电路（IC）功能的非破坏性和安全性的禁用的结构和方法。用于实现IC的非破坏性和安全的禁用和重新启用的结构包括初始设置为芯片使能状态的微电机械结构（MEMS）。该结构还包括激活电路，其可操作以基于检测到的IC的预定条件将MEMS器件设置为错误状态。当MEMS器件处于错误状态时，IC被禁止。

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