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81. 发明授权

US08530319B2 Vertical silicide e-fuse 有权
标题翻译：垂直硅化物电熔丝
公开(公告)号：US08530319B2
公开(公告)日：2013-09-10
申请号：US12904435
申请日：2010-10-14
申请人： Ephrem G. Gebreselasie , Joseph M. Lukaitis , Robert R. Robison , William R. Tonti , Ping-Chuan Wang
发明人： Ephrem G. Gebreselasie , Joseph M. Lukaitis , Robert R. Robison , William R. Tonti , Ping-Chuan Wang
IPC分类号： H01L21/20 , H01L21/44
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： An apparatus and a method of manufacturing an e-fuse includes a substrate, a patterned gate insulator on the substrate, and a patterned gate conductor on the patterned gate insulator. The patterned gate conductor has sidewalls and a top. A silicide contacts the sidewalls of the patterned gate conductor, the top of the patterned gate conductor, and a region of the substrate adjacent the patterned gate insulator and the patterned gate conductor.
摘要翻译：一种制造电熔丝的装置和方法包括：衬底，衬底上的图案化栅极绝缘体，以及图案化栅极绝缘体上的图案化栅极导体。图案化的栅极导体具有侧壁和顶部。硅化物接触图案化栅极导体的侧壁，图案化栅极导体的顶部以及与图案化栅极绝缘体和图案化栅极导体相邻的衬底的区域。

82. 发明申请

US20130222013A1 PHYSICAL UNCLONABLE FUNCTION CELL AND ARRAY 失效
标题翻译：物理不可靠功能单元和阵列
公开(公告)号：US20130222013A1
公开(公告)日：2013-08-29
申请号：US13403339
申请日：2012-02-23
申请人： Kai D. Feng , Hailing Wang , Ping-Chuan Wang , Zhijian Yang
发明人： Kai D. Feng , Hailing Wang , Ping-Chuan Wang , Zhijian Yang
IPC分类号： H03D13/00
CPC分类号： H03K5/156 , H03K5/1534
摘要： A function cell comprising a first field effect transistor (FET) device, a second FET device, a first node connected to a gate terminal of the first FET device and a gate terminal of the second FET device, wherein the first node is operative to receive a voltage signal from an alternating current (AC) voltage source, an amplifier portion connected to the first FET device and the second FET device, the amplifier portion operative to receive a signal from the first FET device and the second FET device, a phase comparator portion having a first input terminal connected to an output terminal of the amplifier and a second input terminal operative to receive the voltage signal from the AC voltage source, the phase comparator portion operative to output a voltage indicative of a bit of a binary value.
摘要翻译：一种功能单元，包括第一场效应晶体管（FET）器件，第二FET器件，连接到第一FET器件的栅极端子的第一节点和第二FET器件的栅极端子，其中第一节点可操作以接收来自交流（AC）电压源的电压信号，连接到第一FET器件和第二FET器件的放大器部分，用于接收来自第一FET器件和第二FET器件的信号的放大器部分，相位比较器部分具有连接到放大器的输出端子的第一输入端子和用于从AC电压源接收电压信号的第二输入端子，该相位比较器部分用于输出指示二进制值的位的电压。

83. 发明授权

US08422322B2 Self-repair integrated circuit and repair method 失效
标题翻译：自修复集电路及维修方法
公开(公告)号：US08422322B2
公开(公告)日：2013-04-16
申请号：US13288472
申请日：2011-11-03
申请人： Louis L. C. Hsu , Rajiv V. Joshi , Zhijian J. Yang , Ping-Chuan Wang
发明人： Louis L. C. Hsu , Rajiv V. Joshi , Zhijian J. Yang , Ping-Chuan Wang
IPC分类号： G11C7/00
CPC分类号： G11C29/04 , G11C7/12 , G11C11/412
摘要： A method for repairing degraded field effect transistors includes forward biasing PN junctions of one of a source and a drain of a field effect transistor (FET), and a body of the FET. Charge is injected from a substrate to a gate region to neutralize charge in the gate region. The method is applicable to CMOS devices. Repair circuits are disclosed for implementing the repairs.
摘要翻译：用于修复劣化场效应晶体管的方法包括场效应晶体管（FET）的源极和漏极之一的正偏置PN结以及FET的主体。电荷从衬底注入到栅极区域以中和栅极区域中的电荷。该方法适用于CMOS器件。公开了用于实施修理的维修电路。

84. 发明申请

US20130027051A1 NONCONTACT ELECTRICAL TESTING WITH OPTICAL TECHNIQUES 失效
标题翻译：非接触式电气测试与光学技术
公开(公告)号：US20130027051A1
公开(公告)日：2013-01-31
申请号：US13191555
申请日：2011-07-27
申请人： Xu Ouyang , Tso-Hui Ting , Ping-Chuan Wang , Yongchun Xin
发明人： Xu Ouyang , Tso-Hui Ting , Ping-Chuan Wang , Yongchun Xin
IPC分类号： G01R31/3187
CPC分类号： G01R31/31728
摘要： An on-chip technique for noncontact electrical testing of a test structure on a chip is provided. On-chip photodiodes receives pump light from a pump light source, where the on-chip photodiodes are electrically connected to the test structure and are configured to generate power for the test structure. An on-chip coupling unit receives probe light from a probe light source, where the on-chip coupling unit is optically connected to on-chip waveguides through which the probe light is transferred. On-chip switches open in response to receiving voltage output from the test structure, and the on-chip switches remain closed when the voltage output is not received from the test structure. The on-chip switches pass the probe light when opened by the voltage output from the test structure. The on-chip switches block the probe light by remaining closed, when the voltage output is not received from the test structure.
摘要翻译：提供了芯片上测试结构的非接触电测试的片上技术。片上光电二极管从泵浦光源接收泵浦光，其中片上光电二极管电连接到测试结构，并且被配置为产生用于测试结构的电力。片上耦合单元接收来自探针光源的探测光，其中片上耦合单元光学连接到传输探针光的片上波导。响应于测试结构的接收电压输出，片内开关打开，并且当没有从测试结构接收到电压输出时，片上开关保持闭合。当由测试结构输出的电压打开时，片上开关通过探测灯。当没有从测试结构接收到电压输出时，片内开关通过保持关闭来阻止探测光。

85. 发明申请

US20120241977A1 CONFIGURABLE INTERPOSER 有权
标题翻译：配置插座
公开(公告)号：US20120241977A1
公开(公告)日：2012-09-27
申请号：US13489596
申请日：2012-06-06
申请人： Oleg Gluschenkov , Yunsheng Song , Tso-Hui Ting , Ping-Chuan Wang
发明人： Oleg Gluschenkov , Yunsheng Song , Tso-Hui Ting , Ping-Chuan Wang
IPC分类号： H01L25/00 , H01L21/66 , H05K13/00 , H01L21/60
CPC分类号： H01L23/49827 , H01L21/486 , H01L22/20 , H01L23/13 , H01L23/481 , H01L24/16 , H01L24/17 , H01L25/0657 , H01L2224/0401 , H01L2224/0603 , H01L2224/1403 , H01L2225/06517 , H01L2225/06541 , H01L2225/06572 , H01L2225/06596 , H01L2924/014 , H01L2924/1301 , H01L2924/1305 , H01L2924/15311 , H05K1/0286 , H05K1/142 , H05K2201/2018 , H05K2203/1572 , Y10T29/49117 , H01L2924/00
摘要： A modularized interposer includes a plurality of interposer units that are assembled to provide a complete set of electrical connections between two semiconductor chips. At least some of the plurality of interposer units can be replaced with other interposer units having an alternate configuration to enable selection of different functional parts of semiconductor chips to be connected through the modularized interposer. Bonding structures, connected to conductive metal pads located at peripheries of neighboring interposer units and an overlying or underlying portion of a semiconductor chip, can provide electrical connections between the neighboring interposer units. The interposer units can be provided by forming through-substrate vias (TSV's) in a substrate, forming patterned conductive structures on the substrate, and cutting the substrate into interposers.
摘要翻译：模块化插入器包括多个插入器单元，其被组合以提供两个半导体芯片之间的完整的电连接。多个插入单元中的至少一些可以被具有替代配置的其它插入单元替代，以便能够通过模块化插入器选择要连接的半导体芯片的不同功能部件。连接到位于相邻插入单元周围的导电金属焊盘和半导体芯片的上部或下部的结合结构可以在相邻插入单元之间提供电连接。可以通过在衬底中形成贯穿衬底通孔（TSV）来形成插入器单元，在衬底上形成图案化的导电结构，并将衬底切割成插入层。

86. 发明授权

US08232115B2 Test structure for determination of TSV depth 有权
标题翻译：用于测定TSV深度的测试结构
公开(公告)号：US08232115B2
公开(公告)日：2012-07-31
申请号：US12566726
申请日：2009-09-25
申请人： Hanyi Ding , Kai D. Feng , Ping-Chuan Wang , Zhijian Yang
发明人： Hanyi Ding , Kai D. Feng , Ping-Chuan Wang , Zhijian Yang
IPC分类号： H01L21/66
CPC分类号： H01L22/34 , H01L21/76898
摘要： A test structure for a through-silicon-via (TSV) in a semiconductor chip includes a first contact, the first contact being electrically connected to a first TSV; and a second contact, wherein the first contact, second contact, and the first TSV form a first channel, and a depth of the first TSV is determined based on a resistance of the first channel. A method of determining a depth of a through-silicon-via (TSV) in a semiconductor chip includes etching a first TSV into the semiconductor chip; forming a first channel, the first channel comprising the first TSV, a first contact electrically connected to the first TSV, and a second contact; connecting a current source to the second contact; determining a resistance across the first channel; and determining a depth of the first TSV based on the resistance of the first channel.
摘要翻译：半导体芯片中的贯穿硅通孔（TSV）的测试结构包括：第一触点，第一触点电连接到第一TSV; 以及第二触点，其中所述第一触点，所述第二触点和所述第一TSV形成第一通道，并且基于所述第一通道的电阻来确定所述第一TSV的深度。确定半导体芯片中的硅通孔（TSV）的深度的方法包括将第一TSV蚀刻到半导体芯片中; 形成第一通道，所述第一通道包括所述第一TSV，电连接到所述第一TSV的第一触点和第二触点; 将电流源连接到第二触点; 确定跨越第一通道的电阻; 以及基于所述第一通道的电阻确定所述第一TSV的深度。

87. 发明授权

US08211756B2 3D chip-stack with fuse-type through silicon via 有权
标题翻译：具有熔断器型硅通孔的3D芯片堆叠
公开(公告)号：US08211756B2
公开(公告)日：2012-07-03
申请号：US12822459
申请日：2010-06-24
申请人： Kai Di Feng , Louis Lu-Chen Hsu , Ping-Chuan Wang , Zhijian Yang
发明人： Kai Di Feng , Louis Lu-Chen Hsu , Ping-Chuan Wang , Zhijian Yang
IPC分类号： H01L21/82
CPC分类号： H01L21/76898 , H01L23/481 , H01L23/5256 , H01L25/0657 , H01L2224/05001 , H01L2224/05009 , H01L2224/05124 , H01L2224/05147 , H01L2224/05184 , H01L2224/0557 , H01L2224/05571 , H01L2224/05624 , H01L2224/05647 , H01L2224/05684 , H01L2224/16 , H01L2225/06513 , H01L2225/06527 , H01L2225/06541 , H01L2924/3011 , H01L2924/00014
摘要： Programmable fuse-type through silicon vias (TSVs) in silicon chips are provided with non-programmable TSVs in the same chip. The programmable fuse-type TSVs may employ a region within the TSV structure having sidewall spacers that restrict the cross-sectional conductive path of the TSV adjacent a chip surface contact pad. Application of sufficient current by programming circuitry causes electromigration of metal to create a void in the contact pad and, thus, an open circuit. Programming may be carried out by complementary circuitry on two adjacent chips in a multi-story chip stack.
摘要翻译：硅芯片中的可编程熔丝式硅通孔（TSV）在同一芯片中提供非可编程TSV。可编程保险丝型TSV可以采用TSV结构内的区域，其具有侧壁间隔件，其限制邻近芯片表面接触焊盘的TSV的横截面导电路径。通过编程电路施加足够的电流导致金属的电迁移，从而在接触焊盘中产生空隙，并因此产生开路。编程可以由多层芯片堆叠中的两个相邻芯片上的互补电路来执行。

88. 发明申请

US20120100712A1 STRUCTURE OF POWER GRID FOR SEMICONDUCTOR DEVICES AND METHOD OF MAKING THE SAME 失效
标题翻译：半导体器件的电源结构及其制造方法
公开(公告)号：US20120100712A1
公开(公告)日：2012-04-26
申请号：US13342221
申请日：2012-01-03
申请人： Ronald Filippi , Wai-kin Li , Ping-Chuan Wang
发明人： Ronald Filippi , Wai-kin Li , Ping-Chuan Wang
IPC分类号： H01L21/76
CPC分类号： H01L23/5226 , H01L21/76802 , H01L21/76847 , H01L21/76852 , H01L23/5286 , H01L23/53223 , H01L23/53238 , H01L23/53252 , H01L23/53266 , H01L2924/0002 , H01L2924/00
摘要： An embodiment of the invention provides a semiconductor structure, which may include a stud of a first conductive material formed inside a dielectric layer; a via of a second conductive material having a bottom and sidewalls with the bottom and the sidewalls being covered by a conductive liner, and the bottom being formed directly on top of the stud and being in contact with the via through the conductive liner; and one or more conductive paths of a third conductive material connecting to the via through the conductive liner at the sidewalls of said the. A method of making the semiconductor structure is also provided.
摘要翻译：本发明的一个实施例提供一种半导体结构，其可以包括形成在电介质层内部的第一导电材料的支柱; 具有底部的第二导电材料的通孔和具有底部的侧壁，并且侧壁被导电衬垫覆盖，并且底部直接形成在螺柱的顶部上并且通过导电衬套与通孔接触; 以及一个或多个第三导电材料的导电路径，所述第三导电材料在所述导电衬套的侧壁处通过所述导电衬套连接到所述通孔。还提供了制造半导体结构的方法。

89. 发明申请

US20110115082A1 CONFIGURABLE INTERPOSER 有权
标题翻译：配置插座
公开(公告)号：US20110115082A1
公开(公告)日：2011-05-19
申请号：US12619002
申请日：2009-11-16
申请人： Oleg Gluschenkov , Yunsheng Song , Tso-Hui Ting , Ping-Chuan Wang
发明人： Oleg Gluschenkov , Yunsheng Song , Tso-Hui Ting , Ping-Chuan Wang
IPC分类号： H01L23/48 , H01L21/66 , H01L21/768
CPC分类号： H01L23/49827 , H01L21/486 , H01L22/20 , H01L23/13 , H01L23/481 , H01L24/16 , H01L24/17 , H01L25/0657 , H01L2224/0401 , H01L2224/0603 , H01L2224/1403 , H01L2225/06517 , H01L2225/06541 , H01L2225/06572 , H01L2225/06596 , H01L2924/014 , H01L2924/1301 , H01L2924/1305 , H01L2924/15311 , H05K1/0286 , H05K1/142 , H05K2201/2018 , H05K2203/1572 , Y10T29/49117 , H01L2924/00
摘要： A modularized interposer includes a plurality of interposer units that are assembled to provide a complete set of electrical connections between two semiconductor chips. At least some of the plurality of interposer units can be replaced with other interposer units having an alternate configuration to enable selection of different functional parts of semiconductor chips to be connected through the modularized interposer. Bonding structures, connected to conductive metal pads located at peripheries of neighboring interposer units and an overlying or underlying portion of a semiconductor chip, can provide electrical connections between the neighboring interposer units. The interposer units can be provided by forming through-substrate vias (TSV's) in a substrate, forming patterned conductive structures on the substrate, and cutting the substrate into interposers.
摘要翻译：模块化插入器包括多个插入器单元，其被组合以提供两个半导体芯片之间的完整的电连接。多个插入单元中的至少一些可以被具有替代配置的其它插入单元替代，以便能够通过模块化插入器选择要连接的半导体芯片的不同功能部件。连接到位于相邻插入单元周围的导电金属焊盘和半导体芯片的上部或下部的结合结构可以在相邻插入单元之间提供电连接。可以通过在衬底中形成贯穿衬底通孔（TSV）来形成插入器单元，在衬底上形成图案化的导电结构，并将衬底切割成插入层。

90. 发明申请

US20110104846A1 Thermoelectric 3D Cooling 失效
标题翻译：热电3D冷却
公开(公告)号：US20110104846A1
公开(公告)日：2011-05-05
申请号：US12985360
申请日：2011-01-06
申请人： Louis Lu-Chen Hsu , Ping-Chuan Wang , Xiaojin Wei , Huilong Zhu
发明人： Louis Lu-Chen Hsu , Ping-Chuan Wang , Xiaojin Wei , Huilong Zhu
IPC分类号： H01L21/71
CPC分类号： H01L23/481 , H01L25/0657 , H01L27/16 , H01L2225/06513 , H01L2225/06541 , H01L2225/06589 , H01L2924/0002 , Y10S257/93 , H01L2924/00
摘要： The invention comprises a 3D chip stack with an intervening thermoelectric coupling (TEC) plate. Through silicon vias in the 3D chip stack transfer electronic signals among the chips in the 3D stack, power the TEC plate, as well as distribute heat in the stack from hotter chips to cooler chips.
摘要翻译：本发明包括具有中间热电耦合（TEC）板的3D芯片堆叠。通过3D芯片堆叠中的硅通孔在3D堆叠中的芯片之间传送电子信号，为TEC板供电，以及将堆叠中的热量从较热的芯片分配到较冷的芯片。

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