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81. 发明授权

US06303502B1 MOCVD metal oxide for one transistor memory 失效
标题翻译： MOCVD金属氧化物用于一个晶体管存储器
公开(公告)号：US06303502B1
公开(公告)日：2001-10-16
申请号：US09588940
申请日：2000-06-06
申请人： Sheng Teng Hsu , David R. Evans , Tingkai Li , Jer-shen Maa , Wei-Wei Zhuang
发明人： Sheng Teng Hsu , David R. Evans , Tingkai Li , Jer-shen Maa , Wei-Wei Zhuang
IPC分类号： H01L2144
CPC分类号： H01L21/28291 , H01L29/78391
摘要： A method of fabricating a one-transistor memory includes, on a single crystal silicon substrate, depositing a bottom electrode structure on a gate oxide layer; implanting ions to form a source region and a drain region and activating the implanted ions spin coating the structure with a first ferroelectric layer; depositing a second ferroelectric layer; and annealing the structure to provide a c-axis ferroelectric orientation.
摘要翻译：制造单晶体管存储器的方法包括在单晶硅衬底上，在栅氧化层上沉积底电极结构; 注入离子以形成源极区域和漏极区域并激活注入的离子旋转涂覆第一铁电层的结构; 沉积第二铁电层; 并退火该结构以提供c轴铁电取向。

82. 发明授权

US06288420B1 Composite iridium-metal-oxygen barrier structure with refractory metal companion barrier 有权
$Composite iridium-metal-oxygen barrier structure with refractory metal companion barrier$
标题翻译：复合铱金属氧阻隔结构与难熔金属伴侣屏障
公开(公告)号：US06288420B1
公开(公告)日：2001-09-11
申请号：US09703192
申请日：2000-10-31
申请人： Fengyan Zhang , Sheng Teng Hsu , Jer-shen Maa , Wei-Wei Zhuang
发明人： Fengyan Zhang , Sheng Teng Hsu , Jer-shen Maa , Wei-Wei Zhuang
IPC分类号： H01L2976
CPC分类号： H01L28/75 , H01L21/28568 , H01L28/55
摘要： An Ir—M—O composite film has been provided that is useful in forming an electrode of a ferroelectric capacitor, where M includes a variety of refractory metals. The Ir combination film is resistant to high temperature annealing in oxygen environments. When used with an underlying barrier layer made from the same variety of M transition metals, the resulting conductive barrier also suppresses to diffusion of Ir into any underlying Si substrates. As a result, Ir silicide products are not formed, which degrade the electrode interface characteristics. That is, the Ir combination film remains conductive, not peeling or forming hillocks, during high temperature annealing processes, even in oxygen. The Ir—M—O conductive electrode/barrier structures are useful in nonvolatile FeRAM devices, DRAMs, capacitors, pyroelectric infrared sensors, optical displays, optical switches, piezoelectric transducers, and surface acoustic wave devices. A method for forming an Ir—M—O composite film barrier layer and an Ir—M—O composite film ferroelectric electrode are also provided.
摘要翻译：已经提供了可用于形成铁电电容器的电极的Ir-M-O复合膜，其中M包括各种难熔金属。 Ir组合膜在氧气环境中耐高温退火。当与由相同种类的M过渡金属制成的底层阻挡层一起使用时，所得到的导电屏障还抑制Ir扩散到任何下面的Si衬底中。结果，不形成铱硅化物产物，这降低了电极界面的特性。也就是说，即使在氧气中，Ir组合膜在高温退火过程中仍保持导电性，不会剥离或形成小丘。 Ir-M-O导电电极/屏障结构可用于非易失性FeRAM器件，DRAM，电容器，热释电红外传感器，光学显示器，光开关，压电换能器和表面声波器件。还提供了形成Ir-M-O复合膜阻挡层和Ir-M-O复合膜铁电电极的方法。

83. 发明授权

US06218249B1 MOS transistor having shallow source/drain junctions and low leakage current 失效
标题翻译： MOS晶体管具有较浅的源/漏结和低漏电流
公开(公告)号：US06218249B1
公开(公告)日：2001-04-17
申请号：US09455588
申请日：1999-12-06
申请人： Jer-Shen Maa , Sheng Teng Hsu , Chien-Hsiung Peng
发明人： Jer-Shen Maa , Sheng Teng Hsu , Chien-Hsiung Peng
IPC分类号： H01L21336
CPC分类号： H01L21/28518 , H01L21/28052 , H01L29/665 , H01L29/6659
摘要： A process of forming silicide at uniform rates across the entire source/drain region is provided. A two-step annealing method permits the thickness of the silicide formed on the edge of a silicon electrode to be substantially the same as it is in the center of the electrode. A first, low temperature anneal begins the salicidation process across the source/drain electrode surface. The time and temperature are controlled so that the metal is only partially consumed. The annealing is interrupted to remove excess silicidation metal, especially the unreacted metal overlying oxide areas neighboring the silicon electrode. Then, the silicidation is completed at a higher temperature anneal. Because the excess metal has been removed, the resulting silicide layer is uniformly flat, permitting the transistor to be fabricated with shallow junction areas and low leakage currents. In one embodiment of the invention, the crystalline structure of source and drain surfaces is annihilated before the deposition of metal, to lower annealing temperatures and add precise control to the silicidation process. A transistor having a uniformly thick silicide layer, fabricated in accordance with the above-mentioned method, is also provided.
摘要翻译：提供了在整个源极/漏极区域以均匀的速率形成硅化物的工艺。两步退火方法允许形成在硅电极边缘上的硅化物的厚度与电极中心基本相同。首先，低温退火开始跨越源/漏电极表面的盐析过程。控制时间和温度，使得金属仅被部分消耗。中断退火以去除过量的硅化金属，特别是覆盖与硅电极相邻的氧化物区域的未反应的金属。然后，在较高温度的退火下完成硅化。由于去除了多余的金属，所得到的硅化物层是均匀平坦的，从而允许晶体管被制造成具有浅结的区域和低的漏电流。在本发明的一个实施例中，源极和漏极表面的晶体结构在金属沉积之前被消除，以降低退火温度并且增加对硅化工艺的精确控制。还提供了具有根据上述方法制造的均匀厚的硅化物层的晶体管。

84. 发明授权

US6043164A Method for transferring a multi-level photoresist pattern 失效
标题翻译：转印多层光刻胶图案的方法
公开(公告)号：US6043164A
公开(公告)日：2000-03-28
申请号：US665014
申请日：1996-06-10
申请人： Tue Nguyen , Sheng Teng Hsu , Jer-shen Maa , Bruce Dale Ulrich , Chien-Hsiung Peng
发明人： Tue Nguyen , Sheng Teng Hsu , Jer-shen Maa , Bruce Dale Ulrich , Chien-Hsiung Peng
IPC分类号： G03F7/36 , H01L21/027 , H01L21/033 , H01L21/302 , H01L21/3065 , H01L21/311 , H01L21/768
CPC分类号： H01L21/31144 , H01L21/76807 , H01L21/76813 , H01L21/0274 , H01L21/0334 , H01L2221/1021
摘要： A method is provided for forming an intermediate level in an integrated circuit dielectric during a damascene process using a photoresist mask having an intermediate thickness. The method forms an interconnect to a first depth in the dielectric through an opening in the photoresist pattern. The photoresist profile is partially etched away in the area of the intermediate thickness to reveal a second dielectric surface area. The second dielectric surface area is then etched to a second depth less than the first depth. In this manner, vias can be formed to the first depth, and lines can be formed at a second depth to intersect the vias. The method of the present invention allows a dual damascene process to be performed with a single step of photoresist formation.
摘要翻译：提供一种用于在使用具有中间厚度的光致抗蚀剂掩模的镶嵌工艺期间在集成电路电介质中形成中间电平的方法。该方法通过光致抗蚀剂图案中的开口形成到电介质中的第一深度的互连。光致抗蚀剂轮廓在中间厚度的区域被部分地蚀刻掉以露出第二电介质表面积。然后将第二电介质表面积蚀刻到小于第一深度的第二深度。以这种方式，可以将通孔形成为第一深度，并且可以在第二深度处形成线以与通孔相交。本发明的方法允许通过单步形成光致抗蚀剂来进行双镶嵌工艺。

85. 发明申请

US20080166878A1 Silicon nanostructures and fabrication thereof 审中-公开
标题翻译：硅纳米结构及其制造
公开(公告)号：US20080166878A1
公开(公告)日：2008-07-10
申请号：US11651242
申请日：2007-01-08
申请人： Tingkai Li , Bruce D. Ulrich , Jer-Shen Maa , Sheng Teng Hsu
发明人： Tingkai Li , Bruce D. Ulrich , Jer-Shen Maa , Sheng Teng Hsu
IPC分类号： H01L21/306
CPC分类号： H01L21/31111 , B81C1/00111 , H01L21/3065 , H01L21/31122
摘要： A method of fabricating silicon nanostructures includes preparing a silicon wafer as a substrate; forming an oxide layer hardmask directly on the silicon substrate; patterning and etching the oxide hardmask; wet etching the silicon wafer to remove oxide to reduce the size of the oxide hardmask and to form nanostructure elements; and dry etching, in one or more steps, the silicon wafer using the oxide hardmask to form a desired nanostructure having substantially parallel vertical sidewalls thereon.
摘要翻译：制造硅纳米结构的方法包括制备硅晶片作为基底; 在硅衬底上直接形成氧化层硬掩模; 图案化和蚀刻氧化物硬掩模; 湿蚀刻硅晶片以除去氧化物以减小氧化物硬掩模的尺寸并形成纳米结构元件; 以及使用氧化物硬掩模在一个或多个步骤中干蚀刻硅晶片以形成其上具有基本上平行的垂直侧壁的所需纳米结构。

86. 发明授权

US06777327B2 Method of barrier metal surface treatment prior to Cu deposition to improve adhesion and trench filling characteristics 失效
标题翻译：在Cu沉积之前进行阻隔金属表面处理以提高粘附性和沟槽填充特性的方法
公开(公告)号：US06777327B2
公开(公告)日：2004-08-17
申请号：US09820068
申请日：2001-03-28
申请人： Wei Pan , Jer-Shen Maa , David R. Evans , Sheng Teng Hsu
发明人： Wei Pan , Jer-Shen Maa , David R. Evans , Sheng Teng Hsu
IPC分类号： H01L2144
CPC分类号： H01L21/76843 , C23C16/0209 , C23C16/18 , H01L21/28556 , H01L21/76864 , H01L21/76876
摘要： A rapid thermal process (RTP) provides steps wherein silicon wafers that are pre-coated with barrier metal films by either in-situ or ex-situ CVD or physical vapor deposition (PVD) are pre-treated, prior to deposition of a Cu film thereon, in a temperature range of between 250 and 550 degrees Celsius in a non-reactive gas such as hydrogen gas (H2), argon (Ar), or helium (He), or in an ambient vacuum. The chamber pressure typically is between 0.1 mTorr and 20 Torr, and the RTP time typically is between 30 to 100 seconds. Performing this rapid thermal process before deposition of the Cu film results in a thin, shiny, densely nucleated, and adhesive Cu film deposited on a variety of barrier metal surfaces. The pre-treatment process eliminates variations in the deposited Cu film caused by Cu precursors and is insensitive to variation in precursor composition, volatility, and other precursor variables. Accordingly, the process disclosed herein is an enabling technology for the use of metal organic CVD (MOCVD) Cu in IC fabrication.
摘要翻译：快速热处理（RTP）提供了在沉积Cu膜之前预处理通过原位或原位CVD或物理气相沉积（PVD）预涂覆有阻挡金属膜的硅晶片的步骤在非反应性气体如氢气（H 2），氩气（Ar）或氦气（He））或在环境真空中，在250-550摄氏度的温度范围内。室压力通常在0.1mTorr和20Torr之间，并且RTP时间通常在30至100秒之间。在沉积Cu膜之前进行这种快速热处理会导致沉积在各种阻挡金属表面上的薄而有光泽，致密成核和粘附的Cu膜。预处理过程消除了由Cu前体引起的沉积的Cu膜的变化，并且对前体组成，挥发性和其它前体变量的变化不敏感。因此，本文公开的方法是在IC制造中使用金属有机CVD（MOCVD）Cu的使能技术。

87. 发明授权

US06555456B2 Method of forming iridium conductive electrode/barrier structure 失效
公开(公告)号：US06555456B2
公开(公告)日：2003-04-29
申请号：US10037192
申请日：2001-11-09
申请人： Fengyan Zhang , Jer-shen Maa , Sheng Teng Hsu
发明人： Fengyan Zhang , Jer-shen Maa , Sheng Teng Hsu
IPC分类号： H01L213205
CPC分类号： H01L29/456 , H01L21/28291 , H01L28/55 , H01L28/65
摘要： A conductive barrier, useful as a ferroelectric capacitor electrode, having high temperature stability has been provided. This conductive barrier permits the use of iridium (Ir) metal in IC processes involving annealing. Separating silicon substrate from Ir film with an intervening, adjacent, tantalum (Ta) film has been found to very effective in suppressing diffusion between layers. The Ir prevents the interdiffusion of oxygen into the silicon during annealing. A Ta or TaN layer prevents the diffusion of Ir into the silicon. This Ir/TaN structure protects the silicon interface so that adhesion, conductance, hillock, and peeling problems are minimized. The use of Ti overlying the Ir/TaN structure also helps prevent hillock formation during annealing. A method of forming a multilayer Ir conductive structure and Ir ferroelectric electrode are also provided.

88. 发明授权

US06541385B2 Method for plasma etching of Ir-Ta-O electrode and for post-etch cleaning 失效
公开(公告)号：US06541385B2
公开(公告)日：2003-04-01
申请号：US09855393
申请日：2001-05-14
申请人： Hong Ying , Fengyan Zhang , Jer-Shen Maa , Sheng Teng Hsu
发明人： Hong Ying , Fengyan Zhang , Jer-Shen Maa , Sheng Teng Hsu
IPC分类号： H01L21302
CPC分类号： H01L21/02071 , C04B41/009 , C04B41/5346 , C04B41/91 , C04B2111/00844 , H01L21/32136 , H01L28/60 , C04B35/495
摘要： A method of forming an electrode in an integrated circuit includes preparing a silicon-base substrate, including forming semiconductor structures on the substrate to form an integrated substrate structure; depositing a layer of electrode material on a substrate structure; patterning the layer of electrode material to form electrode elements, wherein said patterning includes plasma etching the layer of electrode material in a plasma reactor in an etching gas atmosphere having a fluorine component therein; and cleaning the substrate structure and electrode elements in a distilled water bath.

89. 发明授权

US06506637B2 Method to form thermally stable nickel germanosilicide on SiGe 失效
公开(公告)号：US06506637B2
公开(公告)日：2003-01-14
申请号：US09834488
申请日：2001-04-12
申请人： Jer-shen Maa , Douglas James Tweet , Sheng Teng Hsu
发明人： Jer-shen Maa , Douglas James Tweet , Sheng Teng Hsu
IPC分类号： H01L2100
CPC分类号： H01L21/28525 , H01L21/28518 , H01L29/45
摘要： A thermally stable nickel germanosilicide on SiGe integrated circuit device, and a method of making the same, is disclosed. During fabrication of the device iridium or cobalt is added at the Ni/SiGe interface to decrease the sheet resistance of the device. The device comprising nickel silicide with iridium on SiGe shows thermal stability at temperatures up to 800° C. The device comprising nickel silicide with cobalt on SiGe shows a decrease in the sheet resistance with temperature, i.e., the resistance remains low when annealing temperatures extend up to and beyond 800° C.

90. 发明授权

US06441417B1 Single c-axis PGO thin film on ZrO2 for non-volatile memory applications and methods of making the same 失效
标题翻译：用于非易失性存储器应用的ZrO 2上的单个c轴PGO薄膜及其制造方法
公开(公告)号：US06441417B1
公开(公告)日：2002-08-27
申请号：US09820022
申请日：2001-03-28
申请人： Fengyan Zhang , Yanjun Ma , Jer-Shen Maa , Wei-Wei Zhuang , Sheng Teng Hsu
发明人： Fengyan Zhang , Yanjun Ma , Jer-Shen Maa , Wei-Wei Zhuang , Sheng Teng Hsu
IPC分类号： H01L2972
CPC分类号： H01L21/28291 , H01L21/31604 , H01L21/31691 , H01L28/56 , H01L29/516
摘要： A thin film structure includes a substantially single-phase, c-axis PGO film on an insulator for use in metal ferroelectric insulator semiconductor single transistor non-volatile memory applications. The PGO on insulator structure can also be used in capacitors, pyroelectric infrared sensors, optical displays, optical switches, piezoelectric transducers, and surface acoustic wave devices. In a preferred embodiment, the PGO film is deposited on a Zirconium Oxide insulator layer.
摘要翻译：薄膜结构包括用于金属铁电绝缘体半导体单晶体管非易失性存储器应用的绝缘体上的基本单相c轴PGO膜。 PGO绝缘体结构也可用于电容器，热释电红外传感器，光学显示器，光开关，压电换能器和表面声波器件中。在优选实施例中，PGO膜沉积在氧化锆绝缘体层上。

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