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81. 发明申请

US20100182842A1 Sense Amplifier and Data Sensing Method Thereof 有权
标题翻译：检测放大器及其数据传感方法
公开(公告)号：US20100182842A1
公开(公告)日：2010-07-22
申请号：US12726542
申请日：2010-03-18
申请人： Chung-Kuang Chen , Yi-Te Shih , Chun-Hsiung Hung
发明人： Chung-Kuang Chen , Yi-Te Shih , Chun-Hsiung Hung
IPC分类号： G11C16/26
CPC分类号： G11C7/14 , G11C7/062 , G11C7/1072
摘要： A data sensing method for sensing data stored in first and second memory cells includes the steps of: setting a first voltage according to a bit-line voltage corresponding to the first memory cell in response to an enabled level of a first clock signal; providing the first voltage as a sensing voltage in response to a disabled level of the first clock signal; comparing the sensing voltage with a reference voltage to generate a first output voltage; setting a second voltage according to a bit-line voltage corresponding to the second memory cell in response to an enabled level of a second clock signal, a phase difference between the first and second clock signals being 180 degrees; providing the second voltage as the sensing voltage in response to a disabled level of the second clock signal; and comparing the sensing voltage with the reference voltage to generate a second output voltage.
摘要翻译：用于感测存储在第一和第二存储单元中的数据的数据感测方法包括以下步骤：响应于第一时钟信号的使能电平，根据与第一存储器单元相对应的位线电压来设置第一电压; 响应于所述第一时钟信号的禁止电平，提供所述第一电压作为感测电压; 将感测电压与参考电压进行比较以产生第一输出电压; 响应于第二时钟信号的使能电平，根据与第二存储器单元相对应的位线电压设置第二电压，第一和第二时钟信号之间的相位差为180度; 响应于第二时钟信号的禁止电平，提供第二电压作为感测电压; 以及将感测电压与参考电压进行比较以产生第二输出电压。

82. 发明申请

US20100182833A1 MEMORY AND BOUNDARY SEARCHING METHOD THEREOF 有权
标题翻译：记忆和边界搜索方法
公开(公告)号：US20100182833A1
公开(公告)日：2010-07-22
申请号：US12355962
申请日：2009-01-19
申请人： Chung-Kuang Chen , Han-Sung Chen , Chun-Hsiung Hung
发明人： Chung-Kuang Chen , Han-Sung Chen , Chun-Hsiung Hung
IPC分类号： G11C16/04 , G11C16/06 , G11C7/00
CPC分类号： G11C29/02 , G11C8/08 , G11C29/021 , G11C29/028 , G11C2029/1202
摘要： A memory and a boundary searching method thereof are provided therein. When searching a boundary of a threshold voltage distribution of the memory, data errors resulted from tail bits of the memory would be corrected. Therefore, a sensing window could be broader, and the boundary of the threshold voltage distribution could be determined precisely.
摘要翻译：其中提供了一种存储器及其边界搜索方法。当搜索存储器的阈值电压分布的边界时，将校正由存储器的尾部位产生的数据错误。因此，感测窗口可以更宽，并且可以精确地确定阈值电压分布的边界。

83. 发明申请

US20090147799A1 CIRCUIT AND METHOD FOR TRANSMITTING DATA STREAM 有权
标题翻译：用于传输数据流的电路和方法
公开(公告)号：US20090147799A1
公开(公告)日：2009-06-11
申请号：US11953940
申请日：2007-12-11
申请人： Chung-Kuang Chen , Chun-Hsiung Hung , Yi-Te Shih
发明人： Chung-Kuang Chen , Chun-Hsiung Hung , Yi-Te Shih
IPC分类号： H04L12/66
CPC分类号： G11C16/26 , G11C7/1012 , G11C7/1027 , G11C2207/002
摘要： A circuit including a first data selection circuit and a second data selection circuit for transmitting a data stream is provided. The first data selection circuit having first controllable channels turns on a first operating channel being one of the first controllable channels in an odd-numbered period and turns off the first controllable channels in an even-numbered period adjacent to the odd-numbered period for transmitting a first bit datum of the data stream. The second data selection circuit having second controllable channels turns off the second controllable channels in the odd-numbered period and turns on a second operating channel being one of the second controllable channels in the even-numbered period for transmitting a second bit datum of the data stream.
摘要翻译：提供一种包括第一数据选择电路和用于发送数据流的第二数据选择电路的电路。具有第一可控通道的第一数据选择电路在奇数周期中导通作为第一可控通道之一的第一操作信道，并在偶数周期中关闭与奇数周期相邻的第一可控通道，用于发送数据流的第一个位数据。具有第二可控通道的第二数据选择电路在奇数周期中关闭第二可控通道，并且在偶数周期中接通作为第二可控通道之一的第二操作通道，用于发送数据的第二位数据流。

84. 发明授权

US07508693B2 One-time-programmable (OTP) memory device and method for testing the same 有权
标题翻译：一次性可编程（OTP）存储器件及其测试方法
公开(公告)号：US07508693B2
公开(公告)日：2009-03-24
申请号：US11388905
申请日：2006-03-24
申请人： Chung-Kuang Chen
发明人： Chung-Kuang Chen
IPC分类号： G11C17/00
CPC分类号： G11C29/52 , G11C17/14 , G11C2216/26
摘要： An OTP memory device and method for testing the same is disclosed. The memory device includes a number of memory cells and each memory cell has an initial threshold voltage. Each memory cell is programmed to have a first threshold voltage larger than a maximum value of the initial threshold voltages in the test program operation. When the memory device is test pass, the memory device is directly provided for a user program operation without need of an erase operation.
摘要翻译：公开了一种OTP存储器件及其测试方法。存储器件包括多个存储器单元，并且每个存储器单元具有初始阈值电压。每个存储单元被编程为在测试程序操作中具有大于初始阈值电压的最大值的第一阈值电压。当存储器件被测试通过时，存储器件直接被提供用于用户编程操作而不需要擦除操作。

85. 发明授权

US07453734B2 Method and apparatus for fast programming of memory 有权
标题翻译：用于快速编程存储器的方法和装置
公开(公告)号：US07453734B2
公开(公告)日：2008-11-18
申请号：US11555620
申请日：2006-11-01
申请人： Chung-Kuang Chen , Yi-Te Shih
发明人： Chung-Kuang Chen , Yi-Te Shih
IPC分类号： G11C16/04
CPC分类号： G11C8/10 , G11C16/10 , G11C2216/14
摘要： Methods and apparatuses are disclosed for programming a page of nonvolatile memory cells across multiple nonvolatile memory cells accessed by multiple word lines.
摘要翻译：公开了用于在跨多个字线访问的多个非易失性存储器单元上编程非易失性存储器单元的页面的方法和装置。

86. 发明申请

US20080101144A1 High program speed MLC memory 有权
标题翻译：高程序速度MLC存储器
公开(公告)号：US20080101144A1
公开(公告)日：2008-05-01
申请号：US11586657
申请日：2006-10-26
申请人： Chung-Kuang Chen
发明人： Chung-Kuang Chen
IPC分类号： G11C7/00
CPC分类号： G11C11/5628 , G11C2211/5622 , G11C2211/5642
摘要： Methods and apparatus are provided for programming a flash multiple level memory cell (MLC) memory. The method may include loading data into an SRAM. The method may include reading a plurality of multiple-bit words from the data in the SRAM and loading the words into at least one latch buffer of a power control circuit. The method may also include pairing one or more bits from one of the words in the latch buffer with one or more bits from another of the words in the latch buffer and determining which of the bit pairs require programming. Moreover, the method may include programming, in parallel, each memory cell with the determined bit pairs. The method may further include programming each multiple level memory cell by applying a voltage to the drain side of a transistor of the memory cells corresponding to the determined bit pairs.
摘要翻译：提供了用于对闪存多级存储器单元（MLC）存储器进行编程的方法和装置。该方法可以包括将数据加载到SRAM中。该方法可以包括从SRAM中的数据读取多个多位字，并将字加载到功率控制电路的至少一个锁存缓冲器中。该方法还可以包括将锁存缓冲器中的一个字中的一个或多个比特与来自锁存缓冲器中的另一个字的一个或多个比特配对，并确定哪个位对需要编程。此外，该方法可以包括并行地编程具有确定的位对的每个存储器单元。该方法还可以包括通过向对应于所确定的位对的存储器单元的晶体管的漏极侧施加电压来对每个多电平存储单元进行编程。

87. 发明授权

US07330376B1 Method for memory data storage by partition into narrower threshold voltage distribution regions 有权
标题翻译：通过分区将存储器数据存储为较窄的阈值电压分布区域的方法
公开(公告)号：US07330376B1
公开(公告)日：2008-02-12
申请号：US11460483
申请日：2006-07-27
申请人： Chung-Kuang Chen , Ful-Long Ni
发明人： Chung-Kuang Chen , Ful-Long Ni
IPC分类号： G11C16/34
CPC分类号： G11C16/3454 , G11C11/5628 , G11C2211/5621 , G11C2211/5634
摘要： A method for data storage of a memory unit and a memory unit using the same are provided in the present invention. The method for data storage of a memory unit includes: first, dividing a memory unit into a plurality of small memory groups; next, defining a threshold voltage distribution region for each small memory group; then, defining a plurality of program verify threshold voltages and a plurality of reference detecting values for each small memory group according to the threshold voltage distribution region of each small memory group; and after that, using these small memory groups to store data.
摘要翻译：在本发明中提供了一种存储单元和使用其的存储单元的数据存储方法。存储单元的数据存储方法包括：首先，将存储器单元划分成多个小存储器组; 接下来，为每个小存储器组定义阈值电压分布区域; 然后根据每个小存储器组的阈值电压分布区域为每个小存储器组定义多个程序验证阈值电压和多个参考检测值; 之后，使用这些小内存组来存储数据。

88. 发明授权

US07257040B2 Fast pre-charge circuit and method of providing same for memory devices 有权
公开(公告)号：US07257040B2
公开(公告)日：2007-08-14
申请号：US11236347
申请日：2005-09-27
申请人： Chung-Kuang Chen
发明人： Chung-Kuang Chen
IPC分类号： G11C7/00
CPC分类号： G11C7/12 , G11C8/08 , G11C2207/2254
摘要： A fast pre-charge circuit and method of providing a fast pre-charge for an integrated circuit memory device is disclosed. The fast pre-charge circuit comprises an address calculating unit and a multi-power driver. The address calculating unit detects the sector distance from driver of the integrated circuit memory device, and the driver provides a voltage to the loading of the integrated circuit memory device based on an output of the address calculating unit. Unlike a conventional fixed-power wordline driver, the driver of the present invention provides multiple voltage levels to the wordline or dynamically adjusts for different loading situations.

89. 发明申请

US20050123838A1 Clear field annular type phase shifting mask 审中-公开
标题翻译：透明环形型移相掩模
公开(公告)号：US20050123838A1
公开(公告)日：2005-06-09
申请号：US10730533
申请日：2003-12-08
申请人： Chung-Hsing Chang , C. H. Lin , Chung-Kuang Chen
发明人： Chung-Hsing Chang , C. H. Lin , Chung-Kuang Chen
IPC分类号： G03F1/00 , G03F1/08 , G03F7/20 , G03F9/00 , H01L21/00
CPC分类号： G03F1/34
摘要： A mask comprises a mask substrate and at least one annular equal line space phase shifting pattern on said mask substrate to produce an opaque region on a semiconductor substrate. A method of manufacturing a mask comprises providing a mask substrate; forming a layer of resist material on said substrate; patterning at least one annular equal line space phase shifting pattern on said resist layer; patterning said pattern onto said mask substrate; removing a remaining portion of said resist layer. A method of transferring a pattern onto a semiconductor substrate comprises illuminating a mask comprising at least one annular equal line space phase shifting pattern on the mask to produce an opaque region on a semiconductor substrate.
摘要翻译：掩模包括掩模基板和在所述掩模基板上的至少一个环形等行空间相移图案，以在半导体基板上产生不透明区域。一种制造掩模的方法包括提供掩模基板; 在所述基板上形成抗蚀材料层; 在所述抗蚀剂层上形成至少一个环形等行空间相移图案; 将所述图案图案化成所述掩模基板; 去除所述抗蚀剂层的剩余部分。将图案转移到半导体衬底上的方法包括在掩模上照射包括至少一个环形等行空间相移图案的掩模，以在半导体衬底上产生不透明区域。

90. 发明授权

US09570133B2 Local word line driver 有权
标题翻译：本地字线驱动
公开(公告)号：US09570133B2
公开(公告)日：2017-02-14
申请号：US13713883
申请日：2012-12-13
申请人： Han-Sung Chen , Chun-Hsiung Hung , Chung-Kuang Chen
发明人： Han-Sung Chen , Chun-Hsiung Hung , Chung-Kuang Chen
IPC分类号： G11C8/08
CPC分类号： G11C8/08
摘要： A memory circuit with a word line driver and control circuitry is disclosed. The word line driver receives a first voltage reference signal, a second voltage reference signal, and an input signal. The word line driver has an output coupled to a word line. The control circuitry is configured to deselect the word line by applying the input signal to the input of the word line driver. For example, in a program operation the word line is deselected to indicate that the word line is not programmed, and another word line is selected to be programmed. During an operation in which the word line is deselected and another word line is selected, the word line discharges through both of a first p-type transistor and a first n-type transistor of the word line driver.
摘要翻译：公开了具有字线驱动器和控制电路的存储器电路。字线驱动器接收第一电压参考信号，第二电压参考信号和输入信号。字线驱动器具有耦合到字线的输出。控制电路被配置为通过将输入信号施加到字线驱动器的输入来取消选择字线。例如，在程序操作中，字线被取消选择以指示字线未被编程，并且另一个字线被选择来被编程。在取消选择字线并选择另一个字线的操作期间，字线通过字线驱动器的第一p型晶体管和第一n型晶体管两者放电。

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