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81. 发明授权

US06421820B1 Semiconductor device fabrication using a photomask with assist features 失效
标题翻译：使用具有辅助功能的光掩模的半导体器件制造
公开(公告)号：US06421820B1
公开(公告)日：2002-07-16
申请号：US09460034
申请日：1999-12-13
申请人： Scott M. Mansfield , Lars W. Liebmann , Shahid Butt , Henning Haffner
发明人： Scott M. Mansfield , Lars W. Liebmann , Shahid Butt , Henning Haffner
IPC分类号： G06F1750
CPC分类号： G03F1/36 , G03F7/70441
摘要： A semiconductor device can be fabricated using a photomask that has been modified using an assist feature design method (see e.g., FIG. 4A) based on normalized feature spacing. Before the device can be fabricated, a layout of original shapes is designed (402). For at least some of the original shapes, the width of the shape and a distance to at least one neighboring shape are measured (404). A modified shape can then be generated by moving edges of the original shape based on the width and distance measurements (406). This modification can be performed on some or all of the original shapes (408). For each of the modified shapes, a normalized space and correct number of assist features can be computed (410). The layout is then modified by adding the correct number of assist features in a space between the modified shape and the neighboring shape (412). This modified layout can then be used in producing a photomask, which can in turn be used to produce a semiconductor device.
摘要翻译：可以使用已经基于归一化特征间隔使用辅助特征设计方法（参见例如图4A）修改的光掩模来制造半导体器件。在可以制造设备之前，设计原始形状的布局（402）。对于至少一些原始形状，测量形状的宽度和至少一个相邻形状的距离（404）。然后可以通过基于宽度和距离测量来移动原始形状的边缘来生成修改的形状（406）。可以对部分或全部原始形状执行该修改（408）。对于每个修改的形状，可以计算归一化空间和正确数量的辅助特征（410）。然后通过在修改的形状和相邻形状之间的空间中添加正确数量的辅助特征来修改布局（412）。然后，该修改后的布局可用于制造光掩模，光掩模又可用于制造半导体器件。

82. 发明授权

US06413683B1 Method for incorporating sub resolution assist features in a photomask layout 有权
标题翻译：在光掩模布局中引入子分辨率辅助功能的方法
公开(公告)号：US06413683B1
公开(公告)日：2002-07-02
申请号：US09602966
申请日：2000-06-23
申请人： Lars W. Liebmann , Scott M. Mansfield
发明人： Lars W. Liebmann , Scott M. Mansfield
IPC分类号： G03F900
CPC分类号： G03F1/36
摘要： A method for developing a photomask layout by which an electrical circuit is imaged that includes introducing sub resolution assist features into a photomask layout by (1) sorting selected details of the main electrical circuit undergoing enhancement according to a predetermined order of importance of enhancement of the selected details of the main electrical circuit to the overall performance of the main electrical circuit, (2) establishing a prioritization for sub resolution assist features associated with the selected details of the main electrical circuit based on the predetermined order of importance of the selected details of the main electrical circuit with which the sub resolution assist features are associated, and (3) incorporating sub resolution assist features in the photomask layout in accordance with the established prioritization of the sub resolution features.
摘要翻译：一种用于开发光掩模布局的方法，通过该方法，电路被成像，其包括通过以下方式将子分辨率辅助特征引入到光掩模布局中：（1）根据预先确定的增强重要性顺序对经历增强的主电路的选定细节进行排序选择主电路的细节到主电路的总体性能，（2）基于所选择的细节的预定重要性顺序，建立与主电路的选定细节相关联的子分辨率辅助特征的优先级与子分辨率辅助特征相关联的主电路，以及（3）根据子分辨率特征的确定的优先级，在光掩模布局中并入子分辨率辅助特征。

83. 发明授权

US6066180A Automatic generation of phase shift masks using net coloring 有权
标题翻译：使用净色自动生成相移掩模
公开(公告)号：US6066180A
公开(公告)日：2000-05-23
申请号：US268414
申请日：1999-03-15
申请人： Young O. Kim , Mark A. Lavin , Lars W. Liebmann , Glenwood S. Weinert
发明人： Young O. Kim , Mark A. Lavin , Lars W. Liebmann , Glenwood S. Weinert
IPC分类号： G03F1/08 , G06F17/50 , H01L21/027 , G06K9/00
CPC分类号： G06F17/5068
摘要： According to the preferred embodiment, a method is provided for automatically coloring VLSI design elements for the purpose of assigning binary properties to the elements. The preferred method is particularly applicable for use generating phase shift mask designs from VLSI CAD datasets. The preferred method uses net coloring to automatically generate a data set of colored elements. The preferred method is not dependent on the order in which the elements are operated upon. The preferred method has the additional advantage of being able to automatically detect conflicts that prevent the VLSI design from being optimally colored. The preferred method is equally applicable to hierarchical VLSI databases with nested components and traditional flat databases. When applied the hierarchical databases, the preferred method provides element coloring with minimal data flattening required.
摘要翻译：根据优选实施例，提供了一种用于自动着色VLSI设计元件以便为元件分配二进制特性的方法。优选的方法特别适用于从VLSI CAD数据集产生相移掩模设计。首选方法使用净色来自动生成彩色元素的数据集。优选的方法不依赖于操作元件的顺序。优选的方法具有能够自动检测阻止VLSI设计被最佳着色的冲突的额外优点。优选的方法同样适用于具有嵌套组件和传统平面数据库的分层VLSI数据库。当应用分层数据库时，首选方法提供了元素着色，需要最少的数据平坦化。

84. 发明授权

US6057063A Phase shifted mask design system, phase shifted mask and VLSI circuit devices manufactured therewith 失效
标题翻译：相移掩模设计系统，相移掩模和用其制造的VLSI电路器件
公开(公告)号：US6057063A
公开(公告)日：2000-05-02
申请号：US824700
申请日：1997-04-14
申请人： Lars W. Liebmann , Ioana C. Graur , Young O. Kim , Mark A. Lavin , Alfred K. Wong
发明人： Lars W. Liebmann , Ioana C. Graur , Young O. Kim , Mark A. Lavin , Alfred K. Wong
IPC分类号： G03F1/00 , G06F17/50 , G03F9/00
CPC分类号： G06F17/5068 , G03F1/26
摘要： A process for creating and verifying a design of phase-shifted masks utilizing at least one phase shift region employing a computer-aided design system. A chip design is provided. A phase-shift mask design capable of producing the chip design is created. Features in a design of the phase-shifted mask that require phase shifting are located. Uncolored phase regions are created on opposite sides of the features. Proper phase termination of the phase regions is ensured based upon space constraints of a phase-shifted mask technique utilized. Phases are determined for the phase regions. Whether coloring errors and un-phase-shiftable design features exist is determined. Mask process specific overlaps and expansions are applied to the mask design to prepare designed data levels for mask manufacture. A residual phase edge image removal design is derived.
摘要翻译：利用采用计算机辅助设计系统的至少一个相移区域来创建和验证相移掩模的设计的过程。提供芯片设计。产生了能够产生芯片设计的相移掩模设计。定位需要相移的相移掩模设计中的特征。未着色的相位区域在特征的相对侧上创建。基于所采用的相移掩模技术的空间限制，确保相位区域的正确相位终止。确定相位区域的相位。是否存在着色误差和不相移设计特征。掩模过程特定的重叠和扩展被应用于掩模设计以准备用于掩模制造的设计的数据级。导出残留相边缘图像去除设计。

85. 发明授权

US5923562A Method for automatically eliminating three way intersection design conflicts in phase edge, phase shift designs 失效
标题翻译：在相位相移设计中自动消除三路交叉设计冲突的方法
公开(公告)号：US5923562A
公开(公告)日：1999-07-13
申请号：US733584
申请日：1996-10-18
申请人： Lars W. Liebmann , Robert Thomas Sayah
发明人： Lars W. Liebmann , Robert Thomas Sayah
IPC分类号： H01L21/027 , G06F17/00 , G06F17/50 , H01L20060101
CPC分类号： G06F17/5068 , G06F2217/12 , Y02P90/265
摘要： A method automatically locates and eliminates the most frequently encountered phase conflict in phase edge phase shift mask (PSM) designs used in the manufacture of VLSI circuits. The process is implemented as an automatic CAD routine that locates and widens one leg of a three way intersection to avoid phase conflicts. CAD and design rule checking techniques are used to first locate and then to resolve design conflicts prior to actually executing the very time consuming phase shift mask design. The original circuit design is manipulated prior to or as part of the design rule checking, allowing the verification of the manipulations made prior to handing the design off to the mask layout and mask data preparation group.
摘要翻译：一种方法自动定位并消除了在制造VLSI电路中使用的相位边缘相移掩模（PSM）设计中最常遇到的相位冲突。该过程被实现为自动CAD程序，其定位和加宽三路交叉口的一条腿以避免相位冲突。 CAD和设计规则检查技术用于首先定位，然后在实际执行非常耗时的相移掩模设计之前解决设计冲突。原始电路设计在设计规则检查之前或作为设计规则检查的一部分进行操作，允许在将设计移交到掩模布局和掩模数据准备组之前进行的操作的验证。

86. 发明授权

US5538833A High resolution phase edge lithography without the need for a trim mask 失效
标题翻译：高分辨率相缘光刻，无需修剪蒙版
公开(公告)号：US5538833A
公开(公告)日：1996-07-23
申请号：US285575
申请日：1994-08-03
申请人： Richard A. Ferguson , Lars W. Liebmann , Ronald M. Martino , Thomas H. Newman
发明人： Richard A. Ferguson , Lars W. Liebmann , Ronald M. Martino , Thomas H. Newman
IPC分类号： G03F1/34 , G03F7/20 , H01L21/027 , G03C5/00
CPC分类号： G03F1/34
摘要： A process of phase edge lithography is employed in the manufacture of very large scale integrated (VLSI) chips in which chrome images are biased on a phase edge of a phase shift mask (PSM) and the mask overexposed to compensate for the positive bias. This overexposure eliminates any residual images from the phase edge mask with minimum impact to the desired images. This simple process results in a trim-less phase edge process that takes advantage of the improved resolution and process latitude of phase edge PSMs while avoiding layout impacts caused by a trim mask or other phase edge elimination methods.
摘要翻译：在制造非常大规模的集成（VLSI）芯片的过程中采用相位光刻技术，其中镀铬图像偏置在相移掩模（PSM）的相位边缘上，并且掩模过度曝光以补偿正偏压。这种过度曝光可以消除来自相边缘掩模的任何残留图像，同时对所需图像的影响最小。这个简单的过程产生了一个无需修剪的相位边缘过程，利用改进的分离和相位边缘PSM的处理纬度，同时避免了由修剪掩模或其他相位边缘消除方法引起的布局影响。

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