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81. 发明授权

US06576530B1 Method of fabricating shallow trench isolation 有权
标题翻译：浅沟槽隔离的制作方法
公开(公告)号：US06576530B1
公开(公告)日：2003-06-10
申请号：US10261648
申请日：2002-10-01
申请人： Yi-Nan Chen , Chung Peng Hao , Chung-Yuan Lee
发明人： Yi-Nan Chen , Chung Peng Hao , Chung-Yuan Lee
IPC分类号： H01L2176
CPC分类号： H01L21/31608 , H01L21/02164 , H01L21/02274 , H01L21/02304 , H01L21/76224
摘要： A method of fabricating shallow trench isolation. A liner silicon nitride layer and a liner silicon oxide layer are used as a hard mask to etch a semiconductor substrate, forming a shallow trench. Then, after forming a thermal oxide film on the inner wall of the shallow trench, a silicon rich oxide is formed using HDPCVD with no bias application. A silicon oxide layer is then formed to fill the shallow trench using HDPCVD with bias application.
摘要翻译：一种制造浅沟槽隔离的方法。使用衬里氮化硅层和衬里氧化硅层作为硬掩模来蚀刻半导体衬底，形成浅沟槽。然后，在浅沟槽的内壁上形成热氧化膜后，使用HDPCVD形成富硅氧化物，而不施加偏压。然后形成氧化硅层，以使用具有偏压应用的HDPCVD来填充浅沟槽。

82. 发明授权

US06426271B2 Method of rounding the corner of a shallow trench isolation region 有权
公开(公告)号：US06426271B2
公开(公告)日：2002-07-30
申请号：US09790493
申请日：2001-02-23
申请人： Yi-Nan Chen , Hsien-Wen Liu
发明人： Yi-Nan Chen , Hsien-Wen Liu
IPC分类号： H01L2176
CPC分类号： H01L21/76232 , H01L21/3065 , H01L21/31116 , H01L21/31662
摘要： The present invention provides a method of rounding the corner of the shallow trench isolation region, comprising the steps of: etching silicon substrate using a patterned mask layer and a pad oxide layer as an etch mask to form a trench in the silicon substrate, then removing part of the pad oxide layer, forming silicon dioxide on the surface of the silicon substrate in the trench, then removing part of the pad oxide layer and the silicon dioxide on the surface of the silicon substrate in the trench, repeating the step of oxidizing the surface of the silicon substrate and removing part of the pad oxide layer and silicon dioxide to round the corner of the trench, then performing the subsequent steps to form the shallow trench isolation region.

83. 发明授权

US09054131B2 Vertical MOSFET electrostatic discharge device 有权
标题翻译：垂直MOSFET静电放电装置
公开(公告)号：US09054131B2
公开(公告)日：2015-06-09
申请号：US13281293
申请日：2011-10-25
申请人： Jeng-Hsing Jang , Yi-Nan Chen , Hsien-Wen Liu
发明人： Jeng-Hsing Jang , Yi-Nan Chen , Hsien-Wen Liu
IPC分类号： H01L29/78 , H01L21/336 , H01L29/66 , H01L27/02 , H01L21/8234 , H01L29/423 , H01L29/06
CPC分类号： H01L29/66666 , H01L21/823487 , H01L27/0266 , H01L29/0692 , H01L29/4238 , H01L29/7827 , H01L2924/0002 , H01L2924/00
摘要： A vertical MOSFET electrostatic discharge device is disclosed, including a substrate comprising a plurality of trenches, a recessed gate disposed in each trench, a drain region disposed between each of the two neighboring recessed gates, an electrostatic discharge implant region disposed under each drain region, and a source region surrounding and disposed under the recessed gates and the electrostatic discharge implant regions.
摘要翻译：公开了一种垂直MOSFET静电放电装置，包括：包括多个沟槽的衬底;设置在每个沟槽中的凹入栅极，设置在两个相邻凹入栅极中的每一个之间的漏极区域，设置在每个漏极区域下方的静电放电注入区域，以及围绕并设置在凹入栅极和静电放电注入区域下面的源极区域。

84. 发明授权

US08759907B2 Memory device having buried bit line and vertical transistor and fabrication method thereof 有权
标题翻译：具有掩埋位线和垂直晶体管的存储器件及其制造方法
公开(公告)号：US08759907B2
公开(公告)日：2014-06-24
申请号：US13094796
申请日：2011-04-26
申请人： Tieh-Chiang Wu , Yi-Nan Chen , Hsien-Wen Liu
发明人： Tieh-Chiang Wu , Yi-Nan Chen , Hsien-Wen Liu
IPC分类号： H01L29/78 , H01L21/336 , H01L27/108 , H01L29/66
CPC分类号： H01L29/66666 , H01L21/2257 , H01L27/10876 , H01L27/10885 , H01L29/7827
摘要： A method of forming a buried bit line is provided. A substrate is provided and a line-shaped trench region is defined in the substrate. A line-shaped trench is formed in the line-shaped trench region of the substrate. The line-shaped trench includes a sidewall surface and a bottom surface. Then, the bottom surface of the line-shaped trench is widened to form a curved bottom surface. Next, a doping area is formed in the substrate adjacent to the curved bottom surface. Lastly, a buried conductive layer is formed on the doping area such that the doping area and the buried conductive layer together constitute the buried bit line.
摘要翻译：提供一种形成掩埋位线的方法。提供衬底并且在衬底中限定线状沟槽区域。在基板的线状沟槽区域中形成线状沟槽。线状沟槽包括侧壁表面和底部表面。然后，将线状沟槽的底面加宽，形成弯曲的底面。接下来，在与该弯曲底面相邻的基板上形成掺杂区域。最后，在掺杂区域上形成掩埋导电层，使得掺杂区域和掩埋导电层一起构成掩埋位线。

85. 发明授权

US08758984B2 Method of forming gate conductor structures 有权
标题翻译：形成栅极导体结构的方法
公开(公告)号：US08758984B2
公开(公告)日：2014-06-24
申请号：US13103108
申请日：2011-05-09
申请人： Chang-Ming Wu , Yi-Nan Chen , Hsien-Wen Liu
发明人： Chang-Ming Wu , Yi-Nan Chen , Hsien-Wen Liu
IPC分类号： H01L21/70
CPC分类号： H01L21/32139 , H01L21/28123 , H01L21/28132
摘要： A method of forming gate conductor structures. A substrate having thereon a gate electrode layer is provided. A multi-layer hard mask is formed overlying the gate electrode layer. The multi-layer hard mask comprises a first hard mask, a second hard mask, and a third hard mask. A photoresist pattern is formed on the multi-layer hard mask. A first etching process is performed to etch the third hard mask, using the photoresist pattern as a first etch resist, thereby forming a patterned third hard mask. A second etching process is performed to etch the second hard mask and the first hard mask, using the patterned third hard mask as a second etch resist, thereby forming a patterned first hard mask. A third etching process is performed to etch a layer of the gate electrode layer, using the patterned first hard mask as a third etch resist.
摘要翻译：一种形成栅极导体结构的方法。提供了具有栅电极层的基板。形成覆盖栅电极层的多层硬掩模。多层硬掩模包括第一硬掩模，第二硬掩模和第三硬掩模。在多层硬掩模上形成光刻胶图形。执行第一蚀刻工艺以蚀刻第三硬掩模，使用光致抗蚀剂图案作为第一蚀刻抗蚀剂，由此形成图案化的第三硬掩模。执行第二蚀刻工艺以蚀刻第二硬掩模和第一硬掩模，使用图案化的第三硬掩模作为第二蚀刻抗蚀剂，由此形成图案化的第一硬掩模。执行第三蚀刻工艺以蚀刻栅极电极层的层，使用图案化的第一硬掩模作为第三蚀刻抗蚀剂。

86. 发明授权

US08476764B2 Bonding pad structure for semiconductor devices 有权
标题翻译：用于半导体器件的接合焊盘结构
公开(公告)号：US08476764B2
公开(公告)日：2013-07-02
申请号：US13235491
申请日：2011-09-18
申请人： Tse-Yao Huang , Yi-Nan Chen , Hsien-Wen Liu
发明人： Tse-Yao Huang , Yi-Nan Chen , Hsien-Wen Liu
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L24/05 , H01L2224/02166 , H01L2224/04042 , H01L2224/05085 , H01L2224/05095 , H01L2224/05624
摘要： A bonding pad structure includes a semiconductor substrate having thereon a plurality of inter-metal dielectric (IMD) layers comprising at least a topmost IMD layer; a bondable metal pad layer disposed on a surface of the topmost IMD layer within a pad forming region; a passivation layer covering a periphery of the bondable metal pad layer and the surface of the topmost IMD layer; and a plurality of via plugs disposed in the topmost IMD layer within an annular region of the pad forming region, wherein the via plugs are not formed in a central region of the pad forming region.
摘要翻译：焊盘结构包括其上具有包括至少最上面的IMD层的多个金属间电介质（IMD）层的半导体衬底; 可焊接金属焊盘层，其设置在焊盘形成区域内的最上层IMD层的表面上; 覆盖可焊接金属焊盘层的周边和最上面的IMD层的表面的钝化层; 以及多个通孔插塞，其设置在焊盘形成区域的环形区域内的最上层的IMD层中，其中通孔插塞不形成在焊盘形成区域的中心区域中。

87. 发明授权

US08420541B2 Method for increasing adhesion between polysilazane and silicon nitride 有权
标题翻译：增加聚硅氮烷和氮化硅之间粘附力的方法
公开(公告)号：US08420541B2
公开(公告)日：2013-04-16
申请号：US13102506
申请日：2011-05-06
申请人： Shing-Yih Shih , Yi-Nan Chen , Hsien-Wen Liu
发明人： Shing-Yih Shih , Yi-Nan Chen , Hsien-Wen Liu
IPC分类号： H01L21/311 , H01L21/31
CPC分类号： H01L21/76224 , H01L21/02164 , H01L21/0217 , H01L21/02222 , H01L21/02282 , H01L21/02307 , H01L21/02326 , H01L21/3105 , H01L21/76227
摘要： A method for increasing adhesion between polysilazane and silicon nitride is disclosed, comprising, providing a substrate comprising a trench, forming a silicon nitride liner layer on a bottom surface and a sidewall of the trench, performing a treating process to the silicon nitride liner layer for producing a hydrophilic surface with OH groups that can increase adhesion between the silicon nitride liner layer and a subsequently formed polysilazane coating layer, and forming a polysilazane coating layer into the trench and on the silicon nitride liner layer.
摘要翻译：公开了一种用于增加聚硅氮烷和氮化硅之间的粘合性的方法，包括：提供包括沟槽的衬底，在沟槽的底表面和侧壁上形成氮化硅衬垫层，对氮化硅衬垫层执行处理工艺产生具有OH基团的亲水表面，其可以增加氮化硅衬垫层和随后形成的聚硅氮烷涂层之间的粘附性，以及在沟槽和氮化硅衬垫层中形成聚硅氮烷涂层。

88. 发明申请

US20130068264A1 WAFER SCRUBBER APPARATUS 审中-公开
公开(公告)号：US20130068264A1
公开(公告)日：2013-03-21
申请号：US13238929
申请日：2011-09-21
申请人： Jeng-Hsing Jang , Yi-Nan Chen , Hsien-Wen Liu
发明人： Jeng-Hsing Jang , Yi-Nan Chen , Hsien-Wen Liu
IPC分类号： B08B3/00
CPC分类号： H01L21/67051 , H01L21/67046
摘要： A wafer scrubber apparatus is disclosed, including a chamber, and holder connecting to a spindle disposed in the chamber, wherein the holder supports a wafer, and a gas purge pipe disposed at the top of a wall of the chamber, wherein the gas purge pipe comprises a plurality of gas injection holes facing downward to purge gas along the chamber wall making water flow along the chamber wall more smoothly and more quickly for preventing the water from scattering back to the wafer.
摘要翻译：公开了一种晶片洗涤器装置，包括一个腔室，以及连接到设置在腔室中的心轴的保持器，其中保持器支撑晶片，以及设置在腔室壁顶部的气体吹扫管，其中气体吹扫管包括面向下的多个气体注入孔以沿着室壁吹扫气体，使得沿着室壁的水流更顺利和更快地用于防止水散射回到晶片。

89. 发明申请

US20120309155A1 SEMICONDUCTOR PROCESS 审中-公开
标题翻译：半导体工艺
公开(公告)号：US20120309155A1
公开(公告)日：2012-12-06
申请号：US13152283
申请日：2011-06-03
申请人： Wen-Chieh Wang , Yi-Nan Chen , Hsien-Wen Liu
发明人： Wen-Chieh Wang , Yi-Nan Chen , Hsien-Wen Liu
IPC分类号： H01L21/8239
CPC分类号： H01L27/1052 , H01L21/76816 , H01L21/76897
摘要： A semiconductor process is provided. A substrate is provided, gates each including a silicon layer, a silicide layer and a cap layer are formed thereon, and doped regions are formed at two sides of each gate. An insulating layer is formed to cover a memory region and a periphery region. First contact holes are formed in the insulating layer in the memory region, and each first contact hole is disposed between the two adjacent gates and exposes the doped region. A contact plug is formed in each first contact hole to electrically connect the doped region. A patterned mask layer is formed on the substrate to cover the memory region and expose a portion of the periphery region. Using the patterned mask layer as a mask, second and third contact holes are formed in the insulating layer in the periphery region, to expose the silicide layer and the doped region.
摘要翻译：提供半导体工艺。提供衬底，在其上形成各自包括硅层，硅化物层和覆盖层的栅极，并且在每个栅极的两侧形成掺杂区域。形成绝缘层以覆盖存储区域和周边区域。第一接触孔形成在存储区域中的绝缘层中，并且每个第一接触孔设置在两个相邻栅极之间并且暴露掺杂区域。在每个第一接触孔中形成接触插塞以电连接掺杂区域。在基板上形成图案化掩模层以覆盖存储区域并暴露外围区域的一部分。使用图案化掩模层作为掩模，在外围区域的绝缘层中形成第二和第三接触孔，以暴露硅化物层和掺杂区域。

90. 发明申请

US20120298992A1 TEST LAYOUT STRUCTURE 审中-公开
标题翻译：测试布局结构
公开(公告)号：US20120298992A1
公开(公告)日：2012-11-29
申请号：US13117126
申请日：2011-05-26
申请人： Chin-Te Kuo , Yi-Nan Chen , Hsien-Wen Liu
发明人： Chin-Te Kuo , Yi-Nan Chen , Hsien-Wen Liu
IPC分类号： H01L23/544
CPC分类号： H01L22/34
摘要： A test layout structure includes a substrate, a first oxide region of a first height, a second oxide region of a second height, a plurality of border regions, and a test layout pattern. The first oxide region is disposed on the substrate. The second oxide region is also disposed on the substrate and adjacent to the first oxide region. The first height is substantially different from the second height. A plurality of border regions are disposed between the first oxide region and the second oxide region. The test layout pattern includes a plurality of individual sections. A test region is disposed between two of the adjacent individual sections which are parallel to each other.
摘要翻译：测试布局结构包括基板，第一高度的第一氧化物区域，第二高度的第二氧化物区域，多个边界区域和测试布局图案。第一氧化物区域设置在基板上。第二氧化物区域也设置在衬底上并与第一氧化物区域相邻。第一高度与第二高度大致不同。多个边界区域设置在第一氧化物区域和第二氧化物区域之间。测试布局图案包括多个单独的部分。测试区域设置在彼此平行的两个相邻的单独部分之间。

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