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1. 发明授权

US08759907B2 Memory device having buried bit line and vertical transistor and fabrication method thereof 有权
标题翻译：具有掩埋位线和垂直晶体管的存储器件及其制造方法
公开(公告)号：US08759907B2
公开(公告)日：2014-06-24
申请号：US13094796
申请日：2011-04-26
申请人： Tieh-Chiang Wu , Yi-Nan Chen , Hsien-Wen Liu
发明人： Tieh-Chiang Wu , Yi-Nan Chen , Hsien-Wen Liu
IPC分类号： H01L29/78 , H01L21/336 , H01L27/108 , H01L29/66
CPC分类号： H01L29/66666 , H01L21/2257 , H01L27/10876 , H01L27/10885 , H01L29/7827
摘要： A method of forming a buried bit line is provided. A substrate is provided and a line-shaped trench region is defined in the substrate. A line-shaped trench is formed in the line-shaped trench region of the substrate. The line-shaped trench includes a sidewall surface and a bottom surface. Then, the bottom surface of the line-shaped trench is widened to form a curved bottom surface. Next, a doping area is formed in the substrate adjacent to the curved bottom surface. Lastly, a buried conductive layer is formed on the doping area such that the doping area and the buried conductive layer together constitute the buried bit line.
摘要翻译：提供一种形成掩埋位线的方法。提供衬底并且在衬底中限定线状沟槽区域。在基板的线状沟槽区域中形成线状沟槽。线状沟槽包括侧壁表面和底部表面。然后，将线状沟槽的底面加宽，形成弯曲的底面。接下来，在与该弯曲底面相邻的基板上形成掺杂区域。最后，在掺杂区域上形成掩埋导电层，使得掺杂区域和掩埋导电层一起构成掩埋位线。

2. 发明申请

US20120256279A1 METHOD OF GATE WORK FUNCTION ADJUSTMENT AND METAL GATE TRANSISTOR 有权
标题翻译：门工作功能调整和金属栅极晶体管的方法
公开(公告)号：US20120256279A1
公开(公告)日：2012-10-11
申请号：US13081505
申请日：2011-04-07
申请人： Tieh-Chiang Wu , Yi-Nan Chen , Hsien-Wen Liu
发明人： Tieh-Chiang Wu , Yi-Nan Chen , Hsien-Wen Liu
IPC分类号： H01L29/772 , H01L21/336
CPC分类号： H01L29/4983 , H01L21/265 , H01L21/26586 , H01L21/28079 , H01L21/28105 , H01L29/495 , H01L29/66575 , H01L29/66795 , H01L29/78 , H01L29/7856
摘要： A method of gate work function adjustment includes the steps as follow. First, a substrate is provided, wherein a metal gate is disposed on the substrate, a source doping region and a drain doping region are disposed in the substrate at opposite sites of the metal gate, wherein the metal gate is divided into a source side adjacent to the source doping region, and a drain side adjacent to the drain doping region. Later, a mask layer is formed to cover the source doping region and the drain doping region. After that, an implantation process is performed to implant nitrogen into the metal gate so as to make a first nitrogen concentration of the source side higher than a second nitrogen concentration of the drain side. Finally, the mask layer is removed.
摘要翻译：门功功能调整方法包括以下步骤。首先，提供基板，其中金属栅极设置在基板上，源极掺杂区域和漏极掺杂区域设置在金属栅极的相对位置处的基板中，其中金属栅极被分成相邻的源极侧到源极掺杂区域和与漏极掺杂区域相邻的漏极侧。然后，形成掩模层以覆盖源极掺杂区域和漏极掺杂区域。之后，进行注入工艺以将氮注入到金属栅中，以使源极侧的第一氮浓度高于漏极侧的第二氮浓度。最后，去除掩模层。

3. 发明授权

US08723261B2 Recessed gate transistor with cylindrical fins 有权
标题翻译：带圆柱形鳍片的嵌入式晶体管
公开(公告)号：US08723261B2
公开(公告)日：2014-05-13
申请号：US13081499
申请日：2011-04-07
申请人： Tieh-Chiang Wu , Yi-Nan Chen , Hsien-Wen Liu
发明人： Tieh-Chiang Wu , Yi-Nan Chen , Hsien-Wen Liu
IPC分类号： H01L27/12
CPC分类号： H01L27/10879 , H01L27/10826 , H01L29/4236 , H01L29/785
摘要： A recessed gate transistor with cylindrical fins is disclosed. The recessed gate transistor is disposed in an active region of a semiconductor substrate. Two isolation regions disposed in the semiconductor substrate to define an active region therebetween. The recessed gate transistor includes a gate structure, a source doping region and a drain doping region. The gate structure has at least three fins forms a concave and convex bottom of the gate structure. The front fin is disposed in one of the two isolation regions, the middle fin is disposed in the active region and a last fin disposed in the other one of the two isolation regions. The front fin and the last fin are both cylindrical. A lower part of the gate structure is M-shaped when view from the source doping region to the drain doping region direction.
摘要翻译：公开了一种具有圆柱形翅片的嵌入式栅极晶体管。凹陷栅极晶体管设置在半导体衬底的有源区中。设置在半导体衬底中以限定它们之间的有源区的两个隔离区。凹陷栅晶体管包括栅极结构，源极掺杂区和漏极掺杂区。栅极结构具有至少三个鳍形成栅极结构的凹凸底部。前鳍设置在两个隔离区域之一中，中间翅片设置在有源区域中，最后一个翅片设置在两个隔离区域中的另一个中。前鳍和最后的鳍都是圆柱形的。当从源极掺杂区域到漏极掺杂区域方向观察时，栅极结构的下部是M形的。

4. 发明授权

US08614467B2 Method of gate work function adjustment and metal gate transistor 有权
标题翻译：栅极功能调节方法和金属栅极晶体管
公开(公告)号：US08614467B2
公开(公告)日：2013-12-24
申请号：US13081505
申请日：2011-04-07
申请人： Tieh-Chiang Wu , Yi-Nan Chen , Hsien-Wen Liu
发明人： Tieh-Chiang Wu , Yi-Nan Chen , Hsien-Wen Liu
IPC分类号： H01L29/66
CPC分类号： H01L29/4983 , H01L21/265 , H01L21/26586 , H01L21/28079 , H01L21/28105 , H01L29/495 , H01L29/66575 , H01L29/66795 , H01L29/78 , H01L29/7856
摘要： A method of gate work function adjustment includes the steps as follow. First, a substrate is provided, wherein a metal gate is disposed on the substrate, a source doping region and a drain doping region are disposed in the substrate at opposite sites of the metal gate, wherein the metal gate is divided into a source side adjacent to the source doping region, and a drain side adjacent to the drain doping region. Later, a mask layer is formed to cover the source doping region and the drain doping region. After that, an implantation process is performed to implant nitrogen into the metal gate so as to make a first nitrogen concentration of the source side higher than a second nitrogen concentration of the drain side. Finally, the mask layer is removed.
摘要翻译：门功功能调整方法包括以下步骤。首先，提供基板，其中金属栅极设置在基板上，源极掺杂区域和漏极掺杂区域设置在金属栅极的相对位置处的基板中，其中金属栅极被分成相邻的源极侧到源极掺杂区域和与漏极掺杂区域相邻的漏极侧。然后，形成掩模层以覆盖源极掺杂区域和漏极掺杂区域。之后，进行注入工艺以将氮注入到金属栅中，以使源极侧的第一氮浓度高于漏极侧的第二氮浓度。最后，去除掩模层。

5. 发明授权

US08530306B2 Method of forming a slit recess channel gate 有权
标题翻译：形成狭缝凹槽通道浇口的方法
公开(公告)号：US08530306B2
公开(公告)日：2013-09-10
申请号：US13117162
申请日：2011-05-27
申请人： Tieh-Chiang Wu , Yi-Nan Chen , Hsien-Wen Liu
发明人： Tieh-Chiang Wu , Yi-Nan Chen , Hsien-Wen Liu
IPC分类号： H01L21/336 , H01L29/66
CPC分类号： H01L29/4236 , H01L21/28114 , H01L21/76224 , H01L29/42376 , H01L29/4966 , H01L29/66553
摘要： A slit recess channel gate is further provided. The slit recess channel gate includes a substrate, a gate dielectric layer, a first conductive layer and a second conductive layer. The substrate has a first trench. The gate dielectric layer is disposed on a surface of the first trench and the first conductive layer is embedded in the first trench. The second conductive layer is disposed on the first conductive layer and aligned with the first conductive layer above the main surface, wherein a bottom surface area of the second conductive layer is substantially smaller than a top surface area of the second conductive layer. The present invention also provides a method of forming the slit recess channel gate.
摘要翻译：还设置狭缝凹槽通道门。狭缝凹槽通道门包括衬底，栅介质层，第一导电层和第二导电层。衬底具有第一沟槽。栅介质层设置在第一沟槽的表面上，第一导电层嵌入第一沟槽中。第二导电层设置在第一导电层上并与主表面上的第一导电层对准，其中第二导电层的底表面积基本上小于第二导电层的顶表面积。本发明还提供了形成狭缝凹槽通道浇口的方法。

6. 发明授权

US08525262B2 Transistor with buried fins 有权
标题翻译：晶体管埋地鳍
公开(公告)号：US08525262B2
公开(公告)日：2013-09-03
申请号：US13081509
申请日：2011-04-07
申请人： Tieh-Chiang Wu , Yi-Nan Chen , Hsien-Wen Liu
发明人： Tieh-Chiang Wu , Yi-Nan Chen , Hsien-Wen Liu
IPC分类号： H01L27/12
CPC分类号： H01L27/10879 , H01L27/10826 , H01L29/1037 , H01L29/4236 , H01L29/42376 , H01L29/78
摘要： The present invention disclosed a recessed gate transistor with buried fins. The recessed gate transistor with buried fins is disposed in an active region on a semiconductor substrate. Two isolation regions disposed in the semiconductor substrate, and sandwich the active region. A gate structure is disposed in the semiconductor substrate, wherein the gate structure includes: an upper part and a lower part. The upper part is disposed in the active region and a lower part having a front fin disposed in one of the two isolation regions, at least one middle fin disposed in the active region, and a last fin disposed in the other one of the two isolation regions, wherein the front fin are both elliptic cylindrical.
摘要翻译：本发明公开了一种具有埋地鳍片的凹陷式栅极晶体管。具有埋入散热片的嵌入式栅极晶体管设置在半导体衬底上的有源区中。两个隔离区域设置在半导体衬底中并夹持有源区。栅极结构设置在半导体衬底中，其中栅极结构包括：上部和下部。上部设置在有源区域中，下部具有设置在两个隔离区域之一中的前翅片，设置在有源区域中的至少一个中间翅片，以及设置在两个隔离物中的另一个中的最后一个翅片区域，其中前鳍都是椭圆柱形。

7. 发明申请

US20120273874A1 MEMORY DEVICE HAVING BURIED BIT LINE AND VERTICAL TRANSISTOR AND FABRICATION METHOD THEREOF 有权
标题翻译：具有BIT线和垂直晶体管的存储器件及其制造方法
公开(公告)号：US20120273874A1
公开(公告)日：2012-11-01
申请号：US13094796
申请日：2011-04-26
申请人： Tieh-Chiang Wu , Yi-Nan Chen , Hsien-Wen Liu
发明人： Tieh-Chiang Wu , Yi-Nan Chen , Hsien-Wen Liu
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/66666 , H01L21/2257 , H01L27/10876 , H01L27/10885 , H01L29/7827
摘要： A method of forming a buried bit line is provided. A substrate is provided and a line-shaped trench region is defined in the substrate. A line-shaped trench is formed in the line-shaped trench region of the substrate. The line-shaped trench includes a sidewall surface and a bottom surface. Then, the bottom surface of the line-shaped trench is widened to form a curved bottom surface. Next, a doping area is formed in the substrate adjacent to the curved bottom surface. Lastly, a buried conductive layer is formed on the doping area such that the doping area and the buried conductive layer together constitute the buried bit line.
摘要翻译：提供一种形成掩埋位线的方法。提供衬底并且在衬底中限定线状沟槽区域。在基板的线状沟槽区域中形成线状沟槽。线状沟槽包括侧壁表面和底部表面。然后，将线状沟槽的底面加宽，形成弯曲的底面。接下来，在与该弯曲底面相邻的基板上形成掺杂区域。最后，在掺杂区域上形成掩埋导电层，使得掺杂区域和掩埋导电层一起构成掩埋位线。

8. 发明申请

US20120299185A1 Slit Recess Channel Gate and Method of Forming the Same 有权
标题翻译：狭缝凹槽通道门及其形成方法
公开(公告)号：US20120299185A1
公开(公告)日：2012-11-29
申请号：US13117162
申请日：2011-05-27
申请人： Tieh-Chiang Wu , Yi-Nan Chen , Hsien-Wen Liu
发明人： Tieh-Chiang Wu , Yi-Nan Chen , Hsien-Wen Liu
IPC分类号： H01L29/49 , H01L21/28
CPC分类号： H01L29/4236 , H01L21/28114 , H01L21/76224 , H01L29/42376 , H01L29/4966 , H01L29/66553
摘要： A slit recess channel gate is further provided. The slit recess channel gate includes a substrate, a gate dielectric layer, a first conductive layer and a second conductive layer. The substrate has a first trench. The gate dielectric layer is disposed on a surface of the first trench and the first conductive layer is embedded in the first trench. The second conductive layer is disposed on the first conductive layer and aligned with the first conductive layer above the main surface, wherein a bottom surface area of the second conductive layer is substantially smaller than a top surface area of the second conductive layer. The present invention also provides a method of forming the slit recess channel gate.
摘要翻译：还设置狭缝凹槽通道门。狭缝凹槽通道门包括衬底，栅介质层，第一导电层和第二导电层。衬底具有第一沟槽。栅介质层设置在第一沟槽的表面上，第一导电层嵌入第一沟槽中。第二导电层设置在第一导电层上并与主表面上的第一导电层对准，其中第二导电层的底表面积基本上小于第二导电层的顶表面积。本发明还提供了形成狭缝凹槽通道浇口的方法。

9. 发明申请

US20120256256A1 RECESSED GATE TRANSISTOR WITH CYLINDRICAL FINS 有权
标题翻译：具有圆柱形金属的闭合闸门晶体管
公开(公告)号：US20120256256A1
公开(公告)日：2012-10-11
申请号：US13081499
申请日：2011-04-07
申请人： Tieh-Chiang Wu , Yi-Nan Chen , Hsien-Wen Liu
发明人： Tieh-Chiang Wu , Yi-Nan Chen , Hsien-Wen Liu
IPC分类号： H01L29/772
CPC分类号： H01L27/10879 , H01L27/10826 , H01L29/4236 , H01L29/785
摘要： A recessed gate transistor with cylindrical fins is disclosed. The recessed gate transistor is disposed in an active region of a semiconductor substrate. Two isolation regions disposed in the semiconductor substrate to define an active region therebetween. The recessed gate transistor includes a gate structure, a source doping region and a drain doping region. The gate structure has at least three fins forms a concave and convex bottom of the gate structure. The front fin is disposed in one of the two isolation regions, the middle fin is disposed in the active region and a last fin disposed in the other one of the two isolation regions. The front fin and the last fin are both cylindrical. A lower part of the gate structure is M-shaped when view from the source doping region to the drain doping region direction.
摘要翻译：公开了一种具有圆柱形翅片的嵌入式栅极晶体管。凹陷栅极晶体管设置在半导体衬底的有源区中。设置在半导体衬底中以限定它们之间的有源区的两个隔离区。凹陷栅晶体管包括栅极结构，源极掺杂区和漏极掺杂区。栅极结构具有至少三个鳍形成栅极结构的凹凸底部。前鳍设置在两个隔离区域之一中，中间翅片设置在有源区域中，最后一个翅片设置在两个隔离区域中的另一个中。前鳍和最后的鳍都是圆柱形的。当从源极掺杂区域到漏极掺杂区域方向观察时，栅极结构的下部是M形的。

10. 发明授权

US08415729B2 Power device with trenched gate structure and method of fabricating the same 有权
标题翻译：具有沟槽栅极结构的功率器件及其制造方法
公开(公告)号：US08415729B2
公开(公告)日：2013-04-09
申请号：US13081500
申请日：2011-04-07
申请人： Tieh-Chiang Wu , Yi-Nan Chen , Hsien-Wen Liu
发明人： Tieh-Chiang Wu , Yi-Nan Chen , Hsien-Wen Liu
IPC分类号： H01L27/108
CPC分类号： H01L29/7397 , H01L29/4236 , H01L29/66348
摘要： A power device with trenched gate structure, includes: a substrate having a first face and a second face opposing to the first face, a body region of a first conductivity type disposed in the substrate, a base region of a second conductivity type disposed in the body region, a cathode region of the first conductivity type disposed in the base region, an anode region of the second conductivity type disposed in the substrate at the second face a trench disposed in the substrate and extending from the first face into the body region, and the cathode region encompassing the trench, wherein the trench has a wavelike sidewall, a gate structure disposed in the trench and an accumulation region disposed in the body region and along the wavelike sidewall. The wavelike sidewall can increase the base current of the bipolar transistor and increase the performance of the IGBT.
摘要翻译：具有沟槽栅极结构的功率器件包括：具有第一面和与第一面相对的第二面的衬底，设置在衬底中的第一导电类型的主体区域，设置在第二导电类型的基极区域设置在所述基底区域中的所述第一导电类型的阴极区域，所述第二导电类型的阳极区域设置在所述基板的所述第二面处，所述沟槽设置在所述基板中并且从所述第一面延伸到所述主体区域中，以及包围所述沟槽的阴极区域，其中所述沟槽具有波状侧壁，设置在所述沟槽中的栅极结构以及设置在所述体区中并沿着所述波浪形侧壁的堆积区域。波浪形侧壁可以增加双极晶体管的基极电流并增加IGBT的性能。

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