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81. 发明授权

US07986177B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US07986177B2
公开(公告)日：2011-07-26
申请号：US12494355
申请日：2009-06-30
申请人： Ja-Beom Koo , Dong-Suk Shin
发明人： Ja-Beom Koo , Dong-Suk Shin
IPC分类号： H03L7/06
CPC分类号： H03L7/0812 , H03K5/133 , H03K2005/00026 , H03L7/087
摘要： A semiconductor device, includes a clock delay unit configured to include a plurality of delay units connected in series, where the delay amount of each delay unit varies depending on a level of a control voltage, for delaying a source clock to generate a feedback clock and mixing clocks outputted from the respective delay units to generate a frequency multiplication clock, a harmonic lock determination unit configured to determine whether a harmonic lock has occurred based on a frequency difference between the source clock and the frequency multiplication clock, and a control voltage generator configured to adjust a level of the control voltage based on a phase difference between the source clock and the feedback clock and a determination result of the harmonic lock determination unit.
摘要翻译：一种半导体器件，包括：时钟延迟单元，被配置为包括串联连接的多个延迟单元，其中每个延迟单元的延迟量根据控制电压的电平而变化，用于延迟源时钟以产生反馈时钟; 从相应的延迟单元输出的混合时钟以产生倍频时钟;谐波锁定确定单元，被配置为基于源时钟和倍频时钟之间的频率差来确定是否发生了谐波锁定;以及控制电压发生器，基于源时钟和反馈时钟之间的相位差以及谐波锁定确定单元的确定结果来调节控制电压的电平。

82. 发明申请

US20100171182A1 METHOD OF FORMING A SEMICONDUCTOR DEVICE HAVING SELECTIVE STRESS RELAXATION OF ETCH STOP LAYER 审中-公开
标题翻译：形成具有选择性应力松弛的半导体器件的方法
公开(公告)号：US20100171182A1
公开(公告)日：2010-07-08
申请号：US12652426
申请日：2010-01-05
申请人： Dong-Suk Shin , Pan-Kwi Park , Ha-Jin Lim , Joo-Chan Kim
发明人： Dong-Suk Shin , Pan-Kwi Park , Ha-Jin Lim , Joo-Chan Kim
IPC分类号： H01L27/092 , H01L21/3115
CPC分类号： H01L21/823412 , H01L21/26506 , H01L21/26586 , H01L21/823425 , H01L21/823807 , H01L29/7843
摘要： A strained semiconductor device includes a first plurality of transistors spaced with a first gate pitch, a second plurality of transistors spaced with a second gate pitch greater than the first gate pitch, and an etch stop layer disposed on the first and second pluralities of transistors. The etch stop layer between each of the second plurality of transistors has a greater proportion of a stress-altering material than the etch stop layer between each of the first plurality of transistors.
摘要翻译：应变半导体器件包括与第一栅极间隔开的第一多个晶体管，与第一栅极间距大于第二栅极间隔的第二多个晶体管，以及设置在第一和第二多个晶体管上的蚀刻停止层。第二多个晶体管中的每一个之间的蚀刻停止层具有比在第一多个晶体管中的每一个之间的蚀刻停止层更大的应力改变材料的比例。

83. 发明授权

US07732311B2 Methods of manufacturing semiconductor devices 失效
标题翻译：制造半导体器件的方法
公开(公告)号：US07732311B2
公开(公告)日：2010-06-08
申请号：US12213502
申请日：2008-06-20
申请人： Dong-Suk Shin , Joo-Won Lee , Tae-Gyun Kim
发明人： Dong-Suk Shin , Joo-Won Lee , Tae-Gyun Kim
IPC分类号： H01L21/336 , H01L21/26 , H01L21/22 , H01L21/38 , H01L21/44
CPC分类号： H01L29/6659 , H01L21/263 , H01L21/26513 , H01L21/324 , H01L29/6656 , H01L29/7833
摘要： In a method of manufacturing a semiconductor device, a conductive layer pattern may be formed on a substrate. An oxide layer may be formed on the substrate to cover the conductive layer pattern. A diffusion barrier layer may be formed by treating the oxide layer to increase an energy required for a diffusion of impurities. An impurity region may be formed on the substrate by implanting impurities into the conductive layer pattern and a portion of the substrate adjacent to the conductive layer pattern, through the diffusion barrier. The impurities in the conductive layer pattern and the impurity region may be prevented or reduced from diffusing, and therefore, the semiconductor device may have improved performance.
摘要翻译：在制造半导体器件的方法中，可以在衬底上形成导电层图案。可以在衬底上形成氧化物层以覆盖导电层图案。可以通过处理氧化物层以增加杂质扩散所需的能量来形成扩散阻挡层。可以通过在扩散阻挡层中将杂质注入到导电层图案和邻近导电层图案的衬底的一部分而在衬底上形成杂质区。可以防止或减少导电层图案和杂质区域中的杂质的扩散，因此，半导体器件可以具有改进的性能。

84. 发明申请

US20100093166A1 Methods of manufacturing a semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20100093166A1
公开(公告)日：2010-04-15
申请号：US12587857
申请日：2009-10-14
申请人： Tae-Gyun Kim , Dong-Suk Shin
发明人： Tae-Gyun Kim , Dong-Suk Shin
IPC分类号： H01L21/283 , H01L21/31
CPC分类号： H01L21/76224 , H01L21/02315 , H01L21/28211 , H01L21/2822 , H01L21/3115 , H01L29/42368 , H01L29/78
摘要： In a method of manufacturing a semiconductor device, a mask pattern is formed on an active region of a substrate. An exposed portion of the substrate is removed to form a trench in the substrate. A preliminary first insulation layer is formed on a bottom and sidewalls of the trench and the mask pattern. A plasma treatment is performed on the preliminary first insulation layer using fluorine-containing plasma to form a first insulation layer including fluorine. A second insulation layer is formed on the first insulation layer to fill the trench. A thickness of a gate insulation layer adjacent to an upper edge of the trench may be selectively increased, and generation of leakage current may be reduced.
摘要翻译：在制造半导体器件的方法中，在衬底的有源区上形成掩模图案。去除衬底的暴露部分以在衬底中形成沟槽。在沟槽的底部和侧壁和掩模图案上形成初步的第一绝缘层。使用含氟等离子体对预备的第一绝缘层进行等离子体处理，以形成包含氟的第一绝缘层。在第一绝缘层上形成第二绝缘层以填充沟槽。可以选择性地增加与沟槽的上边缘相邻的栅极绝缘层的厚度，并且可以减少漏电流的产生。

85. 发明授权

US07671420B2 Semiconductor devices having faceted channels and methods of fabricating such devices 有权
标题翻译：具有小平面通道的半导体器件和制造这种器件的方法
公开(公告)号：US07671420B2
公开(公告)日：2010-03-02
申请号：US11281599
申请日：2005-11-18
申请人： Dong-Suk Shin , Ueno Tetsuji , Seung-Hwan Lee , Ho Lee , Hwa-Sung Rhee
发明人： Dong-Suk Shin , Ueno Tetsuji , Seung-Hwan Lee , Ho Lee , Hwa-Sung Rhee
IPC分类号： H01L29/76 , H01L27/148 , H01L27/01
CPC分类号： H01L21/823807 , H01L21/823821 , H01L21/823828 , H01L29/045 , H01L29/66795 , H01L29/7851 , H01L29/7853
摘要： Disclosed are processes and techniques for fabricating semiconductor substrates for the manufacture of semiconductor devices, particularly CMOS devices, that include selectively formed, high quality single crystal or monocrystalline surface regions exhibiting different crystal orientations. At least one of the surface regions will incorporate at least one faceted epitaxial semiconductor structure having surfaces that exhibit a crystal orientation different than the semiconductor region on which the faceted epitaxial semiconductor structure is formed. According, the crystal orientation in the channel regions of the NMOS and/or PMOS devices may be configured to improve the relative performance of at least one of the devices and allow corresponding redesign of the semiconductor devices fabricated using such a process.
摘要翻译：公开了用于制造用于制造半导体器件，特别是CMOS器件的半导体衬底的工艺和技术，其包括具有不同晶体取向的选择性地形成的高质量单晶或单晶表面区域。表面区域中的至少一个将结合至少一个具有不同于其上形成有刻面外延半导体结构的半导体区域的晶体取向的表面的分面外延半导体结构。根据，NMOS和/或PMOS器件的沟道区域中的晶体取向可以被配置为改善至少一个器件的相对性能，并允许对使用这种工艺制造的半导体器件进行相应的重新设计。

86. 发明授权

US07611973B2 Methods of selectively forming epitaxial semiconductor layer on single crystalline semiconductor and semiconductor devices fabricated using the same 有权
标题翻译：在使用其制造的单晶半导体和半导体器件上选择性地形成外延半导体层的方法
公开(公告)号：US07611973B2
公开(公告)日：2009-11-03
申请号：US11154236
申请日：2005-06-16
申请人： Dong-Suk Shin , Hwa-Sung Rhee , Tetsuji Ueno , Ho Lee , Seung-Hwan Lee
发明人： Dong-Suk Shin , Hwa-Sung Rhee , Tetsuji Ueno , Ho Lee , Seung-Hwan Lee
IPC分类号： H01L21/20 , H01L21/36
CPC分类号： H01L21/28044 , H01L21/02378 , H01L21/02381 , H01L21/02529 , H01L21/02532 , H01L21/0262 , H01L21/02636 , H01L29/66628 , H01L29/66772
摘要： In methods of selectively forming an epitaxial semiconductor layer on a single crystalline semiconductor and semiconductor devices fabricated using the same, a single crystalline epitaxial semiconductor layer and a non-single crystalline epitaxial semiconductor layer are formed on a single crystalline semiconductor and a non-single crystalline semiconductor pattern respectively, using a main semiconductor source gas and a main etching gas. The non-single crystalline epitaxial semiconductor layer is removed using a selective etching gas. The main gases and the selective etching gas are alternately and repeatedly supplied at least two times to selectively form an elevated single crystalline epitaxial semiconductor layer having a desired thickness only on the single crystalline semiconductor. The selective etching gas suppresses formation of an epitaxial semiconductor layer on the non-single crystalline semiconductor pattern.
摘要翻译：在单晶半导体上选择性地形成外延半导体层的方法和使用其制造的半导体器件的方法中，单晶外延半导体层和非单晶外延半导体层形成在单晶半导体和非单晶半导体图案，分别使用主半导体源气体和主蚀刻气体。使用选择性蚀刻气体去除非单晶外延半导体层。主要气体和选择性蚀刻气体交替地和重复地供应至少两次以选择性地形成仅在单晶半导体上具有期望厚度的升高的单晶外延半导体层。选择性蚀刻气体抑制在非单晶半导体图案上形成外延半导体层。

87. 发明授权

US07598783B2 DLL circuit and method of controlling the same 有权
标题翻译： DLL电路及其控制方法
公开(公告)号：US07598783B2
公开(公告)日：2009-10-06
申请号：US11826401
申请日：2007-07-16
申请人： Dong-Suk Shin , Hyun-Woo Lee , Won-Joo Yun
发明人： Dong-Suk Shin , Hyun-Woo Lee , Won-Joo Yun
IPC分类号： H03L7/06
CPC分类号： H03K5/133 , H03K5/1565 , H03K2005/00052 , H03K2005/00065 , H03L7/0814 , H03L7/087
摘要： A DLL circuit includes a duty ratio detection unit that detects a duty ratio of a rising clock and a duty ratio of a falling clock, thereby outputting a duty ratio detection signal. A correction control unit generates a correction control signal in response to the duty ratio detection signal. A duty ratio correction unit corrects a duty ratio of an internal. clock in response to the correction control signal, thereby outputting a reference clock.
摘要翻译： DLL电路包括占空比检测单元，其检测上升时钟的占空比和下降时钟的占空比，从而输出占空比检测信号。校正控制单元响应于占空比检测信号产生校正控制信号。占空比校正单元校正内部的占空比。响应于校正控制信号，从而输出参考时钟。

88. 发明申请

US20090058483A1 DUTY CYCLE CORRECTING CIRCUIT AND METHOD 审中-公开
标题翻译：占空比校正电路和方法
公开(公告)号：US20090058483A1
公开(公告)日：2009-03-05
申请号：US12200747
申请日：2008-08-28
申请人： Dong-Suk Shin , Hyun-Woo Lee , Won-Joo Yun
发明人： Dong-Suk Shin , Hyun-Woo Lee , Won-Joo Yun
IPC分类号： H03K3/017
CPC分类号： H03K5/1565
摘要： A duty cycle correcting circuit includes a duty detector that detects a duty ratio of an output clock signal to output a duty detection signal, a variable delay unit that outputs a delay clock signal obtained by variably delaying a input signal according to the duty detection signal, and a pulse width modulating unit that generates a first clock signal that is at a high level when both the input clock signal and the delay clock signal are at a high level and generates a second clock signal that is at a high level when any of the input clock signal and the delay clock signal is at a high level, wherein the pulse width modulating unit selectively outputs the first clock signal or the second clock signal as the output clock signal.
摘要翻译：占空比校正电路包括检测输出时钟信号的占空比以输出占空比检测信号的占空比检测器，输出通过根据占空比检测信号可变地延迟输入信号而获得的延迟时钟信号的可变延迟单元，以及脉冲宽度调制单元，当所述输入时钟信号和所述延迟时钟信号都处于高电平时，产生处于高电平的第一时钟信号，并且当所述第二时钟信号为输入时钟信号和延迟时钟信号处于高电平，其中脉冲宽度调制单元选择性地输出第一时钟信号或第二时钟信号作为输出时钟信号。

89. 发明申请

US20080166854A1 SEMICONDUCTOR DEVICES INCLUDING TRENCH ISOLATION STRUCTURES AND METHODS OF FORMING THE SAME 审中-公开
标题翻译：包括耐热隔离结构的半导体器件及其形成方法
公开(公告)号：US20080166854A1
公开(公告)日：2008-07-10
申请号：US12052257
申请日：2008-03-20
申请人： Dong-Suk Shin , Tae-Gyun Kim
发明人： Dong-Suk Shin , Tae-Gyun Kim
IPC分类号： H01L21/76
CPC分类号： H01L21/76229 , H01L21/76232
摘要： Trench isolation methods include forming a first trench and a second trench in a semiconductor substrate. The second trench has a larger width than the first trench. A tower isolation layer is formed on the semiconductor substrate using a first high density plasma deposition process. The lower isolation layer has a first thickness on an upper sidewall of the first trench and a second thickness on an upper sidewall of the second trench. The second thickness is greater than the first thickness. An upper isolation layer is formed on the semiconductor substrate including the lower isolation layer using a second high density plasma deposition process, different from the first high density plasma deposition process. The second high density plasma deposition process includes an H2 treatment process.
摘要翻译：沟槽隔离方法包括在半导体衬底中形成第一沟槽和第二沟槽。第二沟槽具有比第一沟槽更大的宽度。使用第一高密度等离子体沉积工艺在半导体衬底上形成塔隔离层。下隔离层在第一沟槽的上侧壁上具有第一厚度，在第二沟槽的上侧壁上具有第二厚度。第二厚度大于第一厚度。使用不同于第一高密度等离子体沉积工艺的第二高密度等离子体沉积工艺在包括下隔离层的半导体衬底上形成上隔离层。第二高密度等离子体沉积工艺包括H 2 N 2处理工艺。

90. 发明申请

US20070158704A1 Semiconductor device and methods of fabricating the same 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20070158704A1
公开(公告)日：2007-07-12
申请号：US11525024
申请日：2006-09-22
申请人： Ki-Chul Kim , Dong-Suk Shin , Yong-Kuk Jeong
发明人： Ki-Chul Kim , Dong-Suk Shin , Yong-Kuk Jeong
IPC分类号： H01L29/76 , H01L21/31
CPC分类号： H01L21/823807 , H01L21/823864
摘要： A semiconductor device having an etch stop layer and a method of fabricating the same are provided. The semiconductor device may include a substrate and a first gate electrode formed on the substrate. An auxiliary spacer may be formed on the sidewall of the first gate electrode. An etch stop layer may be formed on the substrate having the auxiliary spacer. The etch stop layer and the auxiliary spacer may be formed of a material having a same stress property.
摘要翻译：提供了具有蚀刻停止层的半导体器件及其制造方法。半导体器件可以包括形成在衬底上的衬底和第一栅电极。可以在第一栅电极的侧壁上形成辅助间隔物。可以在具有辅助间隔物的衬底上形成蚀刻停止层。蚀刻停止层和辅助间隔物可以由具有相同应力特性的材料形成。

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