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1. 发明授权

US07808043B2 Semiconductor device and methods of fabricating the same including forming spacers and etch stop layers with stress properties 有权
标题翻译：半导体器件及其制造方法包括形成具有应力特性的间隔物和蚀刻停止层
公开(公告)号：US07808043B2
公开(公告)日：2010-10-05
申请号：US11525024
申请日：2006-09-22
申请人： Ki-Chul Kim , Dong-Suk Shin , Yong-Kuk Jeong
发明人： Ki-Chul Kim , Dong-Suk Shin , Yong-Kuk Jeong
IPC分类号： H01L29/74 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119 , H01L21/8238 , H01L21/4763
CPC分类号： H01L21/823807 , H01L21/823864
摘要： A semiconductor device having an etch stop layer and a method of fabricating the same are provided. The semiconductor device may include a substrate and a first gate electrode formed on the substrate. An auxiliary spacer may be formed on the sidewall of the first gate electrode. An etch stop layer may be formed on the substrate having the auxiliary spacer. The etch stop layer and the auxiliary spacer may be formed of a material having a same stress property.
摘要翻译：提供了具有蚀刻停止层的半导体器件及其制造方法。半导体器件可以包括形成在衬底上的衬底和第一栅电极。可以在第一栅电极的侧壁上形成辅助间隔物。可以在具有辅助间隔物的衬底上形成蚀刻停止层。蚀刻停止层和辅助间隔物可以由具有相同应力特性的材料形成。

2. 发明申请

US20070158704A1 Semiconductor device and methods of fabricating the same 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20070158704A1
公开(公告)日：2007-07-12
申请号：US11525024
申请日：2006-09-22
申请人： Ki-Chul Kim , Dong-Suk Shin , Yong-Kuk Jeong
发明人： Ki-Chul Kim , Dong-Suk Shin , Yong-Kuk Jeong
IPC分类号： H01L29/76 , H01L21/31
CPC分类号： H01L21/823807 , H01L21/823864
摘要： A semiconductor device having an etch stop layer and a method of fabricating the same are provided. The semiconductor device may include a substrate and a first gate electrode formed on the substrate. An auxiliary spacer may be formed on the sidewall of the first gate electrode. An etch stop layer may be formed on the substrate having the auxiliary spacer. The etch stop layer and the auxiliary spacer may be formed of a material having a same stress property.
摘要翻译：提供了具有蚀刻停止层的半导体器件及其制造方法。半导体器件可以包括形成在衬底上的衬底和第一栅电极。可以在第一栅电极的侧壁上形成辅助间隔物。可以在具有辅助间隔物的衬底上形成蚀刻停止层。蚀刻停止层和辅助间隔物可以由具有相同应力特性的材料形成。

3. 发明申请

US20110306198A1 METHOD OF FABRICATING SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 审中-公开
标题翻译：制造半导体集成电路器件的方法
公开(公告)号：US20110306198A1
公开(公告)日：2011-12-15
申请号：US13157615
申请日：2011-06-10
申请人： Yong-Kuk Jeong , Dong-Suk Shin , Jong-Hun Kim , Hyun-Kwan Yu , Ki-eun Kim
发明人： Yong-Kuk Jeong , Dong-Suk Shin , Jong-Hun Kim , Hyun-Kwan Yu , Ki-eun Kim
IPC分类号： H01L21/28
CPC分类号： H01L29/7833 , H01L21/823412 , H01L21/823425 , H01L29/6653 , H01L29/6659 , H01L29/7843
摘要： A method of fabricating a semiconductor integrated circuit device includes forming a gate pattern on a semiconductor substrate, the gate pattern having a gate insulation film and a gate electrode. A spacer is formed on sidewalls of the gate pattern. A silicide layer is formed by a silicide process on at least one portion of the semiconductor substrate exposed by the gate pattern and the spacer, the silicide layer being formed using a silicide process. A stress buffer layer is formed on a resultant structure having the silicide layer. A stress film is formed on the stress buffer layer.
摘要翻译：一种制造半导体集成电路器件的方法包括在半导体衬底上形成栅极图案，栅极图案具有栅极绝缘膜和栅电极。在栅极图案的侧壁上形成间隔物。硅化物层通过硅化物工艺在由栅极图案和间隔物暴露的半导体衬底的至少一部分上形成，硅化物层使用硅化物工艺形成。在具有硅化物层的所得结构上形成应力缓冲层。在应力缓冲层上形成应力膜。

4. 发明授权

US08951853B1 Method of forming semiconductor device using Si-H rich silicon nitride layer 有权
标题翻译：使用富Si硅氮化物层形成半导体器件的方法
公开(公告)号：US08951853B1
公开(公告)日：2015-02-10
申请号：US12659474
申请日：2010-03-10
申请人： Pan-Kwi Park , Dong-Suk Shin , Yong-Kuk Jeong , Dong-Hyun Roh , Ha-Jin Lim
发明人： Pan-Kwi Park , Dong-Suk Shin , Yong-Kuk Jeong , Dong-Hyun Roh , Ha-Jin Lim
IPC分类号： H01L21/8238
CPC分类号： H01L21/823807 , H01L29/6656 , H01L29/6659 , H01L29/7843 , H01L29/7847
摘要： A method of forming a semiconductor device includes forming a gate electrode and source/drain regions in a semiconductor substrate, forming a first capping nitride layer covering the gate electrode and the source/drain regions, the first capping nitride layer including a Si—H rich SiN layer, annealing the semiconductor substrate having the first capping nitride layer, and removing the first capping nitride layer.
摘要翻译：形成半导体器件的方法包括在半导体衬底中形成栅电极和源/漏区，形成覆盖栅电极和源/漏区的第一覆盖氮化物层，第一覆盖氮化物层包括富Si-H SiN层，退火具有第一覆盖氮化物层的半导体衬底，以及去除第一覆盖氮化物层。

5. 发明申请

US20070059898A1 Semiconductor devices including trench isolation structures and methods of forming the same 审中-公开
标题翻译：包括沟槽隔离结构的半导体器件及其形成方法
公开(公告)号：US20070059898A1
公开(公告)日：2007-03-15
申请号：US11393546
申请日：2006-03-30
申请人： Dong-Suk Shin , Seung-Jin Lee , Yong-Kuk Jeong , Ki-Kwan Park
发明人： Dong-Suk Shin , Seung-Jin Lee , Yong-Kuk Jeong , Ki-Kwan Park
IPC分类号： H01L21/76
CPC分类号： H01L21/76229 , H01L21/76232
摘要： Trench isolation methods include forming a first trench and a second trench, having a larger width than the first trench, in a semiconductor substrate. A lower isolation layer is formed having a first thickness on an upper sidewall of the first trench and a second thickness on an upper sidewall of the second trench using a first high density plasma deposition process, the second thickness being greater than the first thickness. An upper isolation layer is formed on the semiconductor substrate including the lower isolation layer using a second high density plasma deposition process, different from the first high density plasma deposition process. The first and second high density plasma deposition processes may be chemical vapor deposition processes. Semiconductor devices including a trench isolation structure are also provided.
摘要翻译：沟槽隔离方法包括在半导体衬底中形成具有比第一沟槽更大的宽度的第一沟槽和第二沟槽。使用第一高密度等离子体沉积工艺在第一沟槽的上侧壁上形成具有第一厚度的第一厚度和在第二沟槽的上侧壁上的第二厚度的下隔离层，第二厚度大于第一厚度。使用不同于第一高密度等离子体沉积工艺的第二高密度等离子体沉积工艺在包括下隔离层的半导体衬底上形成上隔离层。第一和第二高密度等离子体沉积工艺可以是化学气相沉积工艺。还提供了包括沟槽隔离结构的半导体器件。

6. 发明授权

US07981784B2 Methods of manufacturing a semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US07981784B2
公开(公告)日：2011-07-19
申请号：US12381175
申请日：2009-03-09
申请人： Dong-Suk Shin , Ki-Chul Kim , Jung-Deog Lee
发明人： Dong-Suk Shin , Ki-Chul Kim , Jung-Deog Lee
IPC分类号： H01L21/00
CPC分类号： H01L21/823807 , H01L21/823814 , H01L21/823864 , H01L29/7843
摘要： Isolation regions are formed on a substrate to define an active region. A gate electrode is formed on the active region. A spacer structure is formed on a sidewall of the gate electrode. A gate silicide layer is formed on the gate electrode and a source/drain silicide layer is formed on the active region adjacent to the gate electrode. An upper portion of the gate silicide layer and a portion of the spacer structure are simultaneously removed to form a spacer structure pattern and a gate silicide layer pattern. A stress layer is formed to cover the gate electrode and spacer structure pattern.
摘要翻译：隔离区形成在衬底上以限定有源区。在有源区上形成栅电极。间隔结构形成在栅电极的侧壁上。在栅电极上形成栅极硅化物层，并且在与栅电极相邻的有源区上形成源极/漏极硅化物层。栅极硅化物层的上部和间隔物结构的一部分被同时去除以形成间隔物结构图案和栅极硅化物层图案。形成应力层以覆盖栅电极和间隔结构图案。

7. 发明申请

US20090227082A1 Methods of manufcturing a semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20090227082A1
公开(公告)日：2009-09-10
申请号：US12381175
申请日：2009-03-09
申请人： Dong-Suk Shin , Ki-Chul Kim , Jung-Deog Lee
发明人： Dong-Suk Shin , Ki-Chul Kim , Jung-Deog Lee
IPC分类号： H01L21/76
CPC分类号： H01L21/823807 , H01L21/823814 , H01L21/823864 , H01L29/7843
摘要： Isolation regions are formed on a substrate to define an active region. A gate electrode is formed on the active region. A spacer structure is formed on a sidewall of the gate electrode. A gate silicide layer is formed on the gate electrode and a source/drain silicide layer is formed on the active region adjacent to the gate electrode. An upper portion of the gate silicide layer and a portion of the spacer structure are simultaneously removed to form a spacer structure pattern and a gate silicide layer pattern. A stress layer is formed to cover the gate electrode and spacer structure pattern.
摘要翻译：隔离区形成在衬底上以限定有源区。在有源区上形成栅电极。间隔结构形成在栅电极的侧壁上。在栅电极上形成栅极硅化物层，并且在与栅电极相邻的有源区上形成源极/漏极硅化物层。栅极硅化物层的上部和间隔物结构的一部分被同时去除以形成间隔物结构图案和栅极硅化物层图案。形成应力层以覆盖栅电极和间隔结构图案。

8. 发明申请

US20080073713A1 Method of fabricating semiconductor device having stress enhanced MOS transistor and semiconductor device fabricated thereby 审中-公开
标题翻译：制造具有应力增强型MOS晶体管的半导体器件及其制造的半导体器件的方法
公开(公告)号：US20080073713A1
公开(公告)日：2008-03-27
申请号：US11785994
申请日：2007-04-23
申请人： Ki-Chul Kim , Dong-Suk Shin
发明人： Ki-Chul Kim , Dong-Suk Shin
IPC分类号： H01L27/092 , H01L21/8238
CPC分类号： H01L21/823807 , H01L21/823864 , H01L29/665 , H01L29/6653 , H01L29/6659 , H01L29/7833 , H01L29/7843
摘要： A method of fabricating a semiconductor device having a stress enhanced MOS transistor is provided. A MOS transistor may be formed in a desired, or alternatively, a predetermined region of a semiconductor substrate. A first sacrificial pattern, formed over the source and drain regions of a MOS transistor, may expose sidewall spacers and cover the upper region of the gate pattern. Thinner spacers may be formed by etching the exposed sidewall spacers using the first sacrificial pattern as an etch mask. A stress liner may be formed over the MOS transistor having the thinner spacers.
摘要翻译：提供一种制造具有应力增强型MOS晶体管的半导体器件的方法。 MOS晶体管可以形成在半导体衬底的期望或替代地预定区域中。形成在MOS晶体管的源极和漏极区域上的第一牺牲图案可以暴露侧壁间隔物并覆盖栅极图案的上部区域。可以通过使用第一牺牲图案作为蚀刻掩模蚀刻暴露的侧壁间隔物来形成更薄的间隔物。可以在具有较薄间隔物的MOS晶体管上形成应力衬垫。

9. 发明申请

US20160197188A1 SEMICONDUCTOR DEVICE HAVING EMBEDDED STRAIN-INDUCING PATTERN AND METHOD OF FORMING THE SAME 有权
公开(公告)号：US20160197188A1
公开(公告)日：2016-07-07
申请号：US15071502
申请日：2016-03-16
申请人： Dong-Suk Shin , Myung-Sun Kim , Seong-Jin Nam , Pan-Kwi Park , Hoi-Sung Chung , Nae-In Lee
发明人： Dong-Suk Shin , Myung-Sun Kim , Seong-Jin Nam , Pan-Kwi Park , Hoi-Sung Chung , Nae-In Lee
IPC分类号： H01L29/78 , H01L29/51 , H01L27/11 , H01L29/45 , H01L27/088 , H01L29/08 , H01L29/165
CPC分类号： H01L27/1104 , H01L21/02532 , H01L21/02636 , H01L21/28247 , H01L21/30604 , H01L21/823807 , H01L21/823814 , H01L27/088 , H01L27/1116 , H01L29/0847 , H01L29/1083 , H01L29/16 , H01L29/161 , H01L29/165 , H01L29/45 , H01L29/513 , H01L29/665 , H01L29/6653 , H01L29/6656 , H01L29/66575 , H01L29/6659 , H01L29/66636 , H01L29/7827 , H01L29/7833 , H01L29/7834 , H01L29/7845 , H01L29/7848 , H01L29/785 , H01L29/78696
摘要： In a semiconductor device, a first active region has a first Σ-shape, and the second active region has a second Σ-shape. When a line that is perpendicular to the substrate and passes a side surface of a first gate electrode in the first region is defined as a first vertical line, when a line that is perpendicular to the substrate and passes a side surface of a second gate electrode in the second region is defined as a second vertical line, when a shortest distance between the first vertical line and the first trench is defined as a first horizontal distance, and when a shortest distance between the second vertical line and the second trench is defined as a second horizontal distance, a difference between the first horizontal distance and the second horizontal distance is equal to or less than 1 nm.

10. 发明授权

US08637373B2 Transistors and methods of manufacturing the same 有权
标题翻译：晶体管及其制造方法
公开(公告)号：US08637373B2
公开(公告)日：2014-01-28
申请号：US13410475
申请日：2012-03-02
申请人： Hoi-Sung Chung , Dong-Suk Shin , Dong-Hyuk Kim , Myung-Sun Kim
发明人： Hoi-Sung Chung , Dong-Suk Shin , Dong-Hyuk Kim , Myung-Sun Kim
IPC分类号： H01L21/336
CPC分类号： H01L21/823807 , H01L21/30608 , H01L21/823814 , H01L21/823864 , H01L29/165 , H01L29/6656 , H01L29/66575 , H01L29/66636 , H01L29/78 , H01L29/7848
摘要： In a method of manufacturing a transistor, a gate structure is formed on a substrate including silicon. An upper portion of the substrate adjacent to the gate structure is etched to form a first recess in the substrate. A preliminary first epitaxial layer including silicon-germanium is formed in the first recess. An upper portion of the preliminary first epitaxial layer is etched to form a second recess on the preliminary first epitaxial layer. In addition, a portion of the preliminary first epitaxial layer adjacent to the second recess is etched to thereby transform the preliminary first epitaxial layer into a first epitaxial layer. A second epitaxial layer including silicon-germanium is formed in the second recess located on the first epitaxial layer.
摘要翻译：在制造晶体管的方法中，在包括硅的衬底上形成栅极结构。蚀刻与栅极结构相邻的衬底的上部，以在衬底中形成第一凹部。在第一凹部中形成包括硅 - 锗的初步的第一外延层。蚀刻初步第一外延层的上部以在初步第一外延层上形成第二凹槽。此外，蚀刻与第二凹槽相邻的初步第一外延层的一部分，从而将初步第一外延层转变为第一外延层。在位于第一外延层上的第二凹槽中形成包括硅 - 锗的第二外延层。

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