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81. 发明授权

US07354822B2 Method of forming a MOSFET with dual work function materials 有权
标题翻译：用双功能材料形成MOSFET的方法
公开(公告)号：US07354822B2
公开(公告)日：2008-04-08
申请号：US11553072
申请日：2006-10-26
申请人： Xiangdong Chen , Geng Wang , Yujun Li , Qiqing C. Ouyang
发明人： Xiangdong Chen , Geng Wang , Yujun Li , Qiqing C. Ouyang
IPC分类号： H01L21/8242
CPC分类号： H01L29/66181 , H01L27/10864
摘要： A vertical pass transistor used in a DRAM cell for maintaining a low total leakage current and providing adequate drive current is described together with a method of fabricating such a device. The transistor gate is engineered in lieu of the channel. The vertical pass transistor for the DRAM cell incorporates two gate materials having different work functions. The gate material near the storage node is n-type doped polysilicon. The gate material near the bit line diffusion is made of silicide or metal having a higher work function than the n-polysilicon. The novel device structure shows several advantages: the channel doping is reduced while maintaining a high Vt and a low sub-threshold leakage current; the carrier mobility improves with the reduced channel doping; the body effect of the device is reduced which improves the write back current; and the sub-threshold swing is reduced because of the low channel doping.
摘要翻译：在DRAM单元中使用的用于保持低总漏电流并提供足够的驱动电流的垂直传输晶体管与制造这种器件的方法一起被描述。晶体管栅极被设计代替通道。用于DRAM单元的垂直传输晶体管包括具有不同功函数的两个栅极材料。存储节点附近的栅极材料为n型掺杂多晶硅。位线扩散附近的栅极材料由具有比n-多晶硅更高的功函数的硅化物或金属制成。该新颖的器件结构显示出几个优点：沟道掺杂减少，同时保持高Vt和低的亚阈值漏电流; 载流子迁移率随着沟道掺杂的降低而提高; 减少了器件的体效，提高了回写电流; 并且由于低通道掺杂，子阈值摆幅减小。

82. 发明申请

US20080048269A1 METHOD OF FABRICATING STRUCTURE FOR INTEGRATED CIRCUIT INCORPORATING HYBRID ORIENTATION TECHNOLOGY AND TRENCH ISOLATION REGIONS 审中-公开
标题翻译：整合电路结合混合方向技术与热分解区域的方法
公开(公告)号：US20080048269A1
公开(公告)日：2008-02-28
申请号：US11467325
申请日：2006-08-25
申请人： Xiangdong Chen , Yong Meng Lee
发明人： Xiangdong Chen , Yong Meng Lee
IPC分类号： H01L29/94
CPC分类号： H01L21/823807 , H01L21/823878 , H01L27/0922
摘要： An embodiment of the present invention discloses a method of fabricating a structure for an integrated circuit incorporating hybrid orientation technology (HOT) and trench isolation regions. The structure of the integrated circuit comprising: a substrate with a first silicon layer of a first crystalline orientation and a second silicon layer, of a second crystalline orientation different from the first crystalline orientation, disposed on the first silicon layer; a dielectric layer on the substrate; a first silicon active trench region, having first crystalline orientation, extending to the first silicon layer; a second silicon active trench region, having the second crystalline orientation, extending to the second silicon layer, the first silicon active region electrically isolated from the second silicon active region by a portion of the dielectric layer; a first transistor on the first silicon active region; and a second transistor on the second silicon active region.
摘要翻译：本发明的实施例公开了一种制造用于集成混合取向技术（HOT）和沟槽隔离区域的集成电路的结构的方法。所述集成电路的结构包括：设置在所述第一硅层上的具有第一晶体取向的第一硅层和与所述第一晶体取向不同的第二晶体取向的第二硅层的衬底; 基底上的电介质层; 具有第一晶体取向的第一硅有源沟槽区，延伸到第一硅层; 具有第二晶体取向的第二硅有源沟槽区延伸到第二硅层，第一硅有源区通过介电层的一部分与第二硅有源区电隔离; 在第一硅有源区上的第一晶体管; 以及在第二硅有源区上的第二晶体管。

83. 发明申请

US20070202654A1 SPACER AND PROCESS TO ENHANCE THE STRAIN IN THE CHANNEL WITH STRESS LINER 失效
标题翻译：通过应力衬垫增强通道中的应变的间隔和过程
公开(公告)号：US20070202654A1
公开(公告)日：2007-08-30
申请号：US11307928
申请日：2006-02-28
申请人： Atul Ajmera , Christopher Baiocco , Xiangdong Chen , Wenzhi Gao , Young Way Teh
发明人： Atul Ajmera , Christopher Baiocco , Xiangdong Chen , Wenzhi Gao , Young Way Teh
IPC分类号： H01L21/336
CPC分类号： H01L29/7843 , H01L29/665 , H01L29/6653 , H01L29/6659 , H01L29/7833
摘要： Process for enhancing strain in a channel with a stress liner, spacer, process for forming integrated circuit and integrated circuit. A first spacer composed of an first oxide and first nitride layer is applied to a gate electrode on a substrate, and a second spacer composed of a second oxide and second nitride layer is applied. Deep implanting of source and drain in the substrate occurs, and removal of the second nitride, second oxide, and first nitride layers.
摘要翻译：通过应力衬垫，间隔物，集成电路形成工艺和集成电路增强通道中的应变的方法。将由第一氧化物和第一氮化物层构成的第一间隔物施加到基板上的栅电极，并施加由第二氧化物和第二氮化物层构成的第二间隔物。在衬底中深入植入源极和漏极，并且去除第二氮化物，第二氧化物和第一氮化物层。

84. 发明授权

US07102914B2 Gate controlled floating well vertical MOSFET 失效
标题翻译：门控浮动阱垂直MOSFET
公开(公告)号：US07102914B2
公开(公告)日：2006-09-05
申请号：US10708381
申请日：2004-02-27
申请人： Xiangdong Chen , Dureseti Chidambarrao , Geng Wang
发明人： Xiangdong Chen , Dureseti Chidambarrao , Geng Wang
IPC分类号： G11C11/24 , G11C11/34
CPC分类号： H01L27/10864 , H01L27/0214 , H01L27/10841
摘要： A novel transistor structure for a DRAM cell includes two deep trenches, one trench including a vertical storage cell for storing the data and the second trench including a vertical control cell for controlling the p-well voltage, which, in effect, places part of the p-well in a floating condition thus decreasing the threshold voltage as compared to when the vertical pass transistor is in an off-state. This enables the transistor to exhibit increased gate overdrive and drive current during an active wordline voltage commonly applied to both gates of the storage and control cells.
摘要翻译：用于DRAM单元的新型晶体管结构包括两个深沟槽，一个沟槽包括用于存储数据的垂直存储单元，第二沟槽包括用于控制p阱电压的垂直控制单元，其实际上将部分 p阱处于浮置状态，从而与垂直传输晶体管处于截止状态时相比降低阈值电压。这使得晶体管能够在通常施加到存储和控制单元的两个栅极的有效字线电压期间表现出增加的栅极过驱动和驱动电流。

85. 发明申请

US20060163631A1 Vertical MOSFET with dual work function materials 失效
标题翻译：具有双功能材料的垂直MOSFET
公开(公告)号：US20060163631A1
公开(公告)日：2006-07-27
申请号：US10622477
申请日：2003-07-18
申请人： Xiangdong Chen , Geng Wang , Yujun Li , Qiqing Ouyang
发明人： Xiangdong Chen , Geng Wang , Yujun Li , Qiqing Ouyang
IPC分类号： H01L29/94
CPC分类号： H01L29/66181 , H01L27/10864
摘要： A vertical pass transistor used in a DRAM cell for maintaining a low total leakage current and providing adequate drive current is described together with a method of fabricating such a device. The transistor gate is engineered in lieu of the channel. The vertical pass transistor for the DRAM cell incorporates two gate materials having different work functions. The gate material near the storage node is n-type doped polysilicon. The gate material near the bit line diffusion is made of silicide or metal having a higher work function than the n-polysilicon. The novel device structure shows several advantages: the channel doping is reduced while maintaining a high Vt and a low sub-threshold leakage current; the carrier mobility improves with the reduced channel doping; the body effect of the device is reduced which improves the write back current; and the sub-threshold swing is reduced because of the low channel doping.
摘要翻译：在DRAM单元中使用的用于保持低总漏电流并提供足够的驱动电流的垂直传输晶体管与制造这种器件的方法一起被描述。晶体管栅极被设计代替通道。用于DRAM单元的垂直传输晶体管包括具有不同功函数的两个栅极材料。存储节点附近的栅极材料为n型掺杂多晶硅。位线扩散附近的栅极材料由具有比n-多晶硅更高的功函数的硅化物或金属制成。该新颖的器件结构显示出几个优点：沟道掺杂减少，同时保持高Vt和低的亚阈值漏电流; 载流子迁移率随着沟道掺杂的降低而提高; 减少了器件的体效，提高了回写电流; 并且由于低通道掺杂，子阈值摆幅减小。

86. 发明授权

US07045873B2 Dynamic threshold voltage MOSFET on SOI 有权
标题翻译： SOI上的动态阈值电压MOSFET
公开(公告)号：US07045873B2
公开(公告)日：2006-05-16
申请号：US10728750
申请日：2003-12-08
申请人： Xiangdong Chen , Dureseti Chidambarrao , Geng Wang
发明人： Xiangdong Chen , Dureseti Chidambarrao , Geng Wang
IPC分类号： H01L29/00
CPC分类号： H01L29/783
摘要： Provision of a body control contact adjacent a transistor and between the transistor and a contact to the substrate or well in which the transistor is formed allows connection and disconnection of the substrate of the transistor to and from a zero (ground) or substantially arbitrary low voltage in accordance with control signals applied to the gate of the transistor to cause the transistor to exhibit a variable threshold which maintains good performance at low supply voltages and reduces power consumption/dissipation which is particularly advantageous in portable electronic devices. Floating body effects (when the transistor substrate in disconnected from a voltage source in the “on” state) are avoided since the substrate is discharged when the transistor is switched to the “off” state. The transistor configuration can be employed with both n-type and p-type transistors which may be in complementary pairs.
摘要翻译：提供与晶体管相邻并且晶体管与形成晶体管的衬底或阱的接触之间的身体控制接触允许晶体管的衬底与零（接地）或基本上任意的低电压的连接和断开根据施加到晶体管的栅极的控制信号，使晶体管呈现可变阈值，其在低电源电压下保持良好的性能，并降低了在便携式电子设备中特别有利的功耗/耗散。避免浮体效应（当晶体管基板与电压源处于“导通”状态断开时），因为当晶体管切换到“关闭”状态时，衬底被放电。晶体管配置可以与可以互补对的n型和p型晶体管一起使用。

87. 发明申请

US20050062161A1 CONDUCTOR LINE STRUCTURE AND METHOD FOR IMPROVED BORDERLESS CONTACT PROCESS TOLERANCE 失效
标题翻译：导体线结构和改进的无边界接触过程公差的方法
公开(公告)号：US20050062161A1
公开(公告)日：2005-03-24
申请号：US10605308
申请日：2003-09-22
申请人： Xiangdong Chen , Li Wang
发明人： Xiangdong Chen , Li Wang
IPC分类号： H01L21/60 , H01L21/8242 , H01L23/485 , H01L23/522 , H01L23/48
CPC分类号： H01L27/10888 , H01L21/76897 , H01L23/485 , H01L27/10861 , H01L27/10873 , H01L2924/0002 , H01L2924/00
摘要： A structure and method are provided for a conductor line stack of an integrated circuit. The conductor line stack includes a layer of a first material such as heavily doped polysilicon or a metal silicide. A layer of a second material such as a metal is formed over the layer of first material, the layer of second material having an upper portion and a lower portion. A pair of first spacers is disposed on sidewalls of the upper portion, wherein the lower portion has width defined by a combined width of the upper portion and the pair of first spacers. A pair of second spacers is formed on sidewalls of the first spacers, the lower portion and the layer of first material. The conductor line stack structure is well adapted for formation of a borderless bitline contact in contact therewith.
摘要翻译：为集成电路的导线堆叠提供了一种结构和方法。导线堆叠包括第一材料层，例如重掺杂多晶硅或金属硅化物。在第一材料层上形成诸如金属的第二材料层，第二材料层具有上部和下部。一对第一间隔件设置在上部的侧壁上，其中下部具有由上部和第一对间隔件的组合宽度限定的宽度。在第一间隔件，下部和第一材料层的侧壁上形成一对第二间隔件。导体线堆叠结构很好地适于形成与其接触的无边界位线接触。

88. 发明授权

US09548251B2 Semiconductor interposer having a cavity for intra-interposer die 有权
标题翻译：具有用于内插器模腔的腔室的半导体插入器
公开(公告)号：US09548251B2
公开(公告)日：2017-01-17
申请号：US13349045
申请日：2012-01-12
申请人： Rezaur Rahman Khan , Sam Ziqun Zhao , Pieter Vorenkamp , Kevin Kunzhong Hu , Sampath K. V. Karikalan , Xiangdong Chen
发明人： Rezaur Rahman Khan , Sam Ziqun Zhao , Pieter Vorenkamp , Kevin Kunzhong Hu , Sampath K. V. Karikalan , Xiangdong Chen
IPC分类号： H01L23/48 , H01L23/13 , H01L25/065 , H01L23/498
CPC分类号： H01L23/13 , H01L23/49827 , H01L23/49833 , H01L25/0657 , H01L2224/14181 , H01L2224/16145 , H01L2224/16225 , H01L2224/16235 , H01L2224/17181 , H01L2224/32225 , H01L2224/73253 , H01L2225/06513 , H01L2225/06517 , H01L2225/06548 , H01L2225/06572 , H01L2924/15151 , H01L2924/15153 , H01L2924/15311 , H01L2924/157
摘要： A semiconductor package may include a substrate, and a semiconductor interposer having a cavity and a plurality of through semiconductor vias. The semiconductor interposer is situated over the substrate. An intra-interposer die is disposed within the cavity of the semiconductor interposer. A thermally conductive adhesive is disposed within the cavity and contacts the intra-interposer die. Additionally, a top die is situated over the semiconductor interposer. In one implementation, the semiconductor interposer is a silicon interposer. In another implementation, the semiconductor interposer is flip-chip mounted to the substrate such that the intra-interposer die disposed within the cavity faces the substrate. In yet another implementation, the cavity in the semiconductor interposer may extend from a top surface of the semiconductor interposer to a bottom surface of the semiconductor interposer and a thermal interface material may be disposed between the intra-interposer die and the substrate.
摘要翻译：半导体封装可以包括衬底和具有空腔和多个通孔半导体通孔的半导体插入器。半导体插入器位于衬底上。插入式管芯设置在半导体插入器的空腔内。导热粘合剂设置在空腔内并与内插器模具接触。此外，顶部管芯位于半导体插入器上方。在一个实现中，半导体插入器是硅插入器。在另一个实施方式中，将半导体插入器倒装芯片安装到基板上，使得设置在空腔内的内插器芯片面向基板。在又一实施方案中，半导体插入器中的空腔可以从半导体插入器的顶表面延伸到半导体插入器的底表面，并且热界面材料可以设置在内插器管芯和衬底之间。

89. 发明授权

US09129856B2 Method for efficiently fabricating memory cells with logic FETs and related structure 有权
标题翻译：用逻辑FET和相关结构有效地制造存储单元的方法
公开(公告)号：US09129856B2
公开(公告)日：2015-09-08
申请号：US13179248
申请日：2011-07-08
申请人： Wei Xia , Xiangdong Chen
发明人： Wei Xia , Xiangdong Chen
IPC分类号： H01L27/115 , H01L21/8238
CPC分类号： H01L27/11534 , H01L21/823842
摘要： According to one exemplary embodiment, a method for concurrently fabricating a memory region with a logic region in a common substrate includes forming a lower dielectric segment in the common substrate in the memory and logic regions. The method also includes forming a polysilicon segment over the lower dielectric segment in the memory region, while concurrently forming a sacrificial polysilicon segment over the lower dielectric segment in the logic region. Furthermore, the method includes removing from the logic region the lower dielectric segment and the sacrificial polysilicon segment. The method additionally includes forming a high-k segment in the logic region over the common substrate, and in the memory region over the polysilicon segment and forming a metal segment over the high-k segment in the logic and memory regions. An exemplary structure achieved by the described exemplary method is also disclosed.
摘要翻译：根据一个示例性实施例，用于同时制造具有公共衬底中的逻辑区域的存储区域的方法包括在存储器和逻辑区域中的公共衬底中形成下部介电段。该方法还包括在存储器区域中的下介电段上形成多晶硅段，同时在逻辑区域中的下介电段上同时形成牺牲多晶硅段。此外，该方法包括从逻辑区域去除下介电段和牺牲多晶硅段。该方法还包括在公共衬底上的逻辑区域中形成高k区段，并在多晶硅区段上的存储区域中形成高k区段，并在逻辑和存储区域中的高k区段上形成金属区段。还公开了通过描述的示例性方法实现的示例性结构。

90. 发明授权

US08748277B2 Method for fabricating a MOS transistor with reduced channel length variation 有权
标题翻译：具有减小的沟道长度变化的MOS晶体管的制造方法
公开(公告)号：US08748277B2
公开(公告)日：2014-06-10
申请号：US13613520
申请日：2012-09-13
申请人： Xiangdong Chen , Wei Xia , Henry Kuo-Shun Chen
发明人： Xiangdong Chen , Wei Xia , Henry Kuo-Shun Chen
IPC分类号： H01L21/336
CPC分类号： H01L29/0878 , H01L21/26586 , H01L29/0847 , H01L29/1045 , H01L29/1083 , H01L29/66537 , H01L29/6656 , H01L29/66659 , H01L29/7835
摘要： According to an exemplary embodiment, a method for fabricating a MOS transistor, such as an LDMOS transistor, includes forming a self-aligned lightly doped region in a first well underlying a first sidewall of a gate. The method further includes forming a self-aligned extension region under a second sidewall of the gate, where the self-aligned extension region extends into the first well from a second well. The method further includes forming a drain region spaced apart from the second sidewall of the gate. The method further includes forming a source region in the self-aligned lightly doped region and the first well. The self-aligned lightly doped region and the self-aligned extension region define a channel length of the MOS transistor, such as an LDMOS transistor.
摘要翻译：根据示例性实施例，用于制造诸如LDMOS晶体管的MOS晶体管的方法包括在栅极的第一侧壁下面的第一阱中形成自对准的轻掺杂区域。该方法还包括在栅极的第二侧壁下方形成自对准延伸区域，其中自对准延伸区域从第二阱延伸到第一阱中。该方法还包括形成与栅极的第二侧壁间隔开的漏极区域。该方法还包括在自对准轻掺杂区域和第一阱中形成源极区域。自对准轻掺杂区域和自对准延伸区域限定诸如LDMOS晶体管的MOS晶体管的沟道长度。

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