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81. 发明申请

US20100237312A1 Nonvolatile memory device 有权
标题翻译：非易失性存储器件
公开(公告)号：US20100237312A1
公开(公告)日：2010-09-23
申请号：US12659175
申请日：2010-02-26
申请人： Kwang-soo Seol , Yoon-dong Park , Deok-kee Kim , Sang-jun Choi
发明人： Kwang-soo Seol , Yoon-dong Park , Deok-kee Kim , Sang-jun Choi
IPC分类号： H01L45/00
CPC分类号： H01L27/2445 , H01L27/2436 , H01L27/249 , H01L45/04 , H01L45/06 , H01L45/1226 , H01L45/144 , H01L45/146 , H01L45/147
摘要： The nonvolatile memory device includes at least one pair of first electrode lines, at least one device structure disposed between the at least one pair of first electrode lines and a dielectric layer disposed between the at least one device structure and the at least one pair of first electrode lines. The at least one device structure includes a second electrode line including a first conductive type semiconductor, a resistance changing material layer adjacent to the second electrode line, a channel adjacent to the resistance changing material layer and including a second conductive type semiconductor different from the first conductive type semiconductor and a third electrode line adjacent to the channel and including the first conductive type semiconductor.
摘要翻译：非易失性存储器件包括至少一对第一电极线，设置在至少一对第一电极线之间的至少一个器件结构和设置在该至少一个器件结构与至少一对第一电极线之间的电介质层电极线。所述至少一个器件结构包括第二电极线，所述第二电极线包括第一导电类型半导体，与所述第二电极线相邻的电阻改变材料层，与所述电阻变化材料层相邻的通道，并且包括不同于所述第一导电类型的第一导电型半导体导电型半导体和与沟道相邻的第三电极线，并且包括第一导电型半导体。

82. 发明授权

US07709928B2 Electromigration fuse and method of fabricating same 有权
标题翻译：电流保险丝及其制造方法
公开(公告)号：US07709928B2
公开(公告)日：2010-05-04
申请号：US11869227
申请日：2007-10-09
申请人： Deok-kee Kim , Haining Sam Yang
发明人： Deok-kee Kim , Haining Sam Yang
IPC分类号： H01L29/00
CPC分类号： H01L23/5256 , H01L28/20 , H01L2924/0002 , H01L2924/00
摘要： Fuses and methods of forming fuses. The fuse includes: a dielectric layer on a semiconductor substrate; a cathode stack on the dielectric layer, a sidewall of the cathode stack extending from a top surface of the cathode stack to a top surface of the dielectric layer; a continuous polysilicon layer comprising a cathode region, an anode region, a link region between the cathode and anode regions and a transition region between the cathode region and the link region, the transition region proximate to the sidewall of the cathode stack, the cathode region on a top surface of the cathode stack, the link region on a top surface of the dielectric layer, both a first thickness of the cathode region and a second thickness of the link region greater than a third thickness of the transition region; and a metal silicide layer on a top surface of the polysilicon layer.
摘要翻译：保险丝和形成保险丝的方法。保险丝包括：半导体衬底上的电介质层; 电介质层上的阴极堆叠，阴极堆叠的侧壁从阴极堆叠的顶表面延伸到电介质层的顶表面; 连续多晶硅层，包括阴极区域，阳极区域，阴极和阳极区域之间的连接区域以及阴极区域和连接区域之间的过渡区域，靠近阴极堆叠侧壁的过渡区域，阴极区域在阴极堆叠的顶表面上，电介质层的顶表面上的连接区域，阴极区域的第一厚度和连接区域的第二厚度大于过渡区域的第三厚度; 以及在所述多晶硅层的顶表面上的金属硅化物层。

83. 发明授权

US07683416B2 Post STI trench capacitor 失效
标题翻译：后STI沟槽电容器
公开(公告)号：US07683416B2
公开(公告)日：2010-03-23
申请号：US11935698
申请日：2007-11-06
申请人： Anil K. Chinthakindi , Deok-kee Kim , Xi Li
发明人： Anil K. Chinthakindi , Deok-kee Kim , Xi Li
IPC分类号： H01L27/108
CPC分类号： H01L29/94 , H01L28/91 , H01L29/66181
摘要： A design structure for capacitor having a suitably large value for decoupling applications is formed in a trench defined by isolation structures such as recessed isolation or shallow trench isolation. The capacitor provides a contact area coextensive with an active area and can be reliably formed individually or in small numbers. Plate contacts are preferably made through implanted regions extending to or between dopant diffused regions forming a capacitor plate. The capacitor can be formed by a process subsequent to formation of isolation structures such that preferred soft mask processes can be used to form the isolation structures and process commonality and compatibility constraint are avoided while the capacitor forming processes can be performed in common with processing for other structures.
摘要翻译：在由诸如凹陷隔离或浅沟槽隔离的隔离结构限定的沟槽中形成用于去耦应用的适当大值的电容器的设计结构。电容器提供与有源区域共同延伸的接触区域，并且可以单独或少量可靠地形成。板触点优选通过延伸到形成电容器板的掺杂剂扩散区域之间或之间的注入区域制成。可以通过形成隔离结构之后的过程形成电容器，使得可以使用优选的软掩模工艺来形成隔离结构和工艺共同性，并避免兼容性约束，同时电容器形成过程可以与其他处理共同执行结构。

84. 发明申请

US20090283840A1 METAL GATE INTEGRATION STRUCTURE AND METHOD INCLUDING METAL FUSE, ANTI-FUSE AND/OR RESISTOR 有权
标题翻译：金属栅组合结构和方法，包括金属保险丝，抗保险丝和/或电阻
公开(公告)号：US20090283840A1
公开(公告)日：2009-11-19
申请号：US12119526
申请日：2008-05-13
申请人： Douglas D. Coolbaugh , Ebenezer E. Eshun , Ephrem G. Gebreselasie , Zhong-Xiang He , Herbert Lei Ho , Deok-kee Kim , Chandrasekharan Kothandaraman , Dan Moy , Robert Mark Rassel , John Matthew Safran , Kenneth Jay Stein , Norman Whitelaw Robson , Ping-Chuan Wang , Hongwen Yan
发明人： Douglas D. Coolbaugh , Ebenezer E. Eshun , Ephrem G. Gebreselasie , Zhong-Xiang He , Herbert Lei Ho , Deok-kee Kim , Chandrasekharan Kothandaraman , Dan Moy , Robert Mark Rassel , John Matthew Safran , Kenneth Jay Stein , Norman Whitelaw Robson , Ping-Chuan Wang , Hongwen Yan
IPC分类号： H01L27/06 , H01L21/8234
CPC分类号： H01L27/0629 , H01L23/5252 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor structure and a method for fabricating the semiconductor structure provide a field effect device located and formed upon an active region of a semiconductor substrate and at least one of a fuse structure, an anti-fuse structure and a resistor structure located and formed at least in part simultaneously upon an isolation region laterally separated from the active region within the semiconductor substrate. The field effect device includes a gate dielectric comprising a high dielectric constant dielectric material and a gate electrode comprising a metal material. The at least one of the fuse structure, anti-fuse structure and resistor structure includes a pad dielectric comprising the same material as the gate dielectric, and optionally, also a fuse, anti-fuse or resistor that may comprise the same metal material as the gate electrode.
摘要翻译：半导体结构和半导体结构的制造方法提供一种场效应器件，其位于和形成在半导体衬底的有源区上，并且至少一个熔丝结构，抗熔丝结构和电阻结构中的至少一个至少位于并形成部分地同时地在与半导体衬底内的有源区域横向分离的隔离区域上。场效应器件包括包括高介电常数介电材料的栅极电介质和包括金属材料的栅电极。熔丝结构，反熔丝结构和电阻器结构中的至少一个包括包括与栅极电介质相同的材料的焊盘电介质，以及可选地还包括熔断器，反熔丝或电阻器，其可以包括与所述栅极电介质相同的金属材料栅电极。

85. 发明申请

US20090243787A1 Electrical fuse devices and methods of operating the same 审中-公开
标题翻译：电熔丝装置及其操作方法
公开(公告)号：US20090243787A1
公开(公告)日：2009-10-01
申请号：US12382877
申请日：2009-03-26
申请人： Soo-Jung Hwang , Ha-young You , Deok-kee Kim , Jung-hun Sung , Young-chang Joo , Sung-yup Jung
发明人： Soo-Jung Hwang , Ha-young You , Deok-kee Kim , Jung-hun Sung , Young-chang Joo , Sung-yup Jung
IPC分类号： H01H85/04
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： Provided are an electrical fuse device and a method of operating the same. The electrical fuse device may include a fuse link having a multi layer structure with at least two metal layers. The number of metal layers that are blown, from among the at least two metal layers, may vary according to either the duration of application of voltage or the strength of voltage applied.
摘要翻译：提供一种电熔丝装置及其操作方法。电熔丝器件可以包括具有至少两个金属层的多层结构的熔断体。从至少两个金属层中吹出的金属层的数量可以根据施加电压的持续时间或施加的电压的强度而变化。

86. 发明申请

US20090231900A1 Fuse devices and methods of operating the same 失效
标题翻译：保险丝及其操作方法
公开(公告)号：US20090231900A1
公开(公告)日：2009-09-17
申请号：US12285914
申请日：2008-10-16
申请人： Deok-kee Kim
发明人： Deok-kee Kim
IPC分类号： G11C17/16
CPC分类号： G11C17/16
摘要： A fuse device includes a fuse unit, which includes a cathode, an anode, and a fuse link coupling the cathode and the anode. A transistor includes at least a portion of the fuse unit to be used as an element of the transistor.
摘要翻译：保险丝装置包括熔丝单元，其包括阴极，阳极和联接阴极和阳极的熔断体。晶体管包括用作晶体管的元件的熔丝单元的至少一部分。

87. 发明申请

US20090206978A1 Electrical fuse device including a fuse link 审中-公开
标题翻译：电熔丝装置包括熔断体
公开(公告)号：US20090206978A1
公开(公告)日：2009-08-20
申请号：US12379347
申请日：2009-02-19
申请人： Soo-Jung Hwang , Deok-kee Kim , Jung-hun Sung , I-hun Song , Hyuk-soon Choi
发明人： Soo-Jung Hwang , Deok-kee Kim , Jung-hun Sung , I-hun Song , Hyuk-soon Choi
IPC分类号： H01H85/10
CPC分类号： G11C17/16 , H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： Example embodiments relate to an electrical device, for example, to an electrical fuse device that includes a fuse link for linking a cathode and anode. An electrical device may include a cathode, an anode, and a fuse link. The fuse link may link the cathode and the anode. The fuse link may include a multi-metal layer structure. The fuse link may include a first metal layer including a first resistance, and a second metal layer stacked on the first metal layer and including a second resistance. The first resistance may be different from the second resistance. The fuse link may include a weak point as a region at which electrical blowing is performed easier than other regions of the fuse link.
摘要翻译：示例性实施例涉及电气设备，例如电气熔断器件，其包括用于连接阴极和阳极的熔断体。电气设备可以包括阴极，阳极和熔断体。熔丝链可以连接阴极和阳极。熔丝链可以包括多金属层结构。熔丝连接件可以包括第一金属层和第二金属层，第一金属层包括第一电阻，第二金属层堆叠在第一金属层上并包括第二电阻。第一阻力可能与第二阻力不同。熔断体可以包括作为进行电吹送的区域的弱点比熔丝链的其它区域更容易。

88. 发明授权

US07564086B2 Self-aligned, silicided, trench-based DRAM/eDRAM processes with improved retention 失效
标题翻译：自对准，硅化，基于沟槽的DRAM / eDRAM工艺，具有更好的保留性
公开(公告)号：US07564086B2
公开(公告)日：2009-07-21
申请号：US11566360
申请日：2006-12-04
申请人： Oh-Jung Kwon , Kim Bosang , Herbert Lei Ho , Ali Babar Khan , Deok-kee Kim
发明人： Oh-Jung Kwon , Kim Bosang , Herbert Lei Ho , Ali Babar Khan , Deok-kee Kim
IPC分类号： H01L29/76
CPC分类号： H01L27/10867 , H01L27/10888
摘要： A DRAM cell in a substrate has a deep trench (DT) extending from a surface of the substrate into the substrate, a word line (WL) formed on the surface of the substrate adjacent the deep trench, and oxide (TTO) disposed in a top portion of the trench and extending beyond the trench in the direction of the word line. In this manner, when silicided, there is oxide rather than silicon on the surface of the substrate in a gap between the word line (WL) and a passing word line (PWL) disposed above the deep trench.
摘要翻译：衬底中的DRAM单元具有从衬底的表面延伸到衬底中的深沟槽（DT），形成在与深沟槽相邻的衬底的表面上的字线（WL）和设置在衬底中的氧化物（TTO）沟槽的顶部并且在字线的方向上延伸超过沟槽。以这种方式，当硅化时，在位于深沟槽之上的字线（WL）和通过字线（PWL）之间的间隙中，衬底表面上存在氧化物而不是硅。

89. 发明申请

US20090141533A1 METAL GATE COMPATIBLE ELECTRICAL ANTIFUSE 有权
标题翻译：金属门兼容电抗
公开(公告)号：US20090141533A1
公开(公告)日：2009-06-04
申请号：US11946938
申请日：2007-11-29
申请人： Deok-kee Kim , Chandrasekharan Kothandaraman , Dan Moy , Norman W. Robson , John M. Safran , Kenneth J. Stein
发明人： Deok-kee Kim , Chandrasekharan Kothandaraman , Dan Moy , Norman W. Robson , John M. Safran , Kenneth J. Stein
IPC分类号： G11C17/08 , H01L27/20 , H01L21/768
CPC分类号： H01L23/5252 , H01L2924/0002 , H01L2924/00
摘要： A metal layer and a semiconductor layer are sequentially deposited on a substrate. The semiconductor layer and the metal layer are lithographically patterned to form a stack of a semiconductor portion and a metal gate portion, which is preferably performed concurrently with formation of at least one metal gate stack. In one embodiment, the size of the semiconductor portion is reduced and a metal semiconductor alloy portion is formed on the semiconductor portion by metallization. In a first electrical antifuse formed thereby, the metal semiconductor alloy portion may be electromigrated to form a short between the metal semiconductor alloy portion and the metal gate portion. In another embodiment, two disjoined metal semiconductor alloy portions are formed on the semiconductor portion. In a second electrical antifuse formed thereby, the metal semiconductor alloy portion may be electromigrated to form a short between the two previously disjoined metal semiconductor alloy portions.
摘要翻译：金属层和半导体层顺序地沉积在基板上。半导体层和金属层被光刻图案化以形成半导体部分和金属栅极部分的堆叠，其优选地与至少一个金属栅极叠层的形成同时进行。在一个实施例中，半导体部分的尺寸减小，并且金属半导体合金部分通过金属化形成在半导体部分上。在由此形成的第一电反熔丝中，金属半导体合金部分可以电铸以在金属半导体合金部分和金属栅极部分之间形成短路。在另一个实施例中，在半导体部分上形成两个非接合的金属半导体合金部分。在由此形成的第二电反熔丝中，金属半导体合金部分可以被电铸以在两个先前接合的金属半导体合金部分之间形成短路。

90. 发明申请

US20090101989A1 METAL GATE COMPATIBLE ELECTRICAL FUSE 失效
标题翻译：金属门兼容电保险丝
公开(公告)号：US20090101989A1
公开(公告)日：2009-04-23
申请号：US11874385
申请日：2007-10-18
申请人： Xiangdong Chen , Deok-kee Kim , Chandrasekharan Kothandaraman
发明人： Xiangdong Chen , Deok-kee Kim , Chandrasekharan Kothandaraman
IPC分类号： H01L27/06 , H01L21/3205
CPC分类号： H01L27/0617 , H01L23/5256 , H01L29/4238 , H01L2924/0002 , H01L2924/00
摘要： A dielectric material layer is formed on a metal gate layer for a metal gate electrode, and then lithographically patterned to form a dielectric material portion, followed by formation of a polycrystalline semiconductor layer thereupon. A semiconductor device employing a metal gate electrode is formed in a region of the semiconductor substrate containing a vertically abutting stack of the metal gate layer and the polycrystalline semiconductor layer. A material stack in the shape of an electrical fuse is formed in another region of the semiconductor substrate containing a vertical stack of the metal gate layer, the dielectric material portion, and the polycrystalline semiconductor layer. After metallization of the polycrystalline semiconductor layer, an electrical fuse containing a polycrystalline semiconductor portion and a metal semiconductor alloy portion is formed over the dielectric material portion that separates the electrical fuse from the metal gate layer.
摘要翻译：在用于金属栅电极的金属栅极层上形成电介质材料层，然后通过光刻图案形成电介质材料部分，随后在其上形成多晶半导体层。在包含金属栅极层和多晶半导体层的垂直邻接堆叠的半导体基板的区域中形成采用金属栅电极的半导体器件。形成有电熔丝形状的材料堆叠形成在半导体衬底的另一区域中，该区域包含金属栅极层，电介质材料部分和多晶半导体层的垂直叠层。在多晶半导体层的金属化之后，在将电熔丝与金属栅极层分离开的电介质材料部分上形成包含多晶半导体部分和金属半导体合金部分的电熔丝。

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