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1. 发明授权

US08216635B2 Method of forming metal wiring and metal wiring formed using the same 有权
标题翻译：形成金属布线和使用其形成的金属布线的方法
公开(公告)号：US08216635B2
公开(公告)日：2012-07-10
申请号：US12503491
申请日：2009-07-15
申请人： Young Ah Song , Young Chang Joo , Ji Hoon Lee , Seol Min Yi , Jae Woo Joung , Sung Il Oh , Tae Hoon Kim , In Young Kim
发明人： Young Ah Song , Young Chang Joo , Ji Hoon Lee , Seol Min Yi , Jae Woo Joung , Sung Il Oh , Tae Hoon Kim , In Young Kim
IPC分类号： B05D5/12 , B05D3/00
CPC分类号： H05K3/1283 , H05K2201/0257 , H05K2203/085 , H05K2203/086 , H05K2203/1131 , H05K2203/1476 , Y10T428/24917
摘要： Disclosed are a method of forming metal wiring and metal wiring formed using the same. The method includes printing wiring using an ink composition including metallic nanoparticles and dispersants maintaining dispersion of the metallic nanoparticles, performing a first firing process of firing the wiring under vacuum or in an inert atmosphere to suppress grain growth, and performing a second firing process of firing the wiring with the vacuum or inert atmosphere released, to accelerate grain growth. The method of forming metal wiring induces abnormal grain growth by rapidly removing dispersants, capable of inducing the growth of metallic nanoparticles, at a temperature at which the growth force of the metallic nanoparticles is high, in the process of firing the metallic nanoparticles. Accordingly, the metal wiring has a coarse-grained structure containing metallic particles with a large average particle size, and the electrical and mechanical characteristics thereof can be enhanced.
摘要翻译：公开了一种形成金属布线和使用其形成的金属布线的方法。该方法包括使用包括金属纳米颗粒的油墨组合物和保持金属纳米颗粒的分散体的分散剂进行印刷布线，进行在真空或惰性气氛下烧结布线以抑制晶粒生长的第一煅烧工艺，并进行第二次烧制布线与真空或惰性气体释放，加速晶粒生长。在金属纳米粒子的烧制过程中，在金属纳米粒子的生长力高的温度下快速除去能够诱导金属纳米粒子生长的分散剂，形成金属配线的方法可以引起异常的晶粒生长。因此，金属布线具有含有平均粒径大的金属粒子的粗粒结构，能够提高其电气和机械特性。

2. 发明授权

US07929330B2 Multi-bit memory device using multi-plug 有权
标题翻译：多位存储设备使用多插头
公开(公告)号：US07929330B2
公开(公告)日：2011-04-19
申请号：US12379894
申请日：2009-03-04
申请人： Deok-kee Kim , Ha-young You , Young-chang Joo , Jung-hun Sung , Soo-jung Hwang , Sung-yup Jung
发明人： Deok-kee Kim , Ha-young You , Young-chang Joo , Jung-hun Sung , Soo-jung Hwang , Sung-yup Jung
IPC分类号： G11C17/06
CPC分类号： H01L27/101 , G11C11/5692
摘要： A memory device may include a cathode, an anode, a link connected to the anode, and a first connection element that connects the link to the cathode. The link and the anode may be located in a position lower than that of the cathode or the link and the anode may be located in a position higher than that of the cathode. Also, the cathode, the anode, the link, and the first connection element may be formed on the same plane.
摘要翻译：存储器件可以包括阴极，阳极，连接到阳极的连杆以及将连杆连接到阴极的第一连接元件。连接件和阳极可以位于比阴极或连接件低的位置，并且阳极可以位于比阴极高的位置。此外，阴极，阳极，连接件和第一连接元件也可以形成在同一平面上。

3. 发明申请

US20130037946A1 SEMICONDUCTOR CHIP INCLUDING BUMP HAVING BARRIER LAYER, AND MANUFACTURING METHOD THEREOF 审中-公开
标题翻译：半导体芯片，包括带有障碍层的保护膜及其制造方法
公开(公告)号：US20130037946A1
公开(公告)日：2013-02-14
申请号：US13642713
申请日：2011-04-21
申请人： Sung-Dong Kim , Hoo-Jeong Lee , Eun-Kyung Kim , Young-Chang Joo , Gu-Sung Kim
发明人： Sung-Dong Kim , Hoo-Jeong Lee , Eun-Kyung Kim , Young-Chang Joo , Gu-Sung Kim
IPC分类号： H01L23/498 , H01L21/768
CPC分类号： H01L21/76898 , H01L21/4853 , H01L23/481 , H01L23/49816 , H01L24/11 , H01L24/13 , H01L24/14 , H01L24/81 , H01L25/0657 , H01L25/50 , H01L2224/0346 , H01L2224/03462 , H01L2224/0391 , H01L2224/03912 , H01L2224/0401 , H01L2224/05009 , H01L2224/05567 , H01L2224/05568 , H01L2224/05655 , H01L2224/05666 , H01L2224/06181 , H01L2224/11009 , H01L2224/11464 , H01L2224/13025 , H01L2224/13082 , H01L2224/13083 , H01L2224/13111 , H01L2224/13124 , H01L2224/13147 , H01L2224/13155 , H01L2224/13157 , H01L2224/13166 , H01L2224/13171 , H01L2224/13181 , H01L2224/14181 , H01L2224/16148 , H01L2224/16238 , H01L2224/81193 , H01L2224/81203 , H01L2224/8181 , H01L2224/8182 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06548 , H01L2225/06572 , H01L2924/00014 , H01L2924/0002 , H01L2924/01029 , H01L2924/01327 , H01L2924/12042 , H01L2924/1431 , H01L2924/1434 , H01L2924/01007 , H01L2924/01028 , H01L2924/01023 , H01L2924/01074 , H01L2924/00 , H01L2224/05552
摘要： A semiconductor chip includes a first substrate including a first surface and a second surface, a through-via plug passing through the first substrate, and a first conduction layer connected to an end of the through-via plug on the first surface, and a first bump including a first barrier layer on the first conduction layer, and a first solder layer for connecting the first substrate and a second substrate on the first barrier layer, and the first barrier layer includes a barrier material for preventing diffusion of a conductive material of the first conduction layer into the first solder layer.
摘要翻译：半导体芯片包括：第一基板，包括第一表面和第二表面;穿过第一基板的通孔塞;以及连接到第一表面上的通孔塞末端的第一导电层，包括第一导电层上的第一阻挡层的凸块和用于在第一阻挡层上连接第一基板和第二基板的第一焊料层，并且第一阻挡层包括用于防止导电材料的扩散的阻挡材料第一导电层进入第一焊料层。

4. 发明申请

US20100196681A1 METHOD OF FORMING METAL WIRING AND METAL WIRING FORMED USING THE SAME 有权
标题翻译：形成金属接线和使用该金属接线的金属接线方法
公开(公告)号：US20100196681A1
公开(公告)日：2010-08-05
申请号：US12503491
申请日：2009-07-15
申请人： Young Ah SONG , Young Chang Joo , Ji Hoon Lee , Seol Min Yi , Jae Woo Joung , Sung Il Oh , Tae Hoon Kim , In Young Kim
发明人： Young Ah SONG , Young Chang Joo , Ji Hoon Lee , Seol Min Yi , Jae Woo Joung , Sung Il Oh , Tae Hoon Kim , In Young Kim
IPC分类号： B32B15/02 , B05D5/12
CPC分类号： H05K3/1283 , H05K2201/0257 , H05K2203/085 , H05K2203/086 , H05K2203/1131 , H05K2203/1476 , Y10T428/24917
摘要： Disclosed are a method of forming metal wiring and metal wiring formed using the same. The method includes printing wiring using an ink composition including metallic nanoparticles and dispersants maintaining dispersion of the metallic nanoparticles, performing a first firing process of firing the wiring under vacuum or in an inert atmosphere to suppress grain growth, and performing a second firing process of firing the wiring with the vacuum or inert atmosphere released, to accelerate grain growth. The method of forming metal wiring induces abnormal grain growth by rapidly removing dispersants, capable of inducing the growth of metallic nanoparticles, at a temperature at which the growth force of the metallic nanoparticles is high, in the process of firing the metallic nanoparticles. Accordingly, the metal wiring has a coarse-grained structure containing metallic particles with a large average particle size, and the electrical and mechanical characteristics thereof can be enhanced.
摘要翻译：公开了一种形成金属布线和使用其形成的金属布线的方法。该方法包括使用包括金属纳米颗粒的油墨组合物和保持金属纳米颗粒的分散体的分散剂进行印刷布线，进行在真空或惰性气氛下烧结布线以抑制晶粒生长的第一煅烧工艺，并进行第二次烧制布线与真空或惰性气体释放，加速晶粒生长。在金属纳米粒子的烧制过程中，在金属纳米粒子的生长力高的温度下快速除去能够诱导金属纳米粒子生长的分散剂，形成金属配线的方法可以引起异常的晶粒生长。因此，金属布线具有含有平均粒径大的金属粒子的粗粒结构，能够提高其电气和机械特性。

5. 发明申请

US20090243787A1 Electrical fuse devices and methods of operating the same 审中-公开
标题翻译：电熔丝装置及其操作方法
公开(公告)号：US20090243787A1
公开(公告)日：2009-10-01
申请号：US12382877
申请日：2009-03-26
申请人： Soo-Jung Hwang , Ha-young You , Deok-kee Kim , Jung-hun Sung , Young-chang Joo , Sung-yup Jung
发明人： Soo-Jung Hwang , Ha-young You , Deok-kee Kim , Jung-hun Sung , Young-chang Joo , Sung-yup Jung
IPC分类号： H01H85/04
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： Provided are an electrical fuse device and a method of operating the same. The electrical fuse device may include a fuse link having a multi layer structure with at least two metal layers. The number of metal layers that are blown, from among the at least two metal layers, may vary according to either the duration of application of voltage or the strength of voltage applied.
摘要翻译：提供一种电熔丝装置及其操作方法。电熔丝器件可以包括具有至少两个金属层的多层结构的熔断体。从至少两个金属层中吹出的金属层的数量可以根据施加电压的持续时间或施加的电压的强度而变化。

6. 发明授权

US06242349B1 Method of forming copper/copper alloy interconnection with reduced electromigration 有权
标题翻译：形成铜/铜合金互连的方法，减少电迁移
公开(公告)号：US06242349B1
公开(公告)日：2001-06-05
申请号：US09207680
申请日：1998-12-09
申请人： Takeshi Nogami , Sergey Lopatin , Young-Chang Joo
发明人： Takeshi Nogami , Sergey Lopatin , Young-Chang Joo
IPC分类号： H01L2144
CPC分类号： H01L21/76874 , H01L21/76843 , H01L21/76864 , H01L21/76873 , H05K1/0306 , H05K3/388
摘要： The electromigration of a Cu or Cu alloy interconnection member is reduced by annealing the seed layer before electroplating or electroless plating the Cu or Cu alloy interconnection member on the seed layer. Embodiments include depositing a Cu or Cu alloy seed layer, annealing at about 100° C. to about 400° C. to increase the grain size of the seed layer and impart a (111)-dominant crystallographic option before plating the Cu or Cu alloy interconnect member thereon the seed layer
摘要翻译：通过在种子层上电镀或无电镀Cu或Cu合金互连构件之前退火种子层，可以减少Cu或Cu合金互连构件的电迁移。实施方案包括沉积Cu或Cu合金种子层，在约100℃至约400℃退火以增加种子层的晶粒尺寸并在镀覆Cu或Cu合金之前赋予（111） - 显性晶体选择互连部件上的籽晶层

7. 发明申请

US20110253431A1 Printed circuit substrate and method of manufacturing the same 有权
标题翻译：印刷电路基板及其制造方法
公开(公告)号：US20110253431A1
公开(公告)日：2011-10-20
申请号：US12801724
申请日：2010-06-22
申请人： Hyung Wook Park , Young Chang Joo , Hong Seok Min , Young Gwan Ko , Chang Sup Ryu , Ho Young Lee , Shin Bok Lee , Min Suk Jung
发明人： Hyung Wook Park , Young Chang Joo , Hong Seok Min , Young Gwan Ko , Chang Sup Ryu , Ho Young Lee , Shin Bok Lee , Min Suk Jung
IPC分类号： H05K1/09 , H05K3/28 , H05K3/10 , H05K1/00 , H05K1/11
CPC分类号： H05K3/244 , H05K2201/0338 , H05K2201/0769 , Y10T29/49126 , Y10T29/49155
摘要： Disclosed herein are a printed circuit substrate and a method of manufacturing the same. The printed circuit substrate includes an insulating layer, and a circuit layer that includes a circuit pattern disposed on the insulating layer and a barrier layer that is disposed to cover at least one surface of the circuit pattern and suppresses electrochemical migration from the circuit pattern, thereby making it possible to achieve high-density and secure reliability, and the method of manufacturing the same.
摘要翻译：这里公开了印刷电路基板及其制造方法。印刷电路基板包括绝缘层和电路层，该电路层包括布置在绝缘层上的电路图案和阻挡层，该阻挡层设置成覆盖电路图案的至少一个表面并抑制电路从电路图案的电化学迁移，由此使得可以实现高密度和可靠性的可靠性及其制造方法。

8. 发明授权

US6124203A Method for forming conformal barrier layers 有权
标题翻译：形成保形层的方法
公开(公告)号：US6124203A
公开(公告)日：2000-09-26
申请号：US206669
申请日：1998-12-07
申请人： Young-Chang Joo , Dirk Brown , Simon S. Chan
发明人： Young-Chang Joo , Dirk Brown , Simon S. Chan
IPC分类号： H01L21/768 , H01L21/283
CPC分类号： H01L21/76876 , H01L21/76865 , H01L21/76873
摘要： The present invention provides a method for forming barrier layers in a channel or via opening by using a plasma etching technique to etch back the barrier layer which reduces the electrical resistance of the barrier layer, maintains its barrier effectiveness and enhances the subsequent filling of the channel or via opening by conductive materials.
摘要翻译：本发明提供了一种通过使用等离子体蚀刻技术在通道或通孔开口中形成阻挡层的方法，以蚀刻阻挡层，降低阻挡层的电阻，保持其屏障效能并增强后续的通道填充或通过导电材料打开。

9. 发明授权

US6121141A Method of forming a void free copper interconnects 有权
标题翻译：形成无空隙铜互连的方法
公开(公告)号：US6121141A
公开(公告)日：2000-09-19
申请号：US198362
申请日：1998-11-24
申请人： Christy Mei-Chu Woo , Dirk Brown , Young-Chang Joo , Imran Hashim
发明人： Christy Mei-Chu Woo , Dirk Brown , Young-Chang Joo , Imran Hashim
IPC分类号： H01L21/768 , H01L21/44
CPC分类号： H01L21/76882
摘要： Void free Cu or Cu alloy interconnects are formed by annealing at superatmospheric pressure after metallization. Embodiments include filling a damascene opening in a dielectric layer with Cu or a Cu alloy and heat treating in a chamber at a pressure of about 2 atmospheres to about 750 atmospheres.
摘要翻译：通过在金属化后的超大气压下退火形成无空隙的Cu或Cu合金互连。实施例包括用Cu或Cu合金填充电介质层中的镶嵌开口，并在室内以约2个大气压至约750个大气压的压力进行热处理。

10. 发明授权

US6053034A Method for measuring fracture toughness of thin films 失效
$Method for measuring fracture toughness of thin films$
标题翻译：测量薄膜断裂韧性的方法
公开(公告)号：US6053034A
公开(公告)日：2000-04-25
申请号：US168570
申请日：1998-10-09
申请人： Ting Y. Tsui , Young-Chang Joo
发明人： Ting Y. Tsui , Young-Chang Joo
IPC分类号： G01N3/00 , G01N3/02 , G01N3/42 , G01Q60/24 , G01N3/48
CPC分类号： G01Q60/366 , B82Y35/00 , G01N3/42 , G01N2203/0064 , G01N2203/0067 , G01N2203/027 , G01N2203/0282 , G01N2203/0286 , Y10S977/70 , Y10S977/856 , Y10S977/90
摘要： A nanoindentation apparatus is used to measure the in-plane fracture toughness of a thin film formed on a substrate. One or more notches are formed in the thin film. An indenter is applied to the thin film near the notch or notches and a load is applied to the indenter to force it into the thin film. Because the substrate is softer than the thin film, the indenter does not penetrate the thin film, but "sinks in" to the soft substrate. The sink in effect enhances the tensile strain and stress at the notch. In one embodiment, both the penetration of the indenter into the thin film and substrate and the load on the indenter are measured. When the thin film fractures at the notch or notches, the indenter sharply sinks into the substrate. The thin film fracture toughness is then calculated based on the value of the load and penetration at the point of fracture using either finite element analysis or an analytical model. In a second embodiment, the cross-section of the notch or notches is measured after removing the indenter which has formed an indentation in the thin film. The indenter acts as a crack extension force. The thin film fracture toughness is then calculated based upon the geometry of a crack tip at the tip of the notch and using finite element analysis, or an analytical model, such as a Crack Tip Opening Displacement (CTOD) method.
摘要翻译：纳米压痕装置用于测量在基板上形成的薄膜的面内断裂韧性。在薄膜中形成一个或多个凹口。将压头施加到缺口附近的薄膜或凹口，并将负载施加到压头以将其压入薄膜中。由于衬底比薄膜柔软，所以压头不穿透薄膜，而是“沉入”到柔性衬底。水槽有效地增强了缺口处的拉伸应变和应力。在一个实施例中，测量压头到薄膜和基底的穿透以及压头上的载荷。当薄膜在切口或凹口处断裂时，压头急剧下沉到基板中。然后使用有限元分析或分析模型，基于负荷点和断裂点的穿透值计算薄膜断裂韧度。在第二实施例中，在去除在薄膜中形成凹陷的压头之后，测量切口或切口的横截面。压头作为裂纹扩展力。然后基于缺口尖端处的裂纹尖端的几何形状和使用有限元分析或诸如裂纹尖端开口位移（CTOD）方法的分析模型来计算薄膜断裂韧度。

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