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81. 发明申请

US20080229161A1 MEMORY PRODUCTS AND MANUFACTURING METHODS THEREOF 审中-公开
标题翻译：记忆产品及其制造方法
公开(公告)号：US20080229161A1
公开(公告)日：2008-09-18
申请号：US11686996
申请日：2007-03-16
申请人： Cheng-Hung Lee , Ching-Wei Wu , Chung-Cheng Chou , Hung-Jen Liao
发明人： Cheng-Hung Lee , Ching-Wei Wu , Chung-Cheng Chou , Hung-Jen Liao
IPC分类号： G11C29/00
CPC分类号： G11C29/50 , G11C29/70 , G11C29/80 , G11C2029/5004 , H01L22/22 , H01L27/1052
摘要： Memory products and manufacturing methods thereof. A memory product comprises at least one memory cell and at least one redundancy memory cell. The memory cell and the redundancy memory cell have different physical or electronic properties. The redundancy memory cells are used as repair schemes for the memory cell if the memory cell is determined to have experienced Vccmin failure.
摘要翻译：内存产品及其制造方法。存储器产品包括至少一个存储器单元和至少一个冗余存储单元。存储单元和冗余存储单元具有不同的物理或电子特性。如果确定存储器单元已经经历Vccmin故障，则冗余存储器单元被用作存储器单元的修复方案。

82. 发明申请

US20080028351A1 Memory macro with irregular edge cells 有权
标题翻译：具有不规则边缘单元格的内存宏
公开(公告)号：US20080028351A1
公开(公告)日：2008-01-31
申请号：US11493405
申请日：2006-07-26
申请人： Chung-Cheng Chou , Cheng-Hung Lee
发明人： Chung-Cheng Chou , Cheng-Hung Lee
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G06F17/5068
摘要： A memory macro includes a first set of cells disposed in a first area of a memory array, and a second set of cells, which differ from the first set of cells in physical dimensions, disposed at an edge of the first area for improving robustness of the cells at the edge of the memory array.
摘要翻译：存储器宏包括设置在存储器阵列的第一区域中的第一组单元，以及设置在第一区域的边缘处的与物理尺寸的第一组单元不同的第二组单元，用于改善第一区域的鲁棒性存储器阵列边缘的单元格。

83. 发明申请

US20070063761A1 Charge pump system with smooth voltage output 有权
标题翻译：电荷泵系统，电压输出平滑
公开(公告)号：US20070063761A1
公开(公告)日：2007-03-22
申请号：US11231035
申请日：2005-09-20
申请人： Chung-Cheng Chou , Chien-Hua Huang
发明人： Chung-Cheng Chou , Chien-Hua Huang
IPC分类号： G05F1/10
CPC分类号： H02M3/07
摘要： A method and system is disclosed for an improved charge pump system. The system comprises one or more charge pump devices for providing an output voltage, a ring oscillator coupled with the charge pump devices for providing an oscillator output, and a multiple level detection device for detecting the output voltage and controlling the charge pump for stabilizing the output voltage.
摘要翻译：公开了一种改进的电荷泵系统的方法和系统。该系统包括用于提供输出电压的一个或多个电荷泵装置，与电荷泵装置耦合以提供振荡器输出的环形振荡器，以及用于检测输出电压并控制电荷泵稳定输出的多电平检测装置电压。

84. 发明申请

US20060284932A1 Fluid injector and method of manufacturing the same 失效
标题翻译：流体注射器及其制造方法
公开(公告)号：US20060284932A1
公开(公告)日：2006-12-21
申请号：US11372964
申请日：2006-03-09
申请人： Hung-Sheng Hu , Wei-Lin Chen , In-Yao Lee , Tsung-Ping Hsu , Chung-Cheng Chou , ShangShi Wu
发明人： Hung-Sheng Hu , Wei-Lin Chen , In-Yao Lee , Tsung-Ping Hsu , Chung-Cheng Chou , ShangShi Wu
IPC分类号： B41J2/04
CPC分类号： B41J2/14137 , Y10T29/49126 , Y10T29/49128 , Y10T29/4913 , Y10T29/49401
摘要： A fluid injector and method of manufacturing the same. The fluid injector comprises a base, a first through hole, a bubble generator, a passivation layer, and a metal layer. The base includes a chamber and a surface. The first through hole communicates with the chamber, and is disposed in the base. The bubble generator is disposed on the surface near the first through hole, and is located outside the chamber. The passivation layer is disposed on the surface. The metal layer defines a second through hole, and is disposed on the passivation layer outside the chamber. The second through hole communicates with the first through hole.
摘要翻译：一种流体注射器及其制造方法。流体注射器包括底座，第一通孔，气泡发生器，钝化层和金属层。底座包括一个腔室和一个表面。第一通孔与腔室连通，并设置在基座中。气泡发生器设置在靠近第一通孔的表面上，并且位于室外。钝化层设置在表面上。金属层限定第二通孔，并且设置在室外的钝化层上。第二通孔与第一通孔连通。

85. 发明授权

US07142043B2 On chip word line voltage with PVT tracking for memory embedded in logic process 有权
标题翻译：片上字线电压采用PVT追踪内存嵌入逻辑过程
公开(公告)号：US07142043B2
公开(公告)日：2006-11-28
申请号：US10909729
申请日：2004-08-02
申请人： Chung-Cheng Chou
发明人： Chung-Cheng Chou
IPC分类号： G05F1/10
CPC分类号： G11C8/08 , G11C5/147
摘要： The present disclosure is directed toward regulation of voltage for semiconductor memories. In an embodiment, a circuit for providing a controlled voltage level comprises a PMOS transistor coupled to a first voltage coupler (VPP), the gate of the PMOS transistor being coupled to the drain of the PMOS transistor; a MOS sub-threshold current source, coupled to a second voltage coupler (ground); and a bias independent current source coupled to the MOS sub-threshold current source and the PMOS transistor intermediate the MOS sub-threshold current source and the PMOS transistor. It is emphasized that this abstract is provided to comply with the rules requiring an abstract which will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.
摘要翻译：本公开涉及用于半导体存储器的电压的调节。在一个实施例中，用于提供受控电压电平的电路包括耦合到第一电压耦合器（V PP PP）的PMOS晶体管，PMOS晶体管的栅极耦合到PMOS晶体管的漏极; 耦合到第二电压耦合器（接地）的MOS子阈值电流源; 以及耦合到MOS子阈值电流源的偏置独立电流源和位于MOS子阈值电流源和PMOS晶体管之间的PMOS晶体管。要强调的是，该摘要被提供以符合要求摘要的规则，这将允许搜索者或其他读者快速确定技术公开的主题。提交它的理解是，它不会用于解释或限制权利要求的范围或含义。

86. 发明申请

US20060092231A1 Fluid injection device and method of fabricating the same 审中-公开
标题翻译：流体注射装置及其制造方法
公开(公告)号：US20060092231A1
公开(公告)日：2006-05-04
申请号：US11265050
申请日：2005-11-02
申请人： Chung-Cheng Chou , Tsung-Ping Hsu , Shang-Shi Wu
发明人： Chung-Cheng Chou , Tsung-Ping Hsu , Shang-Shi Wu
IPC分类号： B41J2/05
CPC分类号： B41J2/1631 , B41J2/1433 , B41J2/1601 , B41J2/1628 , B41J2/1629 , B41J2/1639 , B41J2/1642 , B41J2002/1437
摘要： A fluid injection device. The device includes a substrate, a chamber formed in the substrate, and a structural layer covering the substrate and the chamber, wherein the structural layer covering the chamber has two regions with different thicknesses, and at least two nozzles pass through the two structural layer regions respectively and connected to the chamber. The method of fabricating the above fluid injection device is also disclosed.
摘要翻译：流体注射装置。该装置包括基板，形成在基板中的腔室和覆盖基板和腔室的结构层，其中覆盖腔室的结构层具有不同厚度的两个区域，并且至少两个喷嘴穿过两个结构层区域分别连接到腔室。还公开了制造上述流体注射装置的方法。

87. 发明申请

US20050248976A1 Dynamic random access memory cell leakage current detector 有权
标题翻译：动态随机存取存储单元泄漏电流检测器
公开(公告)号：US20050248976A1
公开(公告)日：2005-11-10
申请号：US10840098
申请日：2004-05-06
申请人： Chien-Hua Huang , Chung-Cheng Chou
发明人： Chien-Hua Huang , Chung-Cheng Chou
IPC分类号： G11C7/12 , G11C11/24 , G11C11/4094 , G11C29/50
CPC分类号： G11C29/50016 , G11C7/12 , G11C11/401 , G11C11/4094 , G11C29/50
摘要： A circuit operable to measure leakage current in a Dynamic Random Access Memory (DRAM) is provided comprising a plurality of DRAM bit cell access transistors coupled to a common bit line, a common word line, and a common storage node, wherein said access transistors may be biased to simulate a corresponding plurality of inactive bit cells of a DRAM; and a current mirror in communication with the common storage node operable to mirror a total leakage current from said plurality of bit cell access transistors when the access transistors are biased to simulate the inactive bit cells.
摘要翻译：提供了可操作以测量动态随机存取存储器（DRAM）中的泄漏电流的电路，其包括耦合到公共位线，公共字线和公共存储节点的多个DRAM位单元存取晶体管，其中所述存取晶体管可以被偏置以模拟DRAM的对应的多个非活动位单元; 以及与公共存储节点通信的电流镜，可操作以当存取晶体管被偏置以模拟非活动位单元时，来自所述多个位单元存取晶体管的总泄漏电流。

88. 发明授权

US06958944B1 Enhanced refresh circuit and method for reduction of DRAM refresh cycles 失效
标题翻译：增强刷新电路和减少DRAM刷新周期的方法
公开(公告)号：US06958944B1
公开(公告)日：2005-10-25
申请号：US10854051
申请日：2004-05-26
申请人： Chung-Cheng Chou
发明人： Chung-Cheng Chou
IPC分类号： G11C8/00 , G11C11/401 , G11C11/406
CPC分类号： G11C11/406 , G11C11/40622 , G11C2211/4061
摘要： A method and circuits are disclosed for refreshing a memory module. After receiving a refresh address identifying a word line to be refreshed, the refresh address is located in one of a predetermined number of memory blocks of the memory module that is monitored. It is further determined whether the word line has been accessed while the memory block is being monitored. If it is determined that the word line has not been accessed, the word line is refreshed. If it is determined that the word line has been accessed, the refreshing operation is skipped for that word line.
摘要翻译：公开了一种用于刷新存储器模块的方法和电路。在接收到识别要刷新的字线的刷新地址之后，刷新地址位于被监视的存储器模块的预定数量的存储块之一中。进一步确定在监视存储器块时是否已经访问了字线。如果确定字线未被访问，则字线被刷新。如果确定已经访问了字线，则针对该字线跳过刷新操作。

89. 发明授权

US06903436B1 Multiple-time programmable electrical fuse utilizing MOS oxide breakdown 失效
标题翻译：多次可编程电熔丝利用MOS氧化物分解
公开(公告)号：US06903436B1
公开(公告)日：2005-06-07
申请号：US10833968
申请日：2004-04-27
申请人： Ruei-Chin Luo , Chung-Cheng Chou , Ching-Wei Wu
发明人： Ruei-Chin Luo , Chung-Cheng Chou , Ching-Wei Wu
IPC分类号： G11C17/16 , G11C17/18 , H01L23/525 , H01L29/00 , H01L29/76
CPC分类号： G11C17/16 , G11C17/18 , H01L23/5252 , H01L2924/0002 , H01L2924/00
摘要： An improved a programmable electrical fuse device utilizing MOS oxide breakdown is described herein. The fuse device comprises a programmable MOS device having a first gate width, a reference MOS device having a second gate width that is substantially less than the first gate width, and a sense amplifier operable to detect a difference in current and generate a corresponding logical signal. According to one embodiment, the fuse device can be programmed only once to invert its logical state and thereby provide a changeable logical signal. This is done by applying an overvoltage signal to the programmable MOS device so that its oxide layer breaks down. Since the programmable MOS device and the reference MOS device are on opposite sides of the sense amplifier, an opposite logical signal is generated by shorting-out the programmable MOS device. According to another embodiment, the fuse device can be programmed and erased multiple times by breaking down oxide layers in MOS devices that are alternating sides of a sense amplifier.
摘要翻译：本文描述了利用MOS氧化物击穿的改进的可编程电熔丝装置。熔丝器件包括具有第一栅极宽度的可编程MOS器件，具有基本上小于第一栅极宽度的第二栅极宽度的参考MOS器件，以及用于检测电流差并产生相应逻辑信号的读出放大器。根据一个实施例，熔丝器件可以仅被编程一次以反转其逻辑状态，从而提供可变的逻辑信号。这通过对可编程MOS器件施加过电压信号以使其氧化层发生故障来完成。由于可编程MOS器件和参考MOS器件位于读出放大器的相对侧，所以通过短路可编程MOS器件产生相反的逻辑信号。根据另一实施例，通过分解作为读出放大器的交替侧的MOS器件中的氧化物层，可以对熔丝器件进行多次编程和擦除。

90. 发明申请

US20050052919A1 Temperature detecting circuit for controlling a self-refresh period of a semiconductor memory device 有权
标题翻译：用于控制半导体存储器件的自刷新周期的温度检测电路
公开(公告)号：US20050052919A1
公开(公告)日：2005-03-10
申请号：US10658833
申请日：2003-09-09
申请人： Chung-Cheng Chou
发明人： Chung-Cheng Chou
IPC分类号： G11C11/406 , G11C7/00
CPC分类号： G11C11/40626 , G11C11/406 , G11C2211/4061
摘要： Systems for providing a temperature detecting circuit includes seven transistors and six resistors. In a preferred embodiment, one of the seven transistors is configured as an enabling element and the others form two comparators. The six resistors form three voltage dividers with output varying based upon changing temperature. Two comparators are included that sense the difference between the outputs of two of the voltage dividers, and generate a corresponding 2-bit detection signal by which the refresh period is determined. Other systems and methods are also provided.
摘要翻译：用于提供温度检测电路的系统包括七个晶体管和六个电阻器。在优选实施例中，七个晶体管中的一个被配置为使能元件，而另一个形成两个比较器。六个电阻形成三个分压器，输出根据温度变化而变化。包括两个比较器，用于检测两个分压器的输出之间的差异，并产生相应的2位检测信号，由此确定刷新周期。还提供了其他系统和方法。

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