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1. 发明授权

US07035131B2 Dynamic random access memory cell leakage current detector 有权
标题翻译：动态随机存取存储单元泄漏电流检测器
公开(公告)号：US07035131B2
公开(公告)日：2006-04-25
申请号：US10840098
申请日：2004-05-06
申请人： Chien-Hua Huang , Chung-Cheng Chou
发明人： Chien-Hua Huang , Chung-Cheng Chou
IPC分类号： G11C11/24
CPC分类号： G11C29/50016 , G11C7/12 , G11C11/401 , G11C11/4094 , G11C29/50
摘要： A circuit operable to measure leakage current in a Dynamic Random Access Memory (DRAM) is provided comprising a plurality of DRAM bit cell access transistors coupled to a common bit line, a common word line, and a common storage node, wherein said access transistors may be biased to simulate a corresponding plurality of inactive bit cells of a DRAM; and a current mirror in communication with the common storage node operable to mirror a total leakage current from said plurality of bit cell access transistors when the access transistors are biased to simulate the inactive bit cells.
摘要翻译：提供了可操作以测量动态随机存取存储器（DRAM）中的泄漏电流的电路，其包括耦合到公共位线，公共字线和公共存储节点的多个DRAM位单元存取晶体管，其中所述存取晶体管可以被偏置以模拟DRAM的对应的多个非活动位单元; 以及与公共存储节点通信的电流镜，可操作以当存取晶体管被偏置以模拟非活动位单元时，来自所述多个位单元存取晶体管的总泄漏电流。

2. 发明授权

US07224207B2 Charge pump system with smooth voltage output 有权
公开(公告)号：US07224207B2
公开(公告)日：2007-05-29
申请号：US11231035
申请日：2005-09-20
申请人： Chung-Cheng Chou , Chien-Hua Huang
发明人： Chung-Cheng Chou , Chien-Hua Huang
IPC分类号： G05F1/10
CPC分类号： H02M3/07
摘要： A method and system is disclosed for an improved charge pump system. The system comprises one or more charge pump devices for providing an output voltage, a ring oscillator coupled with the charge pump devices for providing an oscillator output, and a multiple level detection device for detecting the output voltage and controlling the charge pump for stabilizing the output voltage.

3. 发明授权

US06862239B1 Circuit and method for self-refresh of DRAM cells through monitoring of cell leakage currents 有权
标题翻译：通过监测电池漏电流来自动刷新DRAM单元的电路和方法
公开(公告)号：US06862239B1
公开(公告)日：2005-03-01
申请号：US10696291
申请日：2003-10-29
申请人： Chien-Hua Huang , Chung-Cheng Chou
发明人： Chien-Hua Huang , Chung-Cheng Chou
IPC分类号： G11C11/406 , G11C7/00
CPC分类号： G11C11/40615 , G11C11/406 , G11C2211/4068
摘要： A circuit and a method for self refresh of DRAM cells are provided. The circuit comprises a bias generator and an oscillator. The bias generator comprises a first current generator, a second current generator and a converter. The first current generator generates a first leakage current of “0” state cells. The second current generator generates a second leakage current of “1” state cells. The converter transforms a current comprising the first leakage current and the second leakage current into output biases. The method comprises generating leakage currents from memory cells; transforming the leakage currents into output biases for determining a self refresh period; and using the output biases to control an oscillator for generating a periodical signal pulse in response to the leakage currents.
摘要翻译：提供了一种用于DRAM单元的自刷新的电路和方法。电路包括偏置发生器和振荡器。偏置发生器包括第一电流发生器，第二电流发生器和转换器。第一电流发生器产生“0”状态单元的第一泄漏电流。第二电流发生器产生“1”状态单元的第二泄漏电流。转换器将包括第一漏电流和第二漏电流的电流转换成输出偏压。该方法包括从存储器单元产生泄漏电流; 将泄漏电流转换成输出偏压，以确定自刷新周期; 以及使用所述输出偏压来控制用于响应于所述漏电流产生周期性信号脉冲的振荡器。

4. 发明授权

US07855932B2 Low power word line control circuits with boosted voltage output for semiconductor memory 有权
标题翻译：具有升压电压输出的半导体存储器的低功率字线控制电路
公开(公告)号：US07855932B2
公开(公告)日：2010-12-21
申请号：US11264041
申请日：2005-10-31
申请人： Chung-Cheng Chou , Chien-Hua Huang , Hau-Tai Shieh , Tsai-Hsin Lai
发明人： Chung-Cheng Chou , Chien-Hua Huang , Hau-Tai Shieh , Tsai-Hsin Lai
IPC分类号： G11C8/00
CPC分类号： G11C5/145 , G11C8/08
摘要： A word line control device has a word line driver for deactivating and activating a word line to control access to a memory cell, and a voltage coupling device for coupling voltages to the word line driver. The word line control device maintains boosted voltages and has significantly reduced leakage currents and power consumption in the active and standby modes.
摘要翻译：字线控制装置具有用于禁用和激活字线以控制对存储器单元的访问的字线驱动器，以及用于将电压耦合到字线驱动器的电压耦合装置。字线控制装置保持升压电压，并且在主动和待机模式下显着减少漏电流和功耗。

5. 发明申请

US20070063761A1 Charge pump system with smooth voltage output 有权
标题翻译：电荷泵系统，电压输出平滑
公开(公告)号：US20070063761A1
公开(公告)日：2007-03-22
申请号：US11231035
申请日：2005-09-20
申请人： Chung-Cheng Chou , Chien-Hua Huang
发明人： Chung-Cheng Chou , Chien-Hua Huang
IPC分类号： G05F1/10
CPC分类号： H02M3/07
摘要： A method and system is disclosed for an improved charge pump system. The system comprises one or more charge pump devices for providing an output voltage, a ring oscillator coupled with the charge pump devices for providing an oscillator output, and a multiple level detection device for detecting the output voltage and controlling the charge pump for stabilizing the output voltage.
摘要翻译：公开了一种改进的电荷泵系统的方法和系统。该系统包括用于提供输出电压的一个或多个电荷泵装置，与电荷泵装置耦合以提供振荡器输出的环形振荡器，以及用于检测输出电压并控制电荷泵稳定输出的多电平检测装置电压。

6. 发明申请

US20050248976A1 Dynamic random access memory cell leakage current detector 有权
标题翻译：动态随机存取存储单元泄漏电流检测器
公开(公告)号：US20050248976A1
公开(公告)日：2005-11-10
申请号：US10840098
申请日：2004-05-06
申请人： Chien-Hua Huang , Chung-Cheng Chou
发明人： Chien-Hua Huang , Chung-Cheng Chou
IPC分类号： G11C7/12 , G11C11/24 , G11C11/4094 , G11C29/50
CPC分类号： G11C29/50016 , G11C7/12 , G11C11/401 , G11C11/4094 , G11C29/50
摘要： A circuit operable to measure leakage current in a Dynamic Random Access Memory (DRAM) is provided comprising a plurality of DRAM bit cell access transistors coupled to a common bit line, a common word line, and a common storage node, wherein said access transistors may be biased to simulate a corresponding plurality of inactive bit cells of a DRAM; and a current mirror in communication with the common storage node operable to mirror a total leakage current from said plurality of bit cell access transistors when the access transistors are biased to simulate the inactive bit cells.
摘要翻译：提供了可操作以测量动态随机存取存储器（DRAM）中的泄漏电流的电路，其包括耦合到公共位线，公共字线和公共存储节点的多个DRAM位单元存取晶体管，其中所述存取晶体管可以被偏置以模拟DRAM的对应的多个非活动位单元; 以及与公共存储节点通信的电流镜，可操作以当存取晶体管被偏置以模拟非活动位单元时，来自所述多个位单元存取晶体管的总泄漏电流。

7. 发明申请

US20060203600A1 Low power word line control circuits with boosted voltage output for semiconductor memory 有权
标题翻译：具有升压电压输出的半导体存储器的低功率字线控制电路
公开(公告)号：US20060203600A1
公开(公告)日：2006-09-14
申请号：US11264041
申请日：2005-10-31
申请人： Chung-Cheng Chou , Chien-Hua Huang , Hau-Tai Shieh , Tsai-Hsin Lai
发明人： Chung-Cheng Chou , Chien-Hua Huang , Hau-Tai Shieh , Tsai-Hsin Lai
IPC分类号： G11C8/00
CPC分类号： G11C5/145 , G11C8/08
摘要： A word line control device has a word line driver for deactivating and activating a word line to control access to a memory cell, and a voltage coupling device for coupling voltages to the word line driver.
摘要翻译：字线控制装置具有用于禁用和激活字线以控制对存储器单元的访问的字线驱动器，以及用于将电压耦合到字线驱动器的电压耦合装置。

8. 发明授权

US10002820B2 Through silicon via layout pattern 有权
公开(公告)号：US10002820B2
公开(公告)日：2018-06-19
申请号：US13478815
申请日：2012-05-23
申请人： Sun-Rong Jan , Che-Yu Yeh , Chee Wee Liu , Chien-Hua Huang , Bing J. Sheu
发明人： Sun-Rong Jan , Che-Yu Yeh , Chee Wee Liu , Chien-Hua Huang , Bing J. Sheu
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L23/481 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device comprises a substrate with a first side and a second side, wherein a plurality of active circuits are formed adjacent to the first side of the substrate and a plurality of through silicon vias arranged in a polygon shape and extending from the first side of to the second side, wherein the polygon shape has more than six sides, and wherein each through silicon via is placed at a corresponding apex of the polygon shape.

9. 发明申请

US20060232322A1 Voltage transfer circuit 有权
标题翻译：电压传输电路
公开(公告)号：US20060232322A1
公开(公告)日：2006-10-19
申请号：US11162667
申请日：2005-09-19
申请人： Chien-Hua Huang
发明人： Chien-Hua Huang
IPC分类号： H03K17/687 , H03H11/24 , H03K17/296
CPC分类号： H03K19/0013 , H03K19/018521
摘要： A voltage transfer circuit outputs an equivalent to an input voltage when enabled. Otherwise, the transfer circuit is in standby and outputs an equivalent to a standby voltage (e.g., signal ground). The voltage transfer circuit includes a switching circuit, a standby circuit, and an input-transfer circuit. The output of the transfer circuit is fed back to both the switching circuit and the input-transfer circuit. When the transfer circuit is in standby, the feedback of the output voltage provides for voltage-balancing in the input-transfer circuit, thereby reducing or eliminating leakage current in the input-transfer circuit. Similarly, when the transfer circuit is in active mode, the feedback of the output voltage provides for voltage-balancing in the standby circuit, thereby reducing or eliminating leakage current in the standby circuit.
摘要翻译：电压传输电路在使能时输出等效于输入电压。否则，传输电路处于待机状态，并输出等效于待机电压（例如，信号地）。电压传输电路包括开关电路，备用电路和输入传输电路。传输电路的输出反馈给开关电路和输入传输电路。当传送电路处于待机状态时，输出电压的反馈提供输入传输电路中的电压平衡，从而减少或消除输入传输电路中的漏电流。类似地，当传输电路处于主动模式时，输出电压的反馈提供备用电路中的电压平衡，从而减少或消除备用电路中的漏电流。

10. 发明申请

US20060152990A1 Multiple-time electrical fuse programming circuit 有权
公开(公告)号：US20060152990A1
公开(公告)日：2006-07-13
申请号：US11028839
申请日：2005-01-04
申请人： Chien-Hua Huang
发明人： Chien-Hua Huang
IPC分类号： G11C17/18
CPC分类号： G11C11/5692 , G11C17/165 , G11C17/18 , G11C29/02 , G11C29/027 , G11C29/4401
摘要： A multiple-time electrical fuse programming circuit is described. The circuit includes a programming counter to record the number of programmings, a blowing reference voltage generator to generate a blowing voltage reference wherein the fuse resistance after programming is determined by the blowing voltage reference, at least one self-controlled programmable fuses which includes a programmable fuse and a control circuit. The multiple-time electrical fuse programming circuit also has a fuse detection reference generator and a high voltage power source.

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