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81. 再颁专利

USRE39227E1 Content addressable memory (CAM) arrays and cells having low power requirements 有权
标题翻译：内容可寻址存储器（CAM）阵列和具有低功率要求的单元
公开(公告)号：USRE39227E1
公开(公告)日：2006-08-08
申请号：US10403581
申请日：2003-03-31
申请人： Chuen-Der Lien , Chau-Chin Wu
发明人： Chuen-Der Lien , Chau-Chin Wu
IPC分类号： G11C15/00
CPC分类号： G11C15/04
摘要： A content addressable memory (CAM) cell that includes a static random access memory (SRAM) cell that operates in response to a VCC supply voltage. A first set of bit lines coupled to the SRAM cell are used to transfer data values to and from the SRAM cell. The signals transmitted on the first set of bit lines have a signal swing equal to the VCC supply voltage. A second set of bit lines is coupled to receive a comparison data value. The signals transmitted on the second set of bit lines have a signal swing that is less than the VCC supply voltage. For example, the signal swing on the second set of bit lines can be as low as two transistor threshold voltages. The second set of bit lines is biased with a supply voltage that is less than the VCC supply voltage. A sensor circuit is provided for comparing the data value stored in the CAM cell with the comparison data value. The sensor circuit pre-charges a match scan line prior to a compare operation. If the data value stored in the CAM cell does not match the comparison data value, the match sense line is pulled down. The signal swing of the match sense line is smaller than the VCC supply voltage. For example, the signal swing on the match sense line can be as low as one transistor threshold voltage.
摘要翻译：一种内容可寻址存储器（CAM）单元，其包括响应于V CC电源电压工作的静态随机存取存储器（SRAM）单元。耦合到SRAM单元的第一组位线用于将数据值传送到SRAM单元和从SRAM单元传送数据值。在第一组位线上发送的信号具有等于V CC电源电压的信号摆幅。第二组位线被耦合以接收比较数据值。在第二组位线上发送的信号具有小于V CC电源电压的信号摆幅。例如，第二组位线上的信号摆幅可以低至两个晶体管阈值电压。第二组位线被供给电压偏压，该电源电压小于V CC电源电压。提供了一种传感器电路，用于将存储在CAM单元中的数据值与比较数据值进行比较。在比较操作之前，传感器电路对匹配扫描线进行预充电。如果存储在CAM单元中的数据值与比较数据值不匹配，则下拉匹配检测线。匹配检测线的信号摆幅小于V CC电源电压。例如，匹配检测线上的信号摆幅可以低至一个晶体管阈值电压。

82. 发明授权

US06560156B2 CAM circuit with radiation resistance 有权
公开(公告)号：US06560156B2
公开(公告)日：2003-05-06
申请号：US10099913
申请日：2002-03-14
申请人： Chuen-Der Lien , Michael J. Miller
发明人： Chuen-Der Lien , Michael J. Miller
IPC分类号： G11C700
CPC分类号： G11C15/046 , G11C11/4125 , G11C15/04 , G11C15/043
摘要： A CAM circuit including a RAM array, a CAM array, and a control circuit that systematically writes data from the RAM array to the CAM array, thereby preventing soft errors by continually restoring data that has been corrupted by radiation. The RAM and CAM arrays can be formed on the same substrate, but are preferably fabricated on separate substrates and mounted in a single package or on a PCB. Both the CAM and RAM can be formed using any conventional memory type (e.g., SRAM, DRAM, NVRAM), and the CAM array can be a binary, ternary, or quad CAM array. The CAM and RAM arrays can be formed on different substrates, or the same substrate. A system including an SRAM ternary CAM array and a RAM array perform quad CAM functions by performing read functions utilizing only the RAM array, while performing lookup functions using the ternary CAM array.

83. 发明授权

US06512685B1 CAM circuit with separate memory and logic operating voltages 有权
标题翻译： CAM电路具有独立的存储器和逻辑工作电压
公开(公告)号：US06512685B1
公开(公告)日：2003-01-28
申请号：US10164981
申请日：2002-06-06
申请人： Chuen-Der Lien , Chau-Chin Wu
发明人： Chuen-Der Lien , Chau-Chin Wu
IPC分类号： G11C1504
CPC分类号： G11C15/00 , G11C14/00 , G11C15/04 , G11C15/043
摘要： A CAM circuit utilizes a relatively high operating voltage to control the memory portion of each CAM cell, and a relatively low operating voltage to control the logic portion of each CAM cell. The CAM cell memory portion includes a memory (e.g., SRAM) cell controlled by a word line to store data values transmitted on complementary bit lines. The CAM cell logic portion includes a comparator that compares the stored data values with an applied data value transmitted on complementary data lines, and discharges a match line when the stored data value differs from the applied data value. The memory cell is driven using the relatively high memory operating voltage (e.g., 2.5 Volts) such that the stored charge resists soft errors. The complementary data lines and match line used to operate the comparator are driven using the relatively low logic operating voltage (e.g., 1.2 Volts) to conserve power.
摘要翻译： CAM电路利用相对较高的工作电压来控制每个CAM单元的存储器部分，以及相对低的工作电压来控制每个CAM单元的逻辑部分。 CAM单元存储器部分包括由字线控制的存储器（例如，SRAM）单元，以存储在互补位线上传输的数据值。 CAM单元逻辑部分包括比较器，用于比较存储的数据值和互补数据线上传输的应用数据值，并且当存储的数据值与应用的数据值不同时，对其进行放电。使用相对高的存储器工作电压（例如，2.5伏特）来驱动存储器单元，使得存储的电荷抵抗软错误。用于操作比较器的补充数据线和匹配线使用相对较低的逻辑工作电压（例如，1.2伏特）来驱动以节省功率。

84. 发明授权

US06421265B1 DRAM-based CAM cell using 3T or 4T DRAM cells 有权
标题翻译：基于DRAM的CAM单元使用3T或4T DRAM单元
公开(公告)号：US06421265B1
公开(公告)日：2002-07-16
申请号：US09816742
申请日：2001-03-22
申请人： Chuen-Der Lien , Chau-Chin Wu , Ta-Ke Tien
发明人： Chuen-Der Lien , Chau-Chin Wu , Ta-Ke Tien
IPC分类号： G11C1500
CPC分类号： G11C15/043 , G11C15/04
摘要： A CAM cell including three-transistor (3T) or four-transistor (4T) DRAM cells. Data is stored using intrinsic capacitance of each 3T or 4T DRAM cell, and is applied to the gate terminal of a pull-down transistor. Read operations are performed in the 3T and 4T DRAM cells without disturbing the stored data value by applying the stored data value to the gate terminal of a pull-down transistor and detecting the operating state (i.e., turned on or turned off) of a pull-down transistor, thereby avoiding the charge sharing problems associated with 1T DRAM cells.
摘要翻译：包括三晶体管（3T）或四晶体管（4T）DRAM单元的CAM单元。使用每个3T或4T DRAM单元的固有电容来存储数据，并且被施加到下拉晶体管的栅极端子。通过将存储的数据值应用于下拉晶体管的栅极端子并检测拉动的操作状态（即，导通或关闭），在3T和4T DRAM单元中执行读操作，而不会干扰存储的数据值降低晶体管，从而避免与1T DRAM单元相关的电荷共享问题。

85. 发明授权

US06333524B1 Electrically programmable interlevel fusible link for integrated circuits 失效
标题翻译：用于集成电路的电可编程的层间可熔链路
公开(公告)号：US06333524B1
公开(公告)日：2001-12-25
申请号：US09342018
申请日：1999-06-28
申请人： Chuen-Der Lien , Anita M. Hansen , David J. Pilling
发明人： Chuen-Der Lien , Anita M. Hansen , David J. Pilling
IPC分类号： H01L2710
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： In a multi-level interconnect structure, a fusible material fills an opening in an isolation layer disposed between two interconnect levels or between an interconnect level and a device layer. The opening which may be, for example, a contact hole or a via, may be fabricated using processes generally used to fabricate normally sized vias and contact holes. The opening has a cross-sectional area A reduced by a factor of x relative to normally sized openings. Because the fusible interlevel interconnection has a reduced cross-sectional area, a programming current develops a destructive programming current density within fusible interlevel interconnection while current densities in coupled conductors, including normally sized vias and contacts, remain within long term reliability limits. Read/write circuitry connected to the fusible interlevel interconnection supports the programming current and supports a read current. The read current is regulated such that a responsive current density in a nonprogrammned fusible interlevel interconnection does not exceed long term reliability limits.
摘要翻译：在多层互连结构中，可熔材料填充设置在两个互连层之间或互连层与器件层之间的隔离层中的开口。可以使用通常用于制造通常尺寸的通孔和接触孔的工艺来制造可以是例如接触孔或通孔的开口。开口具有相对于正常尺寸的开口减小X因子的横截面面积A. 由于易熔层间互连具有减小的横截面积，因此编程电流在易熔层间互连中产生破坏性编程电流密度，而耦合导体（包括通常尺寸的通孔和触点）中的电流密度仍然保持在长期可靠性限度内。连接到易熔层互连的读/写电路支持编程电流并支持读取电流。读取电流被调节，使得非编程的可熔层间互连中的响应电流密度不超过长期可靠性限制。

86. 发明授权

US06307399B1 High speed buffer circuit with improved noise immunity 失效
标题翻译：具有提高抗噪声能力的高速缓冲电路
公开(公告)号：US06307399B1
公开(公告)日：2001-10-23
申请号：US09089309
申请日：1998-06-02
申请人： Chuen-Der Lien , Ta-Ke Tien
发明人： Chuen-Der Lien , Ta-Ke Tien
IPC分类号： H03K190175
CPC分类号： H03K19/00361 , H03K17/167
摘要： In a buffer circuit a pull-up circuit causes an output terminal of the buffer circuit make a transition from a low voltage to a high, and a feedback circuit increases the rate of the transition during the part of the transition when the output terminal moves from the low voltage to a predesignated voltage, the predesignated voltage being a value between but different from the low and high voltages. In another buffer circuit powered by a power supply voltage, a pull-up transistor causes a signal at an output terminal of the buffer circuit make a transition from a low voltage to a high voltage, and a converter circuit converts the power supply voltage to a lower voltage, the lower voltage powering the pull-up transistor.
摘要翻译：在缓冲电路中，上拉电路使得缓冲电路的输出端子从低电压转变到高电平，并且反馈电路在输出端子从...移动时增加转换部分期间的转换速率低电压到预定电压，预定电压是一个但不同于低电压和高电压之间的值。在由电源电压供电的另一个缓冲电路中，上拉晶体管使得缓冲电路的输出端的信号从低电压转变为高电压，并且转换器电路将电源电压转换为较低的电压，较低的电压供电上拉晶体管。

87. 发明授权

US06215708B1 Charge pump for improving memory cell low VCC performance without increasing gate oxide thickness 有权
标题翻译：电荷泵用于提高存储单元的低VCC性能，而不增加栅极氧化物厚度
公开(公告)号：US06215708B1
公开(公告)日：2001-04-10
申请号：US09164450
申请日：1998-09-30
申请人： Chuen-Der Lien , Chau-Chin Wu
发明人： Chuen-Der Lien , Chau-Chin Wu
IPC分类号： G11C1604
CPC分类号： G11C5/145 , G11C8/08 , G11C11/4085
摘要： A memory circuit that operates in response to a VCC supply voltage and a ground voltage is provided. The memory circuit includes a word line voltage generation circuit that generates a fixed word line voltage. The fixed word line voltage is selectively applied to word lines of the memory circuit. The word line voltage generation circuit generates the fixed word line voltage for all values of the VCC supply voltage between the minimum VCC supply voltage and the maximum VCC supply voltage. The fixed word line voltage is referenced to the ground voltage, rather than the VCC supply voltage. Because the ground voltage does not vary, the boosted word line voltage of the present invention can be controlled more precisely than prior art boosted word line voltages, which are referenced to the VCC supply voltage. This improved control enables the boosted word line voltage to be fixed for the entire range of the VCC supply voltage. This improved control also enables the boosted word line voltage to be selected to optimize the operating and design characteristics of the memory circuit.
摘要翻译：提供响应于VCC电源电压和接地电压工作的存储器电路。存储电路包括产生固定字线电压的字线电压产生电路。固定字线电压被选择性地施加到存储器电路的字线。字线电压产生电路为VCC电源电压的最小VCC电源电压和最大VCC电源电压之间的所有值产生固定字线电压。固定字线电压参考地电压，而不是VCC电源电压。因为接地电压没有变化，所以本发明的升压字线电压可以比参考VCC电源电压的现有技术的升压字线电压更精确地被控制。该改进的控制使得可以在VCC电源电压的整个范围内固定升压的字线电压。该改进的控制还使得可以选择提升的字线电压来优化存储器电路的操作和设计特性。

88. 发明授权

US06205049B1 Five-transistor SRAM cell 失效
标题翻译：五晶体管SRAM单元
公开(公告)号：US06205049B1
公开(公告)日：2001-03-20
申请号：US09384300
申请日：1999-08-26
申请人： Chuen-Der Lien , Chau Chin Wu
发明人： Chuen-Der Lien , Chau Chin Wu
IPC分类号： G11C1100
CPC分类号： G11C11/412 , G11C11/419
摘要： A static random access memory (SRAM) system that includes a five-transistor SRAM cell and a cell voltage control circuit coupled to provide power to the SRAM cell. The cell voltage control circuit supplies the SRAM cell with the VCC supply voltage if the SRAM cell is not being written (i.e., during a read mode or a standby mode). If the SRAM cell is being written, the cell voltage control circuit supplies the SRAM cell with a cell voltage that is less than the VCC supply voltage. The lower cell voltage weakens pull-down transistors in the SRAM cell, thereby enabling logic high values to be written to the SRAM cell. In one embodiment, the cell voltage is less than the VCC supply voltage minus the threshold voltage of an access transistor of the SRAM cell. The cell voltage is high enough to enable the SRAM cell to reliably store data during a write disturb condition. A method of operating the five-transistor SRAM cell includes the steps of (1) powering the SRAM cell with a VCC supply voltage during a read mode, (2) powering the SRAM cell with the VCC supply voltage during a standby mode, and (3) powering the SRAM cell with a cell voltage less than the VCC supply voltage during a write mode.
摘要翻译：一种静态随机存取存储器（SRAM）系统，其包括耦合以向SRAM单元提供电力的五晶体管SRAM单元和单元电压控制电路。如果SRAM单元未被写入（即，在读取模式或待机模式期间），单元电压控制电路向SRAM单元提供VCC电源电压。如果SRAM单元正被写入，则单元电压控制电路向SRAM单元提供小于VCC电源电压的单元电压。较低的电池电压会削弱SRAM单元中的下拉晶体管，从而使逻辑高电平值能够写入SRAM单元。在一个实施例中，电池电压小于VCC电源电压减去SRAM单元的存取晶体管的阈值电压。电池电压足够高，以使SRAM单元在写入干扰条件期间可靠地存储数据。一种操作五晶体管SRAM单元的方法包括以下步骤：（1）在读取模式期间，以VCC电源电压为SRAM单元供电，（2）在待机模式期间以VCC电源电压为SRAM单元供电;以及 3）在写模式期间，电池电压小于VCC电源电压为SRAM单元供电。

89. 发明授权

US06127710A CMOS structure having a gate without spacers 失效
标题翻译： CMOS结构具有不带间隔物的栅极
公开(公告)号：US06127710A
公开(公告)日：2000-10-03
申请号：US900811
申请日：1997-07-25
申请人： Jeong Yeol Choi , Chung-Jen Chien , Chung-Chyung Han , Chuen-Der Lien
发明人： Jeong Yeol Choi , Chung-Jen Chien , Chung-Chyung Han , Chuen-Der Lien
IPC分类号： H01L21/762 , H01L21/8238 , H01L29/78
CPC分类号： H01L21/823864 , H01L21/76202 , H01L21/823814 , H01L21/823871 , H01L21/823892
摘要： A CMOS Structure is disclosed wherein two adjacent transistors of opposite conductivity each have a gate above their respective channel regions. Spacers are absent from the gate of one of the transistors. The structure is also characterized by lightly doped regions.
摘要翻译：公开了CMOS结构，其中具有相反导电性的两个相邻的晶体管每个在它们各自的沟道区上方具有栅极。其中一个晶体管的栅极不存在间隔。该结构的特征还在于轻掺杂区域。

90. 发明授权

US6100128A Process for making six-transistor SRAM cell local interconnect structure 有权
标题翻译：制造六晶体管SRAM单元局部互连结构的工艺
公开(公告)号：US6100128A
公开(公告)日：2000-08-08
申请号：US129254
申请日：1998-08-04
申请人： Pailu Wang , Chuen-Der Lien , Kyle W. Terrill
发明人： Pailu Wang , Chuen-Der Lien , Kyle W. Terrill
IPC分类号： G11C11/412 , H01L27/11 , H01L21/8238
CPC分类号： G11C11/412 , H01L27/1104 , Y10S257/903
摘要： A patterned planarized insulating layer and a patterned metal layer form all local interconnects required within six-transistor SRAM cells. Supply voltage and ground lines are formed in the metal layer or in a separate layer to maximize available wiring area. Local interconnect size is maximized to increase node capacitance within the cells and reduce soft error rates, and supply voltage and ground wiring area is maximized for added cell stability and static noise margin improvement. Openings in the insulating layer for contacts, including local interconnects, bit lines, supply voltage and ground contacts, are formed with a single mask and self-aligned contact etch. Line size and spacing for the patterned metal layer is minimized because surface contours do not disturb masking and etching and all openings are formed using a single mask. The metal layer can be made thin so that the layers overlying the interconnect layer are nearly flat and so bonding pads in the metal layer are eliminated. In one embodiment, the metal layer that includes a glue layer and a plug layer and is etched to remove the plug layer from above the surface of the insulating layer. This leaves the glue layer for forming the local interconnects.
摘要翻译：图形化的平坦化绝缘层和图案化金属层形成六晶体管SRAM单元内所需的所有局部互连。在金属层或单独的层中形成电源电压和接地线以最大化可用的布线面积。局部互连尺寸最大化以增加单元内的节点电容并降低软错误率，并且为增加的单元稳定性和静态噪声容限提高，电源电压和接地布线面积最大化。用于接触的绝缘层中的开口，包括局部互连，位线，电源电压和接地触点，用单个掩模和自对准接触蚀刻形成。图案化金属层的线尺寸和间距最小化，因为表面轮廓不会妨碍掩模和蚀刻，并且使用单个掩模形成所有开口。可以使金属层变薄，使得覆盖在互连层上的层几乎是平坦的，因此消除了金属层中的接合焊盘。在一个实施例中，包括胶层和插塞层的金属层被蚀刻以从绝缘层的表面上方移除插塞层。这留下用于形成局部互连的胶层。

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