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1. 发明授权

US6100128A Process for making six-transistor SRAM cell local interconnect structure 有权
标题翻译：制造六晶体管SRAM单元局部互连结构的工艺
公开(公告)号：US6100128A
公开(公告)日：2000-08-08
申请号：US129254
申请日：1998-08-04
申请人： Pailu Wang , Chuen-Der Lien , Kyle W. Terrill
发明人： Pailu Wang , Chuen-Der Lien , Kyle W. Terrill
IPC分类号： G11C11/412 , H01L27/11 , H01L21/8238
CPC分类号： G11C11/412 , H01L27/1104 , Y10S257/903
摘要： A patterned planarized insulating layer and a patterned metal layer form all local interconnects required within six-transistor SRAM cells. Supply voltage and ground lines are formed in the metal layer or in a separate layer to maximize available wiring area. Local interconnect size is maximized to increase node capacitance within the cells and reduce soft error rates, and supply voltage and ground wiring area is maximized for added cell stability and static noise margin improvement. Openings in the insulating layer for contacts, including local interconnects, bit lines, supply voltage and ground contacts, are formed with a single mask and self-aligned contact etch. Line size and spacing for the patterned metal layer is minimized because surface contours do not disturb masking and etching and all openings are formed using a single mask. The metal layer can be made thin so that the layers overlying the interconnect layer are nearly flat and so bonding pads in the metal layer are eliminated. In one embodiment, the metal layer that includes a glue layer and a plug layer and is etched to remove the plug layer from above the surface of the insulating layer. This leaves the glue layer for forming the local interconnects.
摘要翻译：图形化的平坦化绝缘层和图案化金属层形成六晶体管SRAM单元内所需的所有局部互连。在金属层或单独的层中形成电源电压和接地线以最大化可用的布线面积。局部互连尺寸最大化以增加单元内的节点电容并降低软错误率，并且为增加的单元稳定性和静态噪声容限提高，电源电压和接地布线面积最大化。用于接触的绝缘层中的开口，包括局部互连，位线，电源电压和接地触点，用单个掩模和自对准接触蚀刻形成。图案化金属层的线尺寸和间距最小化，因为表面轮廓不会妨碍掩模和蚀刻，并且使用单个掩模形成所有开口。可以使金属层变薄，使得覆盖在互连层上的层几乎是平坦的，因此消除了金属层中的接合焊盘。在一个实施例中，包括胶层和插塞层的金属层被蚀刻以从绝缘层的表面上方移除插塞层。这留下用于形成局部互连的胶层。

2. 发明授权

US5831899A Local interconnect structure and process for six-transistor SRAM cell 失效
标题翻译：用于六晶体管SRAM单元的局部互连结构和工艺
公开(公告)号：US5831899A
公开(公告)日：1998-11-03
申请号：US841985
申请日：1997-04-07
申请人： Pailu Wang , Chuen-Der Lien , Kyle W. Terrill
发明人： Pailu Wang , Chuen-Der Lien , Kyle W. Terrill
IPC分类号： G11C11/412 , H01L27/11 , G11C11/00
CPC分类号： G11C11/412 , H01L27/1104 , Y10S257/903
摘要： A patterned planarized insulating layer and a patterned metal layer form all local interconnects required within six-transistor SRAM cells. Supply voltage and ground lines are formed in the metal layer or in a separate layer to maximize available wiring area. Local interconnect size is maximized to increase node capacitance within the cells and reduce soft error rates, and supply voltage and ground wiring area is maximized for added cell stability and static noise margin improvement. Openings in the insulating layer for contacts, including local interconnects, bit lines, supply voltage and ground contacts, are formed with a single mask and self-aligned contact etch. Line size and spacing for the patterned metal layer is minimized because surface contours do not disturb masking and etching and all openings are formed using a single mask. The metal layer can be made thin so that the layers overlying the interconnect layer are nearly flat and so that bonding pads in the metal layer are eliminated. In one embodiment, the metal layer includes a glue layer and a plug layer and is etched to remove the plug layer from above the surface of the insulating layer. This leaves the glue layer for forming the local interconnects.
摘要翻译：图形化的平坦化绝缘层和图案化金属层形成六晶体管SRAM单元内所需的所有局部互连。在金属层或单独的层中形成电源电压和接地线以最大化可用的布线面积。局部互连尺寸最大化以增加单元内的节点电容并降低软错误率，并且为增加的单元稳定性和静态噪声容限提高，电源电压和接地布线面积最大化。用于接触的绝缘层中的开口，包括局部互连，位线，电源电压和接地触点，用单个掩模和自对准接触蚀刻形成。图案化金属层的线尺寸和间距最小化，因为表面轮廓不会妨碍掩模和蚀刻，并且使用单个掩模形成所有开口。可以使金属层变薄，使得覆盖在互连层上的层几乎是平的，并且消除金属层中的接合焊盘。在一个实施例中，金属层包括胶层和塞层，并被蚀刻以从绝缘层的表面上方移除塞子层。这留下用于形成局部互连的胶层。

3. 发明授权

US5258317A Method for using a field implant mask to correct low doping levels at the outside edges of the base in a walled-emitter transistor structure 失效
标题翻译：一种使用场注入掩模来校正墙体发射极晶体管结构中基极外边缘处的低掺杂水平的方法
公开(公告)号：US5258317A
公开(公告)日：1993-11-02
申请号：US835200
申请日：1992-02-13
申请人： Chuen-Der Lien , Kyle W. Terrill
发明人： Chuen-Der Lien , Kyle W. Terrill
IPC分类号： H01L21/331 , H01L21/762 , H01L21/265
CPC分类号： H01L29/66272 , H01L21/76216 , Y10S148/01 , Y10S148/011 , Y10S148/102 , Y10S148/124
摘要： An embodiment of the present invention is a process for semiconductor device having a silicon substrate. The process comprises positioning at least one field implant mask and field implanting a silicon substrate around a bipolar active region in a substrate such that boron atoms are blocked out of an active region, and only the field region surrounding said active area is implanted, said implanting such that a predetermined layout area of a semiconductor device does not need to be increased to compensate for a BV.sub.bso problem.
摘要翻译：本发明的实施例是具有硅衬底的半导体器件的工艺。该方法包括定位至少一个场注入掩模，并且在衬底中的双极有源区周围注入硅衬底，使得硼原子被阻挡在有源区之外，并且仅植入围绕所述有源区的场区，所述注入使得半导体器件的预定布局区域不需要增加以补偿BVbso问题。

4. 发明授权

US5745404A ISRAM layout and structure 失效
标题翻译： ISRAM布局和结构
公开(公告)号：US5745404A
公开(公告)日：1998-04-28
申请号：US567443
申请日：1995-12-05
申请人： Chuen-Der Lien , Kyle W. Terrill
发明人： Chuen-Der Lien , Kyle W. Terrill
IPC分类号： H01L27/11 , G11C11/00
CPC分类号： H01L27/1112 , Y10S257/903 , Y10S257/904
摘要： A triple-poly process forms a static random access memory (SRAM) which has a compact four-transistor SRAM cell layout. The cell layout divides structures among the three layers of polysilicon to reduce the area required for each cell. Additionally, a contact between a pull-up resistor formed in an upper polysilicon layer forms a "strapping" via which cross-couples a gate region and a drain region underlying the strapping via. Pull-up resistors extend across boundaries of cell areas to increase the length and resistance of the pull-up resistors.
摘要翻译：三重多工艺形成具有紧凑的四晶体管SRAM单元布局的静态随机存取存储器（SRAM）。单元格布局在三层多晶硅之间划分结构，以减少每个单元所需的面积。此外，形成在上多晶硅层中的上拉电阻器之间的接触形成“捆扎”，通过该接头将栅极区域和穿通通孔下方的漏极区域交叉。上拉电阻延伸到单元区域的边界，以增加上拉电阻的长度和电阻。

5. 发明授权

US5574305A Walled-emitter transistor 失效
标题翻译：壁发射极晶体管
公开(公告)号：US5574305A
公开(公告)日：1996-11-12
申请号：US272277
申请日：1994-07-08
申请人： Chuen-Der Lien , Kyle W. Terrill
发明人： Chuen-Der Lien , Kyle W. Terrill
IPC分类号： H01L21/331 , H01L21/762 , H01L29/70
CPC分类号： H01L29/66272 , H01L21/76216 , Y10S148/01 , Y10S148/011 , Y10S148/102 , Y10S148/124
摘要： An embodiment of the present invention is a process for semiconductor device having a silicon substrate. The process comprises positioning at least one field implant mask and field implanting a silicon substrate around a bipolar active region in a substrate such that boron atoms are blocked out of an active region, and only the field region surrounding said active area is implanted, said implanting such that a predetermined layout area of a semiconductor device does not need to be increased to compensate for a BV.sub.bso problem.
摘要翻译：本发明的实施例是具有硅衬底的半导体器件的工艺。该方法包括定位至少一个场注入掩模，并且在衬底中的双极有源区周围注入硅衬底，使得硼原子被阻挡在有源区之外，并且仅植入围绕所述有源区的场区，所述注入使得半导体器件的预定布局区域不需要增加以补偿BVbso问题。

6. 发明授权

US06350645B1 Strapping via for interconnecting integrated circuit structures 失效
标题翻译：用于互连集成电路结构的带通
公开(公告)号：US06350645B1
公开(公告)日：2002-02-26
申请号：US08898907
申请日：1997-07-22
申请人： Chuen-Der Lien , Kyle W. Terrill
发明人： Chuen-Der Lien , Kyle W. Terrill
IPC分类号： H01L218242
CPC分类号： H01L27/1112 , Y10S148/02 , Y10S148/03 , Y10S257/903
摘要： A triple-poly process forms a static random access memory (SRAM) which has a compact four-transistor SRAM cell layout. The cell layout divides structures among the three layers of polysilicon to reduce the area required for each cell. Additionally, a contact between a pull-up resistor formed in an upper polysilicon layer forms a “strapping” via which cross-couples a gate region and a drain region underlying the strapping via. Pull-up resistors extend across boundaries of cell areas to increase the length and resistance of the pull-up resistors.
摘要翻译：三重多工艺形成具有紧凑的四晶体管SRAM单元布局的静态随机存取存储器（SRAM）。单元格布局在三层多晶硅之间划分结构，以减少每个单元所需的面积。此外，形成在上多晶硅层中的上拉电阻器之间的接触形成“捆扎”，通过该接头将栅极区域和穿通通孔下方的漏极区域交叉。上拉电阻延伸到单元区域的边界，以增加上拉电阻的长度和电阻。

7. 发明授权

US5712508A Strapping via for interconnecting integrated circuit structures 失效
公开(公告)号：US5712508A
公开(公告)日：1998-01-27
申请号：US567649
申请日：1995-12-05
申请人： Chuen-Der Lien , Kyle W. Terrill
发明人： Chuen-Der Lien , Kyle W. Terrill
IPC分类号： H01L27/11 , H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L27/1112 , Y10S148/02 , Y10S148/03 , Y10S257/903
摘要： A triple-poly process forms a static random access memory (SRAM) which has a compact four-transistor SRAM cell layout. The cell layout divides structures among the three layers of polysilicon to reduce the area required for each cell. Additionally, a contact between a pull-up resistor formed in an upper polysilicon layer forms a "strapping" via which cross-couples a gate region and a drain region underlying the strapping via. Pull-up resistors extend across boundaries of cell areas to increase the length and resistance of the pull-up resistors.

8. 发明授权

US5393677A Method of optimizing wells for PMOS and bipolar to yield an improved BICMOS process 失效
标题翻译：优化PMOS和双极的阱以产生改进的BICMOS工艺的方法
公开(公告)号：US5393677A
公开(公告)日：1995-02-28
申请号：US20234
申请日：1993-02-19
申请人： Chuen-Der Lien , Kyle W. Terrill , Jeong Y. Choi
发明人： Chuen-Der Lien , Kyle W. Terrill , Jeong Y. Choi
IPC分类号： H01L21/8249 , H01L21/265
CPC分类号： H01L21/8249
摘要： A first process embodiment of the present invention comprises the steps of implanting a blanket low dose n-well implant before field oxidation. A blanket n-type punchthrough suppression implant precedes the field oxidation step. After field oxidation, an implantation masking step is used to adjust the doping for the p-well in its active and field regions.
摘要翻译：本发明的第一种方法实施方案包括在场氧化之前植入覆盖低剂量的n阱植入物的步骤。在场氧化步骤之前，一个覆盖的n型穿通抑制植入物。在场氧化之后，使用注入掩模步骤来调整其活性区域和场区中p阱的掺杂。

9. 发明授权

US5789314A Method of topside and inter-metal oxide coating 失效
标题翻译：顶部和金属间氧化物涂层的方法
公开(公告)号：US5789314A
公开(公告)日：1998-08-04
申请号：US567648
申请日：1995-12-05
申请人： Chu-Tsao Yen , Shih-Ked Lee , Tong Zhang , Pailu Wang , Chuen-Der Lien
发明人： Chu-Tsao Yen , Shih-Ked Lee , Tong Zhang , Pailu Wang , Chuen-Der Lien
IPC分类号： H01L21/768 , H01L21/4763
CPC分类号： H01L21/76837 , Y10S438/945
摘要： A method is provided for suppressing or eliminating void formation during the manufacture of integrated circuits. TEOS is deposited and etched to form recesses that assist in eliminating or suppressing void formation. The recesses may be located in an interlevel layer, or within the oxide layer just beneath the passivation layer.
摘要翻译：提供了在集成电路制造期间抑制或消除空隙形成的方法。沉积和蚀刻TEOS以形成有助于消除或抑制空隙形成的凹陷。凹陷可以位于层间层中，或位于钝化层正下方的氧化物层内。

10. 发明授权

US07941723B1 Clock generator and method for providing reliable clock signal using array of MEMS resonators 有权
标题翻译：时钟发生器和使用MEMS谐振器阵列提供可靠时钟信号的方法
公开(公告)号：US07941723B1
公开(公告)日：2011-05-10
申请号：US11861869
申请日：2007-09-26
申请人： Chuen-Der Lien , Jimmy Lee
发明人： Chuen-Der Lien , Jimmy Lee
IPC分类号： G01R31/3181 , G01R31/40
CPC分类号： G01R31/31702 , G01R31/31727 , H03B5/32
摘要： A clock generator is disclosed that includes an array of MEMS resonators and a test circuit. The test circuit is operable at start-up to operate one or more of the MEMS resonators to generate test output and analyze the test output to determine whether the operated MEMS resonators meet test criteria. A MEMS resonator is selected that meets the test criteria and its output is used to generate an output clock signal. In addition, the test circuit is operable to analyze the output of the selected MEMS resonator and select a replacement MEMS resonator when the output of the selected MEMS resonator no longer meets the test criteria. The replacement MEMS resonator is then operated and its output is coupled to the output of the clock generator. Thereby, failing and potentially failing MEMS resonators are automatically replaced during operation of the clock generator in its end-use application.
摘要翻译：公开了一种包括MEMS谐振器阵列和测试电路的时钟发生器。测试电路在启动时可操作以操作一个或多个MEMS谐振器以产生测试输出并分析测试输出以确定所操作的MEMS谐振器是否符合测试标准。选择符合测试标准的MEMS谐振器，并且其输出用于产生输出时钟信号。另外，当选择的MEMS谐振器的输出不再满足测试标准时，测试电路可操作以分析所选择的MEMS谐振器的输出并选择替换的MEMS谐振器。然后更换MEMS谐振器，并将其输出耦合到时钟发生器的输出端。因此，在其最终用途应用中的时钟发生器的操作期间，故障和潜在故障的MEMS谐振器被自动替换。

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