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81. 发明申请

US20100013005A1 INTEGRATED CIRCUIT INCLUDING A VERTICAL TRANSISTOR AND METHOD 有权
标题翻译：集成电路，包括垂直晶体管和方法
公开(公告)号：US20100013005A1
公开(公告)日：2010-01-21
申请号：US12173524
申请日：2008-07-15
申请人： Wolfgang Roesner , Franz Hofmann
发明人： Wolfgang Roesner , Franz Hofmann
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7827 , H01L21/2255 , H01L27/108 , H01L27/10802 , H01L27/10876 , H01L29/0878 , H01L29/0886 , H01L29/1083 , H01L29/1095 , H01L29/41766 , H01L29/42356 , H01L29/66734 , H01L29/7813
摘要： An integrated circuit including a vertical transistor and method of manufacturing. In one embodiment a vertical transistor is formed in a pillar of a semiconductor substrate. A buried conductive line is separated from the semiconductor substrate by a first insulating layer in a first portion and is electrically coupled to a buried source/drain region of the vertical transistor through a contact structure. A second insulating layer is arranged above and adjacent to the contact structure. At least one of the first and second insulating layers includes a dopant. A doped region is formed in the semiconductor substrate at an interface to the at least one insulating layer. The doped region has a dopant concentration higher than a substrate dopant concentration.
摘要翻译：一种包括垂直晶体管和制造方法的集成电路。在一个实施例中，垂直晶体管形成在半导体衬底的柱中。埋入导线通过第一部分中的第一绝缘层与半导体衬底分离，并通过接触结构电耦合到垂直晶体管的掩埋源/漏区。第二绝缘层布置在接触结构的上方并与之相邻。第一和第二绝缘层中的至少一个包括掺杂剂。掺杂区域形成在半导体衬底中与至少一个绝缘层的界面处。掺杂区域的掺杂浓度高于衬底掺杂剂浓度。

82. 发明授权

US07611928B2 Method for producing a substrate 有权
标题翻译：制造基板的方法
公开(公告)号：US07611928B2
公开(公告)日：2009-11-03
申请号：US10968846
申请日：2004-10-18
申请人： Franz Hofmann , Richard Johannes Luyken , Wolfgang Roesner , Michael Specht , Martin Stadele
发明人： Franz Hofmann , Richard Johannes Luyken , Wolfgang Roesner , Michael Specht , Martin Stadele
IPC分类号： H01L21/00
CPC分类号： H01L21/76254
摘要： Substrate having a first partial substrate with a carrier layer and a second partial substrate, which is bonded to the first partial substrate. The second partial substrate has an insulator layer, which is applied on the carrier layer and has at least two regions each having a different thickness, thereby forming a stepped surface of the insulator layer, and a semiconductor layer, which is applied to the stepped surface of the insulator layer and is formed at least partially epitaxially, wherein the semiconductor layer has a planar surface which is opposite to the stepped surface of the insulator layer. Transistors are formed on the semiconductor layer.
摘要翻译：衬底，具有第一部分衬底和载体层，第二部分衬底与第一部分衬底结合。第二部分基板具有绝缘体层，其被施加在载体层上并且具有至少两个各自具有不同厚度的区域，从而形成绝缘体层的台阶表面，以及施加到台阶表面的半导体层并且至少部分地外延形成，其中半导体层具有与绝缘体层的台阶表面相对的平面。在半导体层上形成晶体管。

83. 发明授权

US07598543B2 Semiconductor memory component with body region of memory cell having a depression and a graded dopant concentration 失效
标题翻译：具有存储单元体区域的半导体存储器组件具有凹陷和渐变的掺杂剂浓度
公开(公告)号：US07598543B2
公开(公告)日：2009-10-06
申请号：US11438883
申请日：2006-05-23
申请人： Franz Hofmann , Richard Johannes Luyken , Wolfgang Roesner , Michael Specht , Martin Staedele
发明人： Franz Hofmann , Richard Johannes Luyken , Wolfgang Roesner , Michael Specht , Martin Staedele
IPC分类号： H01L27/108
CPC分类号： H01L27/108 , H01L27/10802 , H01L27/1203
摘要： A semiconductor memory component comprises at least one memory cell. The memory cell comprises a semiconductor body comprised of a body region, a drain region and a source region, a gate dielectric, and a gate electrode. The body region comprises a first conductivity type and a depression between the source and drain regions, and the source and drain regions comprise a second conductivity type. The gate electrode is arranged at least partly in the depression and is insulated from the body, source, and drain regions by the gate dielectric. The body region further comprises a first continuous region with a first dopant concentration and a second continuous region with a second dopant concentration greater than the first dopant concentration. The first continuous region adjoins the drain region, the depression and the source region, and the second region is arranged below the first region and adjoins the first region.
摘要翻译：半导体存储器组件包括至少一个存储单元。存储单元包括由体区，漏区和源区组成的半导体本体，栅电介质和栅电极。主体区域包括第一导电类型和源极和漏极区域之间的凹陷，并且源极和漏极区域包括第二导电类型。栅电极至少部分地布置在凹陷中，并且通过栅极电介质与主体，源极和漏极区绝缘。体区还包括具有第一掺杂剂浓度的第一连续区域和具有大于第一掺杂剂浓度的第二掺杂剂浓度的第二连续区域。第一连续区域邻接漏极区域，凹陷部分和源极区域，并且第二区域布置在第一区域下方并与第一区域相邻。

84. 发明申请

US20080195368A1 METHOD, SYSTEM AND PROGRAM PRODUCT FOR SELECTIVELY REMOVING INSTRUMENTATION LOGIC FROM A SIMULATION MODEL 审中-公开
标题翻译：用于从模拟模型中选择性地去除仪器逻辑的方法，系统和程序产品
公开(公告)号：US20080195368A1
公开(公告)日：2008-08-14
申请号：US12060717
申请日：2008-04-01
申请人： GABOR BOBOK , Wolfgang Roesner , Matyas A. Sustik , Derek E. Williams
发明人： GABOR BOBOK , Wolfgang Roesner , Matyas A. Sustik , Derek E. Williams
IPC分类号： G06G7/48
CPC分类号： G06F17/5022
摘要： According to a method of simulation processing, a simulation model is received that includes a plurality of design entity instances modeling a digital system and one or more instrumentation entity instances, separate from the plurality of design entity instances, that generate instances of instrumentation events for testing purposes during simulation. In response to receiving an exclusion list identifying at least one instance of one or more instrumentation events to be removed from the simulation model, at least one instance of the one or more instrumentation events and associated logic elements are removed from the one or more instrumentation entity instances of the simulation model prior to simulation, such that a more compact simulation model is obtained.
摘要翻译：根据模拟处理的方法，接收模拟模型，其包括建立数字系统的多个设计实体实例和与多个设计实体实例分开的一个或多个仪表实体实例，其生成用于测试的仪表事件的实例模拟过程中的目的。响应于接收到排除列表，其识别要从仿真模型中移除的一个或多个仪器事件的至少一个实例，所述一个或多个检测事件和相关逻辑元件的至少一个实例从所述一个或多个检测实体中移除在模拟之前的仿真模型的实例，使得获得更紧凑的模拟模型。

85. 发明申请

US20070260443A1 METHOD, SYSTEM AND PROGRAM PRODUCT SUPPORTING SPECIFICATION OF SIGNALS FOR SIMULATION RESULT VIEWING 失效
标题翻译：方法，系统和程序产品支持模拟结果查看信号的规范
公开(公告)号：US20070260443A1
公开(公告)日：2007-11-08
申请号：US11381437
申请日：2006-05-03
申请人： Gabor Bobok , Wolfgang Roesner , Derek Williams
发明人： Gabor Bobok , Wolfgang Roesner , Derek Williams
IPC分类号： G06F17/50
CPC分类号： G06F17/5022
摘要： According to a method of data processing, a data set including at least one entry specifying a signal group by a predetermined signal group name is received by a data processing system. In response to receipt of the data set, the entry in the data set is processed to identify the signal group name. Signal group information associated with an event trace file containing simulation results is accessed to determine signal names of multiple signals that are members of the signal group. Simulation results from the event trace file that are associated with instances of said multiple signals are then included within a presentation of simulation results.
摘要翻译：根据数据处理的方法，由数据处理系统接收包括由预定信号组名称指定信号组的至少一个条目的数据集。响应于数据集的接收，处理数据集中的条目以识别信号组名称。与包含模拟结果的事件跟踪文件相关联的信号组信息被访问以确定作为信号组成员的多个信号的信号名称。然后将与所述多个信号的实例相关联的事件跟踪文件的仿真结果包括在仿真结果的呈现中。

86. 发明授权

US07208794B2 High-density NROM-FINFET 失效
标题翻译：高密度NROM-FINFET
公开(公告)号：US07208794B2
公开(公告)日：2007-04-24
申请号：US11073017
申请日：2005-03-04
申请人： Franz Hofmann , Erhard Landgraf , Richard Johannes Luyken , Wolfgang Roesner , Michael Specht
发明人： Franz Hofmann , Erhard Landgraf , Richard Johannes Luyken , Wolfgang Roesner , Michael Specht
IPC分类号： H01L29/76 , H01L29/788 , H01L29/792 , H01L29/94 , H01L31/119
CPC分类号： H01L21/28273 , G11C16/0466 , H01L21/28282 , H01L21/845 , H01L27/115 , H01L27/11521 , H01L27/11568 , H01L27/1203 , H01L29/66795 , H01L29/66825 , H01L29/66833 , H01L29/785 , H01L29/7881 , H01L29/792 , Y10S257/903 , Y10S257/904 , Y10S257/905
摘要： Semiconductor memory having memory cells, each including first and second conductively-doped contact regions and a channel region arranged between the latter, formed in a web-like rib made of semiconductor material and arranged one behind the other in this sequence in the longitudinal direction of the rib. The rib has an essentially rectangular shape with an upper side of the rib and rib side faces lying opposite. A memory layer is configured for programming the memory cell, arranged on the upper side of the rib spaced apart by a first insulator layer, and projects in the normal direction of the one rib side face over one of the rib side faces so that the one rib side face and the upper side of the rib form an edge for injecting charge carriers from the channel region into the memory layer. A gate electrode is spaced apart from the one rib side face by a second insulator layer and from the memory layer by a third insulator layer, electrically insulated from the channel region, and configured to control its electrical conductivity.
摘要翻译：具有存储单元的半导体存储器，每个存储单元包括第一和第二导电掺杂的接触区域和布置在其间的沟道区域，所述沟道区域形成在由半导体材料制成的网状肋状物中，肋骨肋具有基本上矩形的形状，肋的上侧和肋侧面相对。存储层被配置为对存储单元进行编程，布置在由第一绝缘体层间隔开的肋的上侧，并且沿着一个肋侧面的一个肋侧面的法线方向突出，使得一个肋侧面和肋的上侧形成用于将电荷载流子从沟道区域注入到存储层中的边缘。栅电极通过第二绝缘体层与一个肋侧面间隔开，并且通过与沟道区电绝缘并且被配置为控制其导电性的第三绝缘体层与存储层隔开。

87. 发明申请

US20070061121A1 Method, system and program product for selectively removing instrumentation logic from a simulation model 失效
标题翻译：用于从仿真模型中选择性地移除仪表逻辑的方法，系统和程序产品
公开(公告)号：US20070061121A1
公开(公告)日：2007-03-15
申请号：US11226969
申请日：2005-09-15
申请人： Gabor Bobok , Wolfgang Roesner , Matyas Sustik , Derek Williams
发明人： Gabor Bobok , Wolfgang Roesner , Matyas Sustik , Derek Williams
IPC分类号： G06F17/50
CPC分类号： G06F17/5022
摘要： According to a method of simulation processing, a simulation model is received that includes a plurality of design entity instances modeling a digital system and one or more instrumentation entity instances, separate from the plurality of design entity instances, that generate instances of instrumentation events for testing purposes during simulation. In response to receiving an exclusion list identifying at least one instance of one or more instrumentation events to be removed from the simulation model, at least one instance of the one or more instrumentation events and associated logic elements are removed from the one or more instrumentation entity instances of the simulation model prior to simulation, such that a more compact simulation model is obtained.
摘要翻译：根据模拟处理的方法，接收模拟模型，其包括建立数字系统的多个设计实体实例和与多个设计实体实例分开的一个或多个仪表实体实例，其生成用于测试的仪表事件的实例模拟过程中的目的。响应于接收到排除列表，其识别要从仿真模型中移除的一个或多个仪器事件的至少一个实例，所述一个或多个检测事件和相关逻辑元件的至少一个实例从所述一个或多个检测实体中移除在模拟之前的仿真模型的实例，使得获得更紧凑的模拟模型。

88. 发明申请

US20060026548A1 Method, system and program product for providing a configuration specification language supporting selective presentation of configuration entities 有权
标题翻译：用于提供支持配置实体的选择性呈现的配置规范语言的方法，系统和程序产品
公开(公告)号：US20060026548A1
公开(公告)日：2006-02-02
申请号：US10902595
申请日：2004-07-29
申请人： Wolfgang Roesner , Derek Williams
发明人： Wolfgang Roesner , Derek Williams
IPC分类号： G06F17/50
CPC分类号： G06F17/5022
摘要： In at least one hardware definition language (HDL) file, at least one design entity containing a functional portion of a digital system is specified. The design entity logically contains a latch having a respective plurality of different possible latch values. With one or more statements in one or more files, a configuration entity is associated with the latch. The configuration entity has a plurality of different settings and each setting reflects which of the plurality of different possible values is loaded in the associated latch. A controlling value set for at least one instance of the configuration entity is also defined in one or more files. The controlling value set indicates at least one controlling value for which presentation of a current setting of the configuration entity instance is restricted. Thereafter, in response to a request to present at least a partial state of the digital system, a current setting of the configuration entity instance is excluded from presentation by reference to a configuration database indicating the controlling value set.
摘要翻译：在至少一个硬件定义语言（HDL）文件中，指定包含数字系统的功能部分的至少一个设计实体。设计实体逻辑地包含具有相应多个不同可能锁存值的锁存器。在一个或多个文件中使用一个或多个语句，配置实体与锁存器相关联。配置实体具有多个不同的设置，并且每个设置反映多个不同的可能值中的哪一个加载到相关联的锁存器中。对于配置实体的至少一个实例设置的控制值也被定义在一个或多个文件中。控制值集合指示限制配置实体的当前设置的呈现的至少一个控制值。此后，响应于呈现数字系统的至少部分状态的请求，通过参考指示控制值集合的配置数据库将配置实体实例的当前设置排除在呈现之外。

89. 发明申请

US20060022275A1 Planar dual-gate transistor and method for fabricating a planar dual-gate transistor 审中-公开
标题翻译：平面双栅晶体管和制造平面双栅晶体管的方法
公开(公告)号：US20060022275A1
公开(公告)日：2006-02-02
申请号：US11177235
申请日：2005-07-07
申请人： Gurkan llicali , Richard Luyken , Wolfgang Roesner
发明人： Gurkan llicali , Richard Luyken , Wolfgang Roesner
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/66772 , H01L29/66628 , H01L29/78618 , H01L29/78648
摘要： A method for fabricating a double-gate transistor including defining an active area on an SOI substrate, forming a first gate region on the SOI substrate, forming source/drain regions made of silicon-germanium in the active area, forming a channel region from the silicon layer of the SOI substrate, forming a layer having a planar surface above the SOI substrate, the source/drain regions, and the first gate region, bonding a second wafer to the planar surface, and forming a second gate region opposite the first gate region.
摘要翻译：一种用于制造双栅极晶体管的方法，包括在SOI衬底上限定有源区，在SOI衬底上形成第一栅极区，在有源区中形成由硅 - 锗制成的源极/漏极区，从而形成来自硅层，形成在SOI衬底上方具有平坦表面的层，源极/漏极区和第一栅极区，将第二晶片接合到平坦表面，以及形成与第一栅极相对的第二栅极区地区。

90. 发明申请

US20060015314A1 Methods, systems and program products for annotating system traces with control program information and presenting annotated system traces 审中-公开
标题翻译：方法，系统和程序产品，用于通过控制程序信息注释系统跟踪并显示注释的系统跟踪
公开(公告)号：US20060015314A1
公开(公告)日：2006-01-19
申请号：US10880730
申请日：2004-06-30
申请人： Wolfgang Roesner , Derek Williams
发明人： Wolfgang Roesner , Derek Williams
IPC分类号： G06F9/45
CPC分类号： G06F11/3664 , G06F11/3636
摘要： The signal state that a signal of interest within a system under test has during each of a plurality of cycles of operation of the system under test is stored in a trace file. In association with the signal state, information regarding a requested access to the signal state by a control program during a particular cycle among the plurality of cycles is also stored. From the trace files a presentation is generated that presents, for at least a signal of interest within the system under test, a plurality of signal state indications, each indicating a respective state that the signal had during a one of a plurality of cycles of operation of the system under test. The presentation also indicates, in a graphically distinctive manner, at least one cycle of operation during which a control program requested access to a state of the signal, so that the influence of the control program on the state of the system under test is visually apparent.
摘要翻译：被测系统中感兴趣的信号在被测系统的多个操作周期中的每一个期间的信号状态被存储在跟踪文件中。与信号状态相关联，还存储关于在多个周期中的特定周期期间由控制程序请求的访问信号状态的信息。从跟踪文件中产生一个演示文稿，对于至少在被测系统内感兴趣的信号，呈现多个信号状态指示，每个信号状态指示各自表示信号在多个操作周期之一中具有的状态的被测系统。演示文稿还以图形上独特的方式指示至少一个操作周期，在该周期期间控制程序请求访问信号的状态，使得控制程序对被测系统的状态的影响在视觉上是明显的。

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