专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20070061121A1 Method, system and program product for selectively removing instrumentation logic from a simulation model 失效
标题翻译：用于从仿真模型中选择性地移除仪表逻辑的方法，系统和程序产品
公开(公告)号：US20070061121A1
公开(公告)日：2007-03-15
申请号：US11226969
申请日：2005-09-15
申请人： Gabor Bobok , Wolfgang Roesner , Matyas Sustik , Derek Williams
发明人： Gabor Bobok , Wolfgang Roesner , Matyas Sustik , Derek Williams
IPC分类号： G06F17/50
CPC分类号： G06F17/5022
摘要： According to a method of simulation processing, a simulation model is received that includes a plurality of design entity instances modeling a digital system and one or more instrumentation entity instances, separate from the plurality of design entity instances, that generate instances of instrumentation events for testing purposes during simulation. In response to receiving an exclusion list identifying at least one instance of one or more instrumentation events to be removed from the simulation model, at least one instance of the one or more instrumentation events and associated logic elements are removed from the one or more instrumentation entity instances of the simulation model prior to simulation, such that a more compact simulation model is obtained.
摘要翻译：根据模拟处理的方法，接收模拟模型，其包括建立数字系统的多个设计实体实例和与多个设计实体实例分开的一个或多个仪表实体实例，其生成用于测试的仪表事件的实例模拟过程中的目的。响应于接收到排除列表，其识别要从仿真模型中移除的一个或多个仪器事件的至少一个实例，所述一个或多个检测事件和相关逻辑元件的至少一个实例从所述一个或多个检测实体中移除在模拟之前的仿真模型的实例，使得获得更紧凑的模拟模型。

2. 发明申请

US20070198566A1 Method and apparatus for efficient storage of hierarchical signal names 审中-公开
标题翻译：分层信号名称有效存储的方法和装置
公开(公告)号：US20070198566A1
公开(公告)日：2007-08-23
申请号：US11360905
申请日：2006-02-23
申请人： Matyas Sustik
发明人： Matyas Sustik
IPC分类号： G06F7/00
CPC分类号： G06F17/5045
摘要： A method, computer program product, and data processing system for efficiently storing a set of hierarchically-specified names in a modular hardware design are disclosed. In accordance with a preferred embodiment of the present invention, a data structure for storing the names is built from a master trie. The master trie is used to store names of instances of modules contained within the design. The node in the master trie corresponding to a particular instance name is associated with an additional trie (“class trie”) corresponding to the class of module to which that instance belongs. In this additional trie are stored the names of the individual signals associated with that class of module. Where there are multiple instances of the same class of module within a design, each instance name may be associated with a single class trie storing each of the individual signal names associated with that class of module.
摘要翻译：公开了一种用于在模块化硬件设计中有效地存储一组分级指定名称的方法，计算机程序产品和数据处理系统。根据本发明的优选实施例，用于存储名称的数据结构是由主特技构建的。主特技用于存储设计中包含的模块实例的名称。与特定实例名称相对应的主特技中的节点与对应于该实例所属的模块类的附加特里（“类别trie”）相关联。在这个附加的trie中存储与该类模块相关联的各个信号的名称。在设计中存在同一类模块的多个实例的情况下，每个实例名称可以与存储与该类模块相关联的每个单独信号名称的单个类别进行关联。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式