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81. 发明授权

US07012273B2 Phase change memory device employing thermal-electrical contacts with narrowing electrical current paths 有权
标题翻译：相变存储器件采用具有窄电流路径的热电接触
公开(公告)号：US07012273B2
公开(公告)日：2006-03-14
申请号：US10641431
申请日：2003-08-14
申请人： Bomy Chen
发明人： Bomy Chen
IPC分类号： H01L47/00
CPC分类号： H01L45/06 , H01L27/2436 , H01L45/1233 , H01L45/126 , H01L45/1273 , H01L45/144 , H01L45/1666
摘要： A phase changing memory device, and method of making the same, that includes contact holes formed in insulation material that extend down to and exposes source regions for adjacent FET transistors. Spacer material is disposed in the holes with surfaces that define openings each having a width that narrows along a depth of the opening. Lower electrodes are disposed in the holes. A layer of phase change memory material is disposed along the spacer material surfaces and along at least a portion of the lower electrodes. Upper electrodes are formed in the openings and on the phase change memory material layer. For each contact hole, the upper electrode and phase change memory material layer form an electrical current path that narrows in width as the current path approaches the lower electrode, such that electrical current passing through the current path generates heat for heating the phase change memory material disposed between the upper and lower electrodes.
摘要翻译：相变存储器件及其制造方法，其包括形成在绝缘材料中的接触孔，所述绝缘材料向下延伸并暴露相邻FET晶体管的源极区域。间隔件材料设置在孔中，其表面限定开口，每个开口具有沿着开口的深度变窄的宽度。下电极设置在孔中。一层相变记忆材料沿着间隔材料表面并沿着下电极的至少一部分设置。上部电极形成在开口部和相变记忆材料层上。对于每个接触孔，上电极和相变存储材料层形成当电流路径接近下电极时宽度变窄的电流路径，使得通过电流路径的电流产生用于加热相变存储材料的热量设置在上电极和下电极之间。

82. 发明申请

US20060037940A1 Apparatus and method for shielding a wafer from charged particles during plasma etching 失效
标题翻译：在等离子体蚀刻期间屏蔽晶片与带电粒子的装置和方法
公开(公告)号：US20060037940A1
公开(公告)日：2006-02-23
申请号：US11260375
申请日：2005-10-28
申请人： Hongwen Yan , Brian Ji , Siddhartha Panda , Richard Wise , Bomy Chen
发明人： Hongwen Yan , Brian Ji , Siddhartha Panda , Richard Wise , Bomy Chen
IPC分类号： C23F1/00 , H01L21/306
CPC分类号： H01J37/32623 , H01J37/3266
摘要： A plasma etching system having a wafer chuck with a magnet that applies a magnetic field over a wafer to shield the wafer from charged particles. The magnetic field is parallel with the wafer, and is strongest near the wafer surface. The magnetic field may be straight, or circular. In operation, electrons are deflected from the wafer by the Lorentz force, the wafer acquires a positive charge, and ions are deflected by electrostatic repulsion. Neutral species are allowed through the magnetic field, and they collide with the wafer. Neutral species generally provide more isotropic and material-selective etching than charged particles, so the present magnetic field tends to increase etch isotropy and material selectivity. Also, the magnetic field can protect the wafer from seasoning processes designed to clean unwanted films from the chamber surface as seasoning processes typically rely on etching by charged particles.
摘要翻译：一种等离子体蚀刻系统，其具有带有磁体的晶片卡盘，该磁体在晶片上施加磁场以将晶片免受带电粒子的影响。磁场与晶片平行，并且在晶片表面附近最强。磁场可以是直的或圆形的。在操作中，电子通过洛伦兹力从晶片偏转，晶片获得正电荷，离子被静电排斥偏转。允许中性物质通过磁场，并且它们与晶片碰撞。中性物质通常提供比带电粒子更多的各向同性和材料选择性蚀刻，因此目前的磁场倾向于增加蚀刻各向同性和材料选择性。此外，由于调味过程通常依赖于带电粒子的蚀刻，所以磁场可以保护晶片免受调节过程的调节过程，以便从室表面清洁不需要的膜。

83. 发明申请

US20050213386A1 Nonvolatile memory cell having floating gate, control gate and separate erase gate, an array of such memory cells, and method of manufacturing 有权
公开(公告)号：US20050213386A1
公开(公告)日：2005-09-29
申请号：US11078562
申请日：2005-02-28
申请人： Amitay Levi , Pavel Klinger , Bomy Chen , Hieu Tran , Dana Lee , Jack Frayer
发明人： Amitay Levi , Pavel Klinger , Bomy Chen , Hieu Tran , Dana Lee , Jack Frayer
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/423 , H01L29/788 , G11C16/04
CPC分类号： H01L27/11521 , H01L27/115 , H01L29/42328 , H01L29/7885
摘要： A nonvolatile memory cell having a floating gate for the storage of charges thereon has a control gate and a separate erase gate. The cell is programmed by hot channel electron injection and is erased by poly to poly Fowler-Nordheim tunneling. A method for making an array of unidirectional cells in a planar substrate, as well as an array of bidirectional cells in a substrate having a trench, is disclosed. An array of such cells and a method of making such an array is also disclosed.

84. 发明授权

US06927410B2 Memory device with discrete layers of phase change memory material 有权
标题翻译：具有离散层的相变存储器材料的存储器件
公开(公告)号：US06927410B2
公开(公告)日：2005-08-09
申请号：US10656668
申请日：2003-09-04
申请人： Bomy Chen
发明人： Bomy Chen
IPC分类号： H01L23/48 , H01L27/24 , H01L45/00 , H01L47/00
CPC分类号： H01L45/144 , G11C13/0004 , H01L27/2436 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/1273 , H01L45/1683 , H01L2924/0002 , H01L2924/00
摘要： A phase changing memory device, and method of making the same, that includes programmable memory material disposed between a pair of electrodes. The programmable memory material includes discrete layers of phase change material, separated by conductive interface layers, that exhibits relatively stable resistivity values over discrete ranges of crystallizing and amorphousizing thermal pulses applied thereto, for multi-bit storage. The memory material and one of the electrodes can be disposed along spacer material surfaces to form an electrical current path that narrows in width as the current path approaches the other electrode, such that electrical current passing through the current path generates heat for heating the memory material disposed between the electrodes.
摘要翻译：相变存储器件及其制造方法，其包括设置在一对电极之间的可编程存储器材料。可编程存储器材料包括由导电界面层隔开的相变材料的离散层，其在施加到其上的结晶和非晶化热脉冲的离散范围上表现出相对稳定的电阻率值，用于多位存储。记忆材料和电极中的一个可以沿着间隔物材料表面设置，以形成当电流路径接近另一个电极时宽度变窄的电流路径，使得通过电流路径的电流产生用于加热存储材料的热量设置在电极之间。

85. 发明申请

US20050122771A1 MEMORY DEVICE AND METHOD OF OPERATING SAME 有权
标题翻译：存储器件及其操作方法
公开(公告)号：US20050122771A1
公开(公告)日：2005-06-09
申请号：US10729605
申请日：2003-12-05
申请人： Bomy Chen
发明人： Bomy Chen
IPC分类号： G11C11/00 , G11C16/02 , H01L27/24
CPC分类号： G11C13/004 , G11C13/0004 , G11C13/0069 , G11C2013/0054 , G11C2013/0078 , G11C2213/72 , G11C2213/77 , G11C2213/79 , H01L27/2454 , H01L27/2481 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/1273 , H01L45/144 , H01L45/1666
摘要： An array of phase changing memory cells that includes a current source, a voltage sensor, a plurality of conductive bit lines electrically connected to the current source, a plurality of conductive word lines each electrically connected to a ground plane via a first resistor and to the voltage sensor, and a plurality of memory cells. Each memory cell is connected between one of the bit lines and one of the word lines and includes phase change memory material. One of the memory cells is selected by turning on switches just on the bit line and word line connected thereto, or by turning a switch connected in series between the corresponding bit and word lines, where the read current flows through the selected memory cell and the voltage sensor measures a voltage drop across the selected memory cell.
摘要翻译：一种相变存储器单元的阵列，包括电流源，电压传感器，电连接到电流源的多个导电位线，多个导电字线，每个导电字线经由第一电阻器电连接到接地层，电压传感器和多个存储单元。每个存储单元连接在一个位线和一条字线之间，并且包括相变存储器材料。其中一个存储单元是通过接通开关位于与其连接的位线和字线上，或者通过将串联连接在相应的位和字线之间的开关转换开来来选择的，其中读取的电流流过选定的存储单元，电压传感器测量所选存储单元上的电压降。

86. 发明申请

US20050051901A1 Memory device with discrete layers of phase change memory material 有权
公开(公告)号：US20050051901A1
公开(公告)日：2005-03-10
申请号：US10656668
申请日：2003-09-04
申请人： Bomy Chen
发明人： Bomy Chen
IPC分类号： H01L23/48 , H01L27/24 , H01L45/00 , H01L47/00
CPC分类号： H01L45/144 , G11C13/0004 , H01L27/2436 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/1273 , H01L45/1683 , H01L2924/0002 , H01L2924/00
摘要： A phase changing memory device, and method of making the same, that includes programmable memory material disposed between a pair of electrodes. The programmable memory material includes discrete layers of phase change material, separated by conductive interface layers, that exhibits relatively stable resistivity values over discrete ranges of crystallizing and amorphousizing thermal pulses applied thereto, for multi-bit storage. The memory material and one of the electrodes can be disposed along spacer material surfaces to form an electrical current path that narrows in width as the current path approaches the other electrode, such that electrical current passing through the current path generates heat for heating the memory material disposed between the electrodes.

87. 发明申请

US20050045940A1 SELF-ALIGNED METHOD OF FORMING A SEMICONDUCTOR MEMORY ARRAY OF FLOATING GATE MEMORY CELLS WITH BURIED FLOATING GATE, AND A MEMORY ARRAY MADE THEREBY 有权
标题翻译：形成具有浮动门的浮动存储器存储器的半导体存储器阵列的自对准方法及其存储器阵列
公开(公告)号：US20050045940A1
公开(公告)日：2005-03-03
申请号：US10653015
申请日：2003-08-28
申请人： Bomy Chen , Dana Lee , Hieu Tran
发明人： Bomy Chen , Dana Lee , Hieu Tran
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/423 , H01L29/788
CPC分类号： H01L27/11556 , H01L27/115 , H01L29/42336 , H01L29/7885
摘要： An array of floating gate memory cells, and a method of making same, where each pair of memory cells includes a pair of trenches formed into a surface of a semiconductor substrate, with a strip of the substrate disposed therebetween, a source region formed in the substrate strip, a pair of drain regions, a pair of channel regions each extending between the source region and one of the drain regions, a pair of floating gates each disposed in one of the trenches, and a pair of control gates. Each channel region has a first portion disposed in the substrate strip and extending along one of the trenches, a second portion extending underneath the one trench, a third portion extending along the one trench, and a fourth portion extending along the substrate surface and under one of the control gates.
摘要翻译：一种浮动栅极存储单元的阵列及其制造方法，其中每对存储单元包括形成在半导体衬底的表面中的一对沟槽，其中衬底的条带设置在其间，源区域形成在衬底条，一对漏极区，一对沟道区，每个沟道区各自在源极区和漏极区之一之间延伸;一对浮置栅极，分别设置在一个沟槽中，以及一对控制栅极。每个通道区域具有设置在衬底条中并沿其中一个沟槽延伸的第一部分，在一个沟槽下面延伸的第二部分，沿该沟槽延伸的第三部分，以及沿衬底表面延伸的第四部分的控制门。

88. 发明授权

US06777260B1 Method of making sub-lithographic sized contact holes 有权
标题翻译：制作亚光刻尺寸接触孔的方法
公开(公告)号：US06777260B1
公开(公告)日：2004-08-17
申请号：US10641490
申请日：2003-08-14
申请人： Bomy Chen
发明人： Bomy Chen
IPC分类号： H01L2106
CPC分类号： H01L21/76802
摘要： A method of forming sub-lithographic sized contact holes in semiconductor material, which includes forming layers of etch mask materials, and forming intersecting first and second trenches in the etch mask layers, where through-holes are formed completely through the etch mask layers only where the first and second trenches intersect. The first and second trenches are made by the formation and subsequent removal of very thin vertical layers of material. The width dimensions of the trenches, and therefore of the through-holes, are sub-lithographic because they are dictated by the thickness of the thin vertical layers of material, and not by conventional photo lithographic processes used to form those vertical layers of material. The sub-lithographic through-holes are then used to etch sub-lithographic sized contact holes in underlying semiconductor materials.
摘要翻译：一种在半导体材料中形成次光刻尺寸的接触孔的方法，其包括形成蚀刻掩模材料层，并在蚀刻掩模层中形成相交的第一和第二沟槽，其中通孔仅完全穿过蚀刻掩模层，第一和第二沟槽相交。第一和第二沟槽通过形成并随后去除非常薄的垂直材料层而制成。沟槽的宽度尺寸，因此通孔的尺寸是亚光刻的，因为它们由薄的垂直材料层的厚度决定，而不是通过用于形成这些垂直材料层的常规光刻工艺。然后使用亚光刻通孔来蚀刻下面的半导体材料中的次光刻尺寸的接触孔。

89. 发明授权

US06294817B1 Source/drain-on insulator (S/DOI) field effect transistor using oxidized amorphous silicon and method of fabrication 失效
标题翻译：使用氧化非晶硅的源极/漏极绝缘体（S / DOI）场效应晶体管及其制造方法
公开(公告)号：US06294817B1
公开(公告)日：2001-09-25
申请号：US09459483
申请日：1999-12-13
申请人： Senthil Srinivasan , Bomy Chen
发明人： Senthil Srinivasan , Bomy Chen
IPC分类号： H01L2972
CPC分类号： H01L29/66636 , H01L29/0653
摘要： Source and drain regions of field effect transistors are fabricated with an electrically insulating layer formed thereunder so as to reduce junction capacitance between each and a semiconductor body in which the regions are formed. Shallow trench isolation partially surrounds each transistor so as to further electrically isolate the source and drain regions from the semiconductor body. Typically for a single transistor only one surface of each drain and source region make direct contact to the semiconductor body and these surfaces are on opposite sides of a channel region of each transistor. One method of fabrication of the source and drain regions is to form an isolating isolation region around active areas in which a transistor is to be formed in a semiconductor body. Trenches separated by portions of the body are then formed in the active areas in which transistors are to be formed. On bottom surfaces of the trenches are formed an electrically insulating layer. The trenches are then filled with semiconductor material of a conductivity type opposite that of the semiconductor body. The semiconductor filled portion of each trench then serves as a drain and/or source of a field effect transistor.
摘要翻译：场效应晶体管的源极和漏极区域由其下面形成的电绝缘层制造，以便减小其中形成区域的半导体本体之间的结电容。浅沟槽隔离部分地围绕每个晶体管，以进一步将源极和漏极区域与半导体本体电隔离。通常，对于单个晶体管，每个漏极和源极区域的仅一个表面与半导体本体直接接触，并且这些表面位于每个晶体管的沟道区域的相对侧上。源极和漏极区域的一种制造方法是在半导体本体内形成晶体管的有源区域周围形成隔离隔离区域。然后在其中将形成晶体管的有源区域中形成由身体的部分分开的沟槽。在沟槽的底表面上形成电绝缘层。然后用与半导体本体相反的导电类型的半导体材料填充沟槽。然后，每个沟槽的半导体填充部分用作场效应晶体管的漏极和/或源极。

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