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81. 发明授权

US08645889B2 Noise coupling reduction and impedance discontinuity control in high-speed ceramic modules 有权
标题翻译：高速陶瓷模块中的噪声耦合减小和阻抗不连续控制
公开(公告)号：US08645889B2
公开(公告)日：2014-02-04
申请号：US13449732
申请日：2012-04-18
申请人： Jinwoo Choi , Sungjun Chun , Anand Haridass , Roger Weekly
发明人： Jinwoo Choi , Sungjun Chun , Anand Haridass , Roger Weekly
IPC分类号： G06F17/50 , H05K1/00
CPC分类号： G06F17/5068 , G06F17/5036 , H01L23/552 , H01L2924/0002 , H01L2924/09701 , H01L2924/3011 , H05K1/0219 , H05K1/0224 , H05K3/4629 , H05K2201/09236 , H05K2201/09681 , H01L2924/00
摘要： A method reduces coupling noise and controls impedance discontinuity in ceramic packages by: providing at least one reference mesh layer; providing a plurality of signal trace layers, with each signal layer having one or more signal lines and the reference mesh layer being adjacent to one or more of the signal layers; disposing a plurality of vias through the at least one reference mesh layer, with each via providing a voltage (Vdd) power connection or a ground (Gnd) connection; selectively placing via-connected coplanar-type shield (VCS) lines relative to the signal lines, with a first VCS line extended along a first side of a first signal line and a second VCS line extended along a second, opposing side of said first signal line. Each of the VCS lines interconnect with and extend past one or more vias located within a directional path along which the VCS lines extends.
摘要翻译：一种方法通过以下方式减少耦合噪声并控制陶瓷封装中的阻抗不连续性：提供至少一个参考网格层; 提供多个信号迹线层，其中每个信号层具有一个或多个信号线，并且所述参考网格层与所述信号层中的一个或多个相邻; 通过所述至少一个参考网格层布置多个通孔，其中每个通孔提供电压（Vdd）电源连接或接地（Gnd）连接; 选择性地将通过连接的共面型屏蔽（VCS）线相对于信号线放置，其中第一VCS线沿着第一信号线的第一侧延伸，并且第二VCS线沿着所述第一信号的第二相对侧延伸线。 VCS线路中的每一条与位于VCS线延伸的定向路径内的一个或多个通孔相互连接并延伸。

82. 发明授权

US08638567B2 Circuit manufacturing and design techniques for reference plane voids with strip segment 失效
公开(公告)号：US08638567B2
公开(公告)日：2014-01-28
申请号：US13603732
申请日：2012-09-05
申请人： Sungjun Chun , Anand Haridass , Roger D. Weekly
发明人： Sungjun Chun , Anand Haridass , Roger D. Weekly
IPC分类号： H05K1/11
CPC分类号： G06F17/5077 , H05K1/0219 , H05K1/0237 , H05K1/0253 , H05K3/4602 , H05K3/4652 , H05K2201/09536 , H05K2201/09672 , H05K2201/0969 , H05K2201/09718 , Y10T29/49117 , Y10T29/49153 , Y10T29/49155 , Y10T29/49165 , Y10T428/24322
摘要： Manufacturing circuits with reference plane voids over vias with a strip segment interconnect permits routing critical signal paths over vias, while increasing via insertion capacitance only slightly. The transmission line reference plane defines voids above (or below) signal-bearing plated-through holes (PTHs) that pass through a rigid substrate core, so that the signals are not degraded by an impedance mismatch that would otherwise be caused by shunt capacitance from the top (or bottom) of the signal-bearing PTHs to the transmission line reference plane. In order to provide increased routing density, signal paths are routed over the voids, but disruption of the signal paths by the voids is prevented by including a conductive strip through the voids that reduces the coupling to the signal-bearing PTHs and maintains the impedance of the signal path conductor.

83. 发明申请

US20120331430A1 CIRCUIT MANUFACTURING AND DESIGN TECHNIQUES FOR REFERENCE PLANE VOIDS WITH STRIP SEGMENT 失效
公开(公告)号：US20120331430A1
公开(公告)日：2012-12-27
申请号：US13603761
申请日：2012-09-05
申请人： Sungjun Chun , Anand Haridass , Roger D. Weekly
发明人： Sungjun Chun , Anand Haridass , Roger D. Weekly
IPC分类号： G06F17/50
CPC分类号： G06F17/5077 , H05K1/0219 , H05K1/0237 , H05K1/0253 , H05K3/4602 , H05K3/4652 , H05K2201/09536 , H05K2201/09672 , H05K2201/0969 , H05K2201/09718 , Y10T29/49117 , Y10T29/49153 , Y10T29/49155 , Y10T29/49165 , Y10T428/24322
摘要： Manufacturing circuits with reference plane voids over vias with a strip segment interconnect permits routing critical signal paths over vias, while increasing via insertion capacitance only slightly. The transmission line reference plane defines voids above (or below) signal-bearing plated-through holes (PTHs) that pass through a rigid substrate core, so that the signals are not degraded by an impedance mismatch that would otherwise be caused by shunt capacitance from the top (or bottom) of the signal-bearing PTHs to the transmission line reference plane. In order to provide increased routing density, signal paths are routed over the voids, but disruption of the signal paths by the voids is prevented by including a conductive strip through the voids that reduces the coupling to the signal-bearing PTHs and maintains the impedance of the signal path conductor.

84. 发明授权

US08288657B2 Noise coupling reduction and impedance discontinuity control in high-speed ceramic modules 有权
标题翻译：高速陶瓷模块中的噪声耦合减小和阻抗不连续控制
公开(公告)号：US08288657B2
公开(公告)日：2012-10-16
申请号：US12577259
申请日：2009-10-12
申请人： Jinwoo Choi , Sungjun Chun , Anand Haridass , Roger Weekly
发明人： Jinwoo Choi , Sungjun Chun , Anand Haridass , Roger Weekly
IPC分类号： H05K1/00
CPC分类号： G06F17/5068 , G06F17/5036 , H01L23/552 , H01L2924/0002 , H01L2924/09701 , H01L2924/3011 , H05K1/0219 , H05K1/0224 , H05K3/4629 , H05K2201/09236 , H05K2201/09681 , H01L2924/00
摘要： An improved multi-layered ceramic package comprises: a plurality of signal layers, each having one or more signal lines; a plurality of vias, each providing one of a voltage (Vdd) power connection or a ground (Gnd) connection; at least one reference mesh layer adjacent to one or more signal layers; and a plurality of via-connected coplanar-type shield (VCS) lines, with a first VCS line extending on a first side of a first signal line within the plurality of signal layers and a second VCS line extending on a second opposing side of the first signal line. Each of the plurality of VCS lines interconnect with and extend past one or more vias that are located along the directional path in which the VCS lines runs. The placement of the VCS lines relative to the signal lines reduces coupling noise and controls impedance discontinuity in the ceramic package.
摘要翻译：一种改进的多层陶瓷封装包括：多个信号层，每个具有一个或多个信号线; 多个通孔，每个通孔提供电压（Vdd）电源连接或地（Gnd）连接中的一个; 与一个或多个信号层相邻的至少一个参考网格层; 以及多个通孔连接的共面型屏蔽（VCS）线，其中在所述多个信号层中的第一信号线的第一侧上延伸的第一VCS线和在所述多个信号层的第二相对侧上延伸的第二VCS线第一条信号线。多个VCS线路中的每一条与VCS线路运行的定向路径相互连接并延伸经过一个或多个通孔。 VCS线相对于信号线的放置减少了耦合噪声并且控制了陶瓷封装中的阻抗不连续性。

85. 发明授权

US08055486B2 Power delivery analysis and design 有权
标题翻译：电力分配和设计
公开(公告)号：US08055486B2
公开(公告)日：2011-11-08
申请号：US12187164
申请日：2008-08-06
申请人： Daniel Douriet , Anand Haridass , Andreas Huber , Colm B. O'Reilly , Bao Gia-Harvey Truong , Roger D. Weekly
发明人： Daniel Douriet , Anand Haridass , Andreas Huber , Colm B. O'Reilly , Bao Gia-Harvey Truong , Roger D. Weekly
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： A computer program product is provided for power delivery analysis and design for a hierarchical system. The product includes a storage medium, readable by a processing circuit, for storing instructions for execution by the processing circuit for facilitating a method. The method includes building a model corresponding to each element of the hierarchical system, and compiling a repository that contains models corresponding to each element, where the repository includes a net list, a domain list, a component list, a pin list, and a layer list. The method also includes performing optimized gridding for each element, the net list, the domain list, the component list, the pin list, and the layer list; assembling a system model from the models contained in the repository; flattening the system model by converting the system model to a flattened system model that consists entirely of resistors; and running a simulation on the flattened system model.
摘要翻译：提供计算机程序产品用于分层系统的功率传递分析和设计。该产品包括可由处理电路读取的存储介质，用于存储由处理电路执行以便于方法的指令。该方法包括构建与分级系统的每个元素相对应的模型，以及编译包含与每个元素对应的模型的仓库，其中仓库包括网络列表，域列表，组件列表，引脚列表和层列表。该方法还包括对每个元素，网络列表，域列表，组件列表，引脚列表和层列表执行优化的网格化; 从存储库中包含的模型组装系统模型; 通过将系统模型转换为完全由电阻组成的扁平化系统模型来平坦化系统模型; 并在扁平化系统模型上运行模拟。

86. 发明授权

US08050174B2 Self-healing chip-to-chip interface 失效
公开(公告)号：US08050174B2
公开(公告)日：2011-11-01
申请号：US12886404
申请日：2010-09-20
申请人： Wiren D. Becker , Daniel M. Dreps , Frank D. Ferraiolo , Anand Haridass , Robert J. Reese
发明人： Wiren D. Becker , Daniel M. Dreps , Frank D. Ferraiolo , Anand Haridass , Robert J. Reese
IPC分类号： G01R31/08
CPC分类号： H01L22/22 , H01L2924/0002 , H01L2924/00
摘要： A method, apparatus, and computer instructions for managing a set of signal paths for a chip. A defective signal path within the set of signal paths for the chip is detected. Signals are re-routed through the set of signal paths such that the defective signal path is removed from the set of signal paths and sending signals using remaining data signal paths in the set of signal paths and using an extra signal path in response to detecting the defective signal path.

87. 发明申请

US20110147068A1 Structure for Enhancing Reference Return Current Conduction 失效
标题翻译：用于增强参考回归电流传导的结构
公开(公告)号：US20110147068A1
公开(公告)日：2011-06-23
申请号：US12641381
申请日：2009-12-18
申请人： Joseph J. Cahill , Anand Haridass , Roger D. Weekly
发明人： Joseph J. Cahill , Anand Haridass , Roger D. Weekly
IPC分类号： H05K1/11 , G06F17/50
CPC分类号： H05K1/0251 , G06F17/5077 , H05K1/162 , H05K2201/09509 , H05K2201/09536
摘要： An apparatus is provided that comprises a plurality of signaling planes providing signal pathways and at least one internal reference plane providing either a voltage or a ground connection. The at least one internal reference plane are provided between at least two of the signaling planes. The apparatus further comprises a signal blind/buried via coupling a signal pathway of a first one of the at least two signaling planes with a signal pathway of a second one of the at least two signaling planes. The blind/buried via runs through the at least one internal reference plane. The apparatus also comprises at least one first conductive feature in the first one of the at least two signaling planes. The at least one first conductive feature is in close proximity to the signal blind/buried via and increases the capacitive coupling of currents in the reference planes of the apparatus.
摘要翻译：提供了一种装置，其包括提供信号路径的多个信令平面和提供电压或接地连接的至少一个内部参考平面。所述至少一个内部参考平面设置在至少两个信令平面之间。该装置还包括通过将至少两个信令平面中的第一个信号平面的第一信号平面的信号路径与至少两个信令平面中的第二信号平面的信号路径耦合而进行信号盲/掩蔽。盲/埋通孔穿过至少一个内部参考平面。该装置还包括至少两个信令平面中的第一个中的至少一个第一导电特征。至少一个第一导电特征与信号盲/掩埋通孔紧密接近，并且增加了装置参考平面中电流的电容耦合。

88. 发明授权

US07945881B2 Method of reducing crosstalk induced noise in circuitry designs 有权
标题翻译：减少电路设计中串扰引起的噪声的方法
公开(公告)号：US07945881B2
公开(公告)日：2011-05-17
申请号：US11961440
申请日：2007-12-20
申请人： Sungjun Chun , Anand Haridass , Jesus Montanez , Xiaomin Shen
发明人： Sungjun Chun , Anand Haridass , Jesus Montanez , Xiaomin Shen
IPC分类号： G06F17/50
CPC分类号： G06F17/5036 , G06F17/5077
摘要： A method of reducing crosstalk induced noise in a physical circuit wiring design constructs a spatial vector for each interconnect wire segment in the physical circuit wiring design. The method compares the spatial vectors of said physical circuit wiring design and identifies any of the spatial vectors that are parallel to each other and have opposite directions. The method may identify all drivers and receivers in the physical circuit wiring design, and trace each interconnect line, starting with its driver, to determine a routed length from the driver to each segment break point of the interconnect line. The method may construct the spatial vector by defining an origin in the physical circuit wiring design. The method determines a starting point and an ending point of the spatial vector with respect to the origin. The starting point of the spatial vector is the break point of the interconnect wire segment closer to the driver. The ending point of the spatial vector is the break point of the interconnect wire segment farther from the driver. The method may define a Cartesian coordinate system with respect to the origin. The Cartesian coordinate system may be orthogonal with the interconnect wire segments of the physical circuit wiring design. The method may define one or more geometry windows in the physical circuit wiring design and compare the spatial vectors in each geometry window.
摘要翻译：在物理电路布线设计中减少串扰引起的噪声的方法在物理电路布线设计中为每个互连线段构造空间矢量。该方法比较了所述物理电路布线设计的空间矢量，并且识别彼此平行且具有相反方向的任何空间矢量。该方法可以识别物理电路布线设计中的所有驱动器和接收器，并且从其驱动器开始追踪每个互连线，以确定从驱动器到互连线的每个段断点的路由长度。该方法可以通过在物理电路布线设计中定义原点来构造空间矢量。该方法确定相对于原点的空间矢量的起始点和终点。空间矢量的起始点是互连线段靠近驾驶员的断点。空间矢量的终点是互连线段远离驾驶员的断点。该方法可以相对于原点定义笛卡尔坐标系。笛卡尔坐标系可以与物理电路布线设计的互连线段正交。该方法可以在物理电路布线设计中定义一个或多个几何窗口并比较每个几何窗口中的空间矢量。

89. 发明申请

US20110083888A1 Noise Coupling Reduction and Impedance Discontinuity Control in High-Speed Ceramic Modules 有权
标题翻译：高速陶瓷模块的噪声耦合降低和阻抗不连续控制
公开(公告)号：US20110083888A1
公开(公告)日：2011-04-14
申请号：US12577259
申请日：2009-10-12
申请人： Jinwoo Choi , Sungjun Chun , Anand Haridass , Roger Weekly
发明人： Jinwoo Choi , Sungjun Chun , Anand Haridass , Roger Weekly
IPC分类号： H05K1/02 , H05K3/10 , G06F17/50
CPC分类号： G06F17/5068 , G06F17/5036 , H01L23/552 , H01L2924/0002 , H01L2924/09701 , H01L2924/3011 , H05K1/0219 , H05K1/0224 , H05K3/4629 , H05K2201/09236 , H05K2201/09681 , H01L2924/00
摘要： An improved multi-layered ceramic package comprises: a plurality of signal layers, each having one or more signal lines; a plurality of vias, each providing one of a voltage (Vdd) power connection or a ground (Gnd) connection; at least one reference mesh layer adjacent to one or more signal layers; and a plurality of via-connected coplanar-type shield (VCS) lines, with a first VCS line extending on a first side of a first signal line within the plurality of signal layers and a second VCS line extending on a second opposing side of the first signal line. Each of the plurality of VCS lines interconnect with and extend past one or more vias that are located along the directional path in which the VCS lines runs. The placement of the VCS lines relative to the signal lines reduces coupling noise and controls impedance discontinuity in the ceramic package.
摘要翻译：一种改进的多层陶瓷封装包括：多个信号层，每个具有一个或多个信号线; 多个通孔，每个通孔提供电压（Vdd）电源连接或地（Gnd）连接中的一个; 与一个或多个信号层相邻的至少一个参考网格层; 以及多个通孔连接的共面型屏蔽（VCS）线，其中在所述多个信号层中的第一信号线的第一侧上延伸的第一VCS线和在所述多个信号层的第二相对侧上延伸的第二VCS线第一条信号线。多个VCS线路中的每一条与VCS线路运行的定向路径相互连接并延伸经过一个或多个通孔。 VCS线相对于信号线的放置减少了耦合噪声并且控制了陶瓷封装中的阻抗不连续性。

90. 发明授权

US07904849B2 Ceramic package in which far end noise is reduced using capacitive cancellation by offset wiring 有权
标题翻译：陶瓷封装，其中通过偏移布线使用电容消除来减少远端噪声
公开(公告)号：US07904849B2
公开(公告)日：2011-03-08
申请号：US11951705
申请日：2007-12-06
申请人： Anand Haridass , Andreas Huber , Bao G. Truong , Roger D. Weekly
发明人： Anand Haridass , Andreas Huber , Bao G. Truong , Roger D. Weekly
IPC分类号： G06F17/50 , G06F9/45
CPC分类号： H01L23/50 , H01L2924/0002 , H01L2924/09701 , H01L2924/3011 , Y10T29/49155 , Y10T29/49163 , H01L2924/00
摘要： A mechanism for reducing the vertical cross-talk interference experienced in signal lines due to the inductive affects from signal lines in other signal planes of a multi-layer ceramic package is provided. With the apparatus and method, one or more vias in the multi-layer ceramic package may be removed from the structure to provide area through which an offset of the signal lines may pass. Because these offsets of the signal lines exist in parallel planes above or below each other, with no ground lines existing directly between these signal line offsets, a capacitive cross-talk is introduced into the signal lines. This capacitive cross-talk is opposite in polarity to the inductive cross-talk already experienced by the signal lines. As a result, the capacitive cross-talk tends to negate or reduce the inductive cross-talk thereby reducing the far end noise in the signal line.
摘要翻译：提供了一种用于减少由于来自多层陶瓷封装的其它信号面中的信号线的感应影响而在信号线中遭受的垂直串扰干扰的机制。利用该装置和方法，多层陶瓷封装中的一个或多个通孔可以从结构中移除以提供信号线的偏移通过的区域。由于信号线的这些偏移存在于彼此之上或之下的并行平面中，在这些信号线偏移之间没有直接存在接地线，所以在信号线中引入电容性串扰。该电容串扰与信号线已经经历的电感串扰的极性相反。结果，电容串扰倾向于消除或减少电感串扰，从而减少信号线中的远端噪声。

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