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81. 发明申请

US20130320945A1 STRUCTURE AND METHOD FOR A SWITCHED CIRCUIT DEVICE 有权
标题翻译：一种开关电路设备的结构和方法
公开(公告)号：US20130320945A1
公开(公告)日：2013-12-05
申请号：US13599909
申请日：2012-08-30
申请人： Alexander Kalnitsky
发明人： Alexander Kalnitsky
IPC分类号： G05F1/46
CPC分类号： H02M3/155 , H01L29/78 , H01L29/7816
摘要： The present disclosure provides a switched voltage converter for receiving a source voltage and producing an output voltage. The voltage converter comprises a switch controller and a switched device communicatively coupled to the switch controller. The switch controller adjusts the output voltage by controlling a duty cycle of the switched device. The switched device is sized such that it is characterized by a drain-to-source breakdown voltage greater than or substantially equal to the source voltage and the output voltage and is further characterized by a hot-carrier injection rating less than the source voltage or the output voltage. In further embodiments, the switched device is sized such that it is characterized by a drain-to-source breakdown voltage greater than or substantially equal to a peak operating voltage and is further characterized by a hot-carrier injection rating less than the peak operating voltage.
摘要翻译：本公开提供了一种用于接收源极电压并产生输出电压的开关电压转换器。电压转换器包括开关控制器和通信地耦合到开关控制器的开关装置。开关控制器通过控制开关器件的占空比来调节输出电压。开关器件的尺寸使得其特征在于漏极 - 源极击穿电压大于或基本上等于源极电压和输出电压，并且进一步的特征在于热载流子注入额定值小于源极电压或输出电压。在另外的实施例中，开关器件的尺寸使得其特征在于漏极 - 源极击穿电压大于或基本上等于峰值工作电压，并且进一步的特征在于小于峰值工作电压的热载流子注入额定值。

82. 发明授权

US08549922B2 Motion detection using capacitor having different work function materials 有权
标题翻译：运动检测使用电容器具有不同的功能材料
公开(公告)号：US08549922B2
公开(公告)日：2013-10-08
申请号：US12720813
申请日：2010-03-10
申请人： Alexander Kalnitsky , Fu-Lung Hsueh
发明人： Alexander Kalnitsky , Fu-Lung Hsueh
IPC分类号： G01P15/125
CPC分类号： G01B7/003 , A63F13/06 , A63F13/211 , A63F13/24 , A63F2300/1043 , A63F2300/105 , G01P3/52 , G01P15/125 , G01P15/16
摘要： An apparatus for detecting mechanical displacement in a micro-electromechanical system includes a capacitor having first and second plates spaced from one another, the first and second plates having different work functions and being electrically connected with each other. The capacitor plates are movable with respect to one another such that a spacing between the plates changes in response to a force. A current through the capacitor represents a rate of change in the spacing between the plates at a given time.
摘要翻译：一种用于检测微机电系统中的机械位移的装置包括具有彼此间隔开的第一和第二板的电容器，所述第一和第二板具有不同的功函数并且彼此电连接。电容器板可以相对于彼此移动，使得板之间的间隔响应于力而变化。通过电容器的电流表示给定时间间板间距的变化率。

83. 发明授权

US08325522B2 Memory array of floating gate-based non-volatile memory cells 有权
标题翻译：基于浮动栅极的非易失性存储单元的存储器阵列
公开(公告)号：US08325522B2
公开(公告)日：2012-12-04
申请号：US13012361
申请日：2011-01-24
申请人： Hosam Haggag , Alexander Kalnitsky , Edgardo Laber , Michael D. Church , Yun Yue
发明人： Hosam Haggag , Alexander Kalnitsky , Edgardo Laber , Michael D. Church , Yun Yue
IPC分类号： G11C16/04 , G11C16/06
CPC分类号： G11C16/0433
摘要： A memory array comprises a plurality of memory cells organized in a matrix of rows and columns. Each of the memory cells includes a high voltage access transistor, a floating gate memory transistor electrically connected to the access transistor, and a coupling capacitor electrically connected to the memory transistor. A first set of word lines are each electrically connected to the capacitor in each of the memory cells in a respective row. A second set of word lines are each electrically connected to the access transistor in each of the memory cells in a respective row. A first set of bit lines are each electrically connected to the access transistor in each of the memory cells in a respective column. A second set of bit lines are each electrically connected to the memory transistor in each of the memory cells in a respective column. Various combinations of voltages can be applied to the word lines and bit lines in operations to program, erase, read, or inhibit a logic state stored by the memory transistor in one or more of the memory cells.
摘要翻译：存储器阵列包括以行和列的矩阵组织的多个存储器单元。每个存储单元包括高电压存取晶体管，电连接到存取晶体管的浮动栅极存储晶体管和电连接到存储晶体管的耦合电容器。第一组字线分别电连接到相应行中的每个存储器单元中的电容器。第二组字线各自电连接到相应行中的每个存储单元中的存取晶体管。第一组位线分别电连接到相应列中每个存储单元中的存取晶体管。第二组位线分别电连接到相应列中每个存储器单元中的存储晶体管。在操作中可以对字线和位线施加电压的各种组合，以对存储器晶体管存储在一个或多个存储器单元中的逻辑状态进行编程，擦除，读取或禁止。

84. 发明申请

US20120122308A1 METHOD OF MANUFACTURING JUNCTION BARRIER SCHOTTKY DIODE WITH DUAL SILICIDES 有权
标题翻译：制造双晶硅二极管肖特基二极管的方法
公开(公告)号：US20120122308A1
公开(公告)日：2012-05-17
申请号：US13356624
申请日：2012-01-23
申请人： Dev Alok Girdhar , Michael David Church , Alexander Kalnitsky
发明人： Dev Alok Girdhar , Michael David Church , Alexander Kalnitsky
IPC分类号： H01L21/8222
CPC分类号： H01L29/872 , H01L27/0629 , H01L29/456 , H01L29/47 , H01L29/7833
摘要： An integrated circuit, including a junction barrier Schottky diode, has an N type well, a P-type anode region in the surface of the well, and an N-type Schottky region in the surface of the well and horizontally abutting the anode region. A first silicide layer is on and makes a Schottky contact to the Schottky region and is on an adjoining anode region. A second silicide layer of a different material than the first silicide is on the anode region. An ohmic contact is made to the second silicide on the anode region and to the well.
摘要翻译：包括结势垒肖特基二极管的集成电路具有N型阱，阱表面中的P型阳极区域和阱表面中的N型肖特基区域，并且水平地邻接阳极区域。第一硅化物层在肖特基区域上并与其相邻的阳极区域形成肖特基接触。与第一硅化物不同的第二硅化物层位于阳极区上。对阳极区域和阱的第二硅化物进行欧姆接触。

85. 发明申请

US20110177668A1 METHOD OF MAKING A THIN FILM RESISTOR 有权
标题翻译：制造薄膜电阻的方法
公开(公告)号：US20110177668A1
公开(公告)日：2011-07-21
申请号：US12688083
申请日：2010-01-15
申请人： Der-Chyang YEH , Hsun-Chung KUANG , Ming Chyi LIU , Chung-Yi YU , Chih-Ping CHAO , Alexander KALNITSKY
发明人： Der-Chyang YEH , Hsun-Chung KUANG , Ming Chyi LIU , Chung-Yi YU , Chih-Ping CHAO , Alexander KALNITSKY
IPC分类号： H01L21/02
CPC分类号： H01L28/20 , H01L21/76801 , H01L21/76843 , H01L21/76864 , H01L21/76865 , H01L27/016 , H01L28/24
摘要： A method of making a thin film resistor includes: forming a doped region in a semiconductor substrate; forming a dielectric layer over the substrate; forming a thin film resistor over the dielectric layer; forming a contact hole in the dielectric layer before annealing the thin film resistor, wherein the contact hole exposes a portion of the doped region; and performing rapid thermal annealing on the thin film resistor after forming the contact hole.
摘要翻译：制造薄膜电阻器的方法包括：在半导体衬底中形成掺杂区域; 在所述衬底上形成介电层; 在介电层上形成薄膜电阻; 在退火所述薄膜电阻器之前，在所述电介质层中形成接触孔，其中所述接触孔暴露所述掺杂区域的一部分; 并且在形成接触孔之后对薄膜电阻器进行快速热退火。

86. 发明授权

US07750426B2 Junction barrier Schottky diode with dual silicides 失效
标题翻译：具有双重硅化物的结型势垒肖特基二极管
公开(公告)号：US07750426B2
公开(公告)日：2010-07-06
申请号：US11849565
申请日：2007-09-04
申请人： Dev Alok Girdhar , Michael David Church , Alexander Kalnitsky
发明人： Dev Alok Girdhar , Michael David Church , Alexander Kalnitsky
IPC分类号： H01L27/095 , H01L29/47 , H01L31/07
CPC分类号： H01L29/872 , H01L27/0629 , H01L29/456 , H01L29/47 , H01L29/7833
摘要： An integrated circuit, including a junction barrier Schottky diode, has an N type well, a P-type anode region in the surface of the well, and an N-type Schottky region in the surface of the well and horizontally abutting the anode region. A first silicide layer is on and makes a Schottky contact to the Schottky region and is on an adjoining anode region. A second silicide layer of a different material than the first silicide is on the anode region. An ohmic contact is made to the second silicide on the anode region and to the well.
摘要翻译：包括结势垒肖特基二极管的集成电路具有N型阱，阱表面中的P型阳极区域和阱表面中的N型肖特基区域，并且水平地邻接阳极区域。第一硅化物层在肖特基区域上并与其相邻的阳极区域形成肖特基接触。与第一硅化物不同的第二硅化物层位于阳极区上。对阳极区域和阱的第二硅化物进行欧姆接触。

87. 发明申请

US20090207655A1 MULTIPLE TIME PROGRAMMABLE (MTP) PMOS FLOATING GATE-BASED NON-VOLATILE MEMORY DEVICE FOR A GENERAL PURPOSE CMOS TECHNOLOGY WITH THICK GATE OXIDE 有权
标题翻译：多通道时间可编程（MTP）PMOS浮动栅基非易失性存储器件用于一般用途CMOS技术与厚栅氧化物
公开(公告)号：US20090207655A1
公开(公告)日：2009-08-20
申请号：US12430007
申请日：2009-04-24
申请人： Alexander Kalnitsky , Michael Church
发明人： Alexander Kalnitsky , Michael Church
IPC分类号： G11C16/04 , G11C16/06 , G11C11/34
CPC分类号： G11C16/0433 , G11C16/10 , H01L27/115 , H01L27/11521 , H01L27/11558
摘要： A multiple time programmable (MTP) memory cell, in accordance with an embodiment, includes a floating gate PMOS transistor, a high voltage NMOS transistor, and an n-well capacitor. The floating gate PMOS transistor includes a source that forms a first terminal of the memory cell, a drain and a gate. The high voltage NMOS transistor includes a source connected to ground, an extended drain connected to the drain of the PMOS transistor, and a gate forming a second terminal of the memory cell. The n-well capacitor includes a first terminal connected to the gate of the PMOS transistor, and a second terminal forming a third terminal of the memory cell. The floating gate PMOS transistor can store a logic state. Combinations of voltages can be applied to the first, second and third terminals of the memory cell to program, inhibit program, read and erase the logic state.
摘要翻译：根据实施例的多时间可编程（MTP）存储单元包括浮置栅极PMOS晶体管，高电压NMOS晶体管和n阱电容器。浮置栅极PMOS晶体管包括形成存储单元的第一端子，漏极和栅极的源极。高电压NMOS晶体管包括连接到地的源极，连接到PMOS晶体管的漏极的延伸漏极和形成存储器单元的第二端子的栅极。 n阱电容器包括连接到PMOS晶体管的栅极的第一端子和形成存储器单元的第三端子的第二端子。浮置栅极PMOS晶体管可以存储逻辑状态。可以将组合的电压施加到存储单元的第一，第二和第三端子，以编程，禁止程序，读取和擦除逻辑状态。

88. 发明授权

US07542342B2 Multiple time programmable (MTP) PMOS floating gate-based non-volatile memory device for a general-purpose CMOS technology with thick gate oxide 失效
标题翻译：多时间可编程（MTP）PMOS浮动栅极非易失性存储器件，用于具有厚栅极氧化物的通用CMOS技术
公开(公告)号：US07542342B2
公开(公告)日：2009-06-02
申请号：US11508771
申请日：2006-08-23
申请人： Alexander Kalnitsky , Michael Church
发明人： Alexander Kalnitsky , Michael Church
IPC分类号： G11C16/04
CPC分类号： G11C16/0433 , G11C16/10 , H01L27/115 , H01L27/11521 , H01L27/11558
摘要： A multiple time programmable (MTP) memory cell, in accordance with an embodiment, includes a floating gate PMOS transistor, a high voltage NMOS transistor, and an n-well capacitor. The floating gate PMOS transistor includes a source that forms a first terminal of the memory cell, a drain and a gate. The high voltage NMOS transistor includes a source connected to ground, an extended drain connected to the drain of the PMOS transistor, and a gate forming a second terminal of the memory cell. The n-well capacitor includes a first terminal connected to the gate of the PMOS transistor, and a second terminal forming a third terminal of the memory cell. The floating gate PMOS transistor can store a logic state. Combinations of voltages can be applied to the first, second and third terminals of the memory cell to program, inhibit program, read and erase the logic state.
摘要翻译：根据实施例的多时间可编程（MTP）存储单元包括浮置栅极PMOS晶体管，高电压NMOS晶体管和n阱电容器。浮置栅极PMOS晶体管包括形成存储单元的第一端子，漏极和栅极的源极。高电压NMOS晶体管包括连接到地的源极，连接到PMOS晶体管的漏极的延伸漏极和形成存储器单元的第二端子的栅极。 n阱电容器包括连接到PMOS晶体管的栅极的第一端子和形成存储器单元的第三端子的第二端子。浮置栅极PMOS晶体管可以存储逻辑状态。可以将组合的电压施加到存储单元的第一，第二和第三端子，以编程，禁止程序，读取和擦除逻辑状态。

89. 发明授权

US07485486B2 Photodiode for multiple wavelength operation 有权
标题翻译：用于多波长操作的光电二极管
公开(公告)号：US07485486B2
公开(公告)日：2009-02-03
申请号：US11532762
申请日：2006-09-18
申请人： Dong Zheng , Phillip J. Benzel , Joy Jones , Alexander Kalnitsky , Perumal Ratman
发明人： Dong Zheng , Phillip J. Benzel , Joy Jones , Alexander Kalnitsky , Perumal Ratman
IPC分类号： H01L21/00
CPC分类号： H01L27/1462 , H01L27/1463 , H01L31/02165
摘要： A method of a fabricating a multiple wavelength adapted photodiode and resulting photodiode includes the steps of providing a substrate having a first semiconductor type surface region on at least a portion thereof, implanting and forming a second semiconductor type shallow surface layer into the surface region, and forming a multi-layer anti-reflective coating (ARC) on the shallow surface layer. The forming step includes depositing or forming a thin oxide layer on the shallow surface layer and depositing a second dielectric layer different from the thin oxide layer on the thin oxide layer. An etch stop is formed on the second dielectric, wherein the etch stop includes at least one layer resistant to oxide etch. At least one oxide including layer (e.g. ILD) is then deposited on the etch stop. The oxide including layer and etch stop are then removed to expose at least a portion of the ARC to the ambient.
摘要翻译：一种制造多波长适应光电二极管和所得光电二极管的方法包括以下步骤：在其至少一部分上提供具有第一半导体类型表面区域的衬底，将表面区域中的第二半导体型浅表面层注入并形成，以及在浅表面层上形成多层抗反射涂层（ARC）。形成步骤包括在浅表面层上沉积或形成薄氧化物层，并在薄氧化物层上沉积不同于薄氧化物层的第二电介质层。蚀刻停止件形成在第二电介质上，其中蚀刻停止层包括至少一层抵抗氧化物蚀刻的层。然后将至少一种包括层（例如ILD）的氧化物沉积在蚀刻停止件上。然后去除包括氧化物层和蚀刻停止层，以将ARC的至少一部分暴露于环境中。

90. 发明申请

US20080266959A1 MEMORY ARRAY OF FLOATING GATE-BASED NON-VOLATILE MEMORY CELLS 有权
标题翻译：基于盖帽的不挥发性记忆细胞的记忆阵列
公开(公告)号：US20080266959A1
公开(公告)日：2008-10-30
申请号：US11861111
申请日：2007-09-25
申请人： Hosam Haggag , Alexander Kalnitsky , Edgardo Laber , Michael D. Church , Yun Yue
发明人： Hosam Haggag , Alexander Kalnitsky , Edgardo Laber , Michael D. Church , Yun Yue
IPC分类号： G11C16/04
CPC分类号： G11C16/0433
摘要： A memory array comprises a plurality of memory cells organized in a matrix of rows and columns. Each of the memory cells includes a high voltage access transistor, a floating gate memory transistor electrically connected to the access transistor, and a coupling capacitor electrically connected to the memory transistor. A first set of word lines are each electrically connected to the capacitor in each of the memory cells in a respective row. A second set of word lines are each electrically connected to the access transistor in each of the memory cells in a respective row. A first set of bit lines are each electrically connected to the access transistor in each of the memory cells in a respective column. A second set of bit lines are each electrically connected to the memory transistor in each of the memory cells in a respective column. Various combinations of voltages can be applied to the word lines and bit lines in operations to program, erase, read, or inhibit a logic state stored by the memory transistor in one or more of the memory cells.
摘要翻译：存储器阵列包括以行和列的矩阵组织的多个存储器单元。每个存储单元包括高电压存取晶体管，电连接到存取晶体管的浮动栅极存储晶体管和电连接到存储晶体管的耦合电容器。第一组字线分别电连接到相应行中的每个存储器单元中的电容器。第二组字线各自电连接到相应行中的每个存储单元中的存取晶体管。第一组位线分别电连接到相应列中每个存储单元中的存取晶体管。第二组位线分别电连接到相应列中每个存储器单元中的存储晶体管。在操作中可以对字线和位线施加电压的各种组合，以对存储器晶体管存储在一个或多个存储器单元中的逻辑状态进行编程，擦除，读取或禁止。

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