专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

71. 发明申请

US20040038462A1 Process for growing a dielectric layer on a silicon-containing surface using a mixture of N2O and O3 失效
标题翻译：使用N2O和O3的混合物在含硅表面上生长电介质层的方法
公开(公告)号：US20040038462A1
公开(公告)日：2004-02-26
申请号：US10642705
申请日：2003-08-18
发明人： Gurtej Singh Sandhu , Randhir PS Thakur
IPC分类号： C23C016/40 , H01L021/335
CPC分类号： H01L21/28202 , H01L21/0214 , H01L21/02249 , H01L21/02255 , H01L21/28185 , H01L21/28211 , H01L21/31662 , H01L21/32105 , H01L29/518
摘要： This invention is embodied in an improved process for growing high-quality silicon dioxide layers on silicon by subjecting it to a gaseous mixture of nitrous oxide (N2O) and ozone (O3). The presence of O3 in the oxidizing ambiance greatly enhances the oxidation rate compared to an ambiance in which N2O is the only oxidizing agent. In addition to enhancing the oxidation rate of silicon, it is hypothesized that the presence of O3 interferes with the growth of a thin silicon oxynitride layer near the interface of the silicon dioxide layer and the unreacted silicon surface which makes oxidation in the presence of N2O alone virtually self-limiting. The presence of O3 in the oxidizing ambiance does not impair oxide reliability, as is the case when silicon is oxidized with N2O in the presence of a strong, fluorine-containing oxidizing agent such as NF3 or SF6.
摘要翻译：本发明体现在通过使其经受一氧化二氮（N 2 O）和臭氧（O 3）的气体混合物在硅上生长高品质二氧化硅层的改进方法。氧化气氛中O3的存在与其中N2O是唯一氧化剂的氛围相比，大大提高了氧化速率。除了提高硅的氧化速率之外，假设O3的存在干扰了在二氧化硅层和未反应的硅表面的界面附近生长的薄氧氮化硅层，这在单独的N2O存在下进行氧化实际上是自限制的。氧化气氛中O 3的存在不会损害氧化物的可靠性，如在含氟的氧化剂如NF3或SF6的存在下用N 2 O氧化硅的情况。

72. 发明申请

US20040029324A1 Method for fabricating semiconductor device by forming damascene interconnections 有权
标题翻译：通过形成镶嵌互连制造半导体器件的方法
公开(公告)号：US20040029324A1
公开(公告)日：2004-02-12
申请号：US10627895
申请日：2003-07-24
发明人： Je-Min Park
IPC分类号： H01L021/335
CPC分类号： H01L21/76897 , H01L21/76802 , H01L21/76807
摘要： A method for fabricating a semiconductor device, in which a sufficient misalignment margin is obtained when forming interconnections and contact holes, is provided. Dielectric layer patterns which define recesses in which damascene interconnections are to be formed, are formed. Then, first contact holes between the dielectric layer patterns are etched, and the first contact holes and the recesses are concurrently filled with a conductive material. The recesses can be filled with the conductive material by performing an etch-back process. The dielectric layer patterns are then etched, thereby forming the damascene interconnections and concurrently covering only a region in which second contact holes are to be formed with the dielectric layer patterns. Spaces between the dielectric layer patterns are filled with a mask layer, and then the dielectric layer patterns are selectively removed from the resultant structure, thereby forming the second contact holes aligned with the damascene interconnections.
摘要翻译：提供一种制造半导体器件的方法，其中在形成互连和接触孔时获得足够的未对准余量。形成限定要形成镶嵌互连的凹部的介电层图案。然后，蚀刻电介质层图案之间的第一接触孔，同时用导电材料填充第一接触孔和凹部。通过执行回蚀工艺，可以用导电材料填充凹部。然后蚀刻介电层图案，从而形成镶嵌互连，并且同时仅覆盖将要与介电层图案形成第二接触孔的区域。电介质层图案之间的空隙用掩模层填充，然后从所得到的结构中选择性地除去电介质层图案，从而形成与镶嵌互连对准的第二接触孔。

73. 发明申请

US20040029319A1 METHOD TO REMOVE AN OXIDE SEAM ALONG GATE STACK EDGE, WHEN NITRIDE SPACE FORMATION BEGINS WITH AN OXIDE LINER SURROUNDING GATE STACK 有权
标题翻译：当氮氧化物空间形成与氧化物衬里周围的栅格堆叠时，在门盖堆积边缘上移除氧化物的方法
公开(公告)号：US20040029319A1
公开(公告)日：2004-02-12
申请号：US10213086
申请日：2002-08-07
发明人： Paul J. Rudeck
IPC分类号： H01L021/335
CPC分类号： H01L27/11521 , H01L27/115
摘要： An exposed top end of a vertical oxide spacer is removed, and a nitride layer is deposited in an amount sufficient to replace the removed portion prior to exposing a memory device to a self align contact etch process. The nitride layer may be used to prevent a short circuit through the oxide spacer. The present invention also provides memory devices that have a gate stack, a vertical spacer adjacent to the gate stack, in which the vertical spacer has a lower portion comprising an oxide and an upper portion comprising a nitride, and a continuous nitride layer overlaying the vertical spacer and the gate stack. The present invention further provides methods of fabricating the above devices, and processor systems which include the devices.
摘要翻译：去除暴露的垂直氧化物间隔物的顶端，并且在将存储器件暴露于自对准接触蚀刻工艺之前，以足以代替去除的部分的量沉积氮化物层。氮化物层可以用于防止通过氧化物间隔物的短路。本发明还提供了一种存储器件，它们具有一个栅极叠层，一个邻近栅极叠层的垂直隔离层，其中垂直间隔物具有一个包含一个氧化物的下部分和一个包含一个氮化物的上部分，以及一个连续的氮化物层，间隔器和栅极堆叠。本发明还提供了制造上述装置的方法以及包括这些装置的处理器系统。

74. 发明申请

US20040029050A1 Fabrication of nanoelectronic circuits 审中-公开
标题翻译：纳米电子电路的制造
公开(公告)号：US20040029050A1
公开(公告)日：2004-02-12
申请号：US10362822
申请日：2003-08-27
发明人： Rolf Brenner , Tilo Marcus Buehler , Robert Graham Clark , Andrew Steven Dzurak , Alexander Rudolf Hamilton , Nancy Ellen Lumpkin , Rita Paytricia McKinnon
IPC分类号： G03F007/16 , G03F007/20 , G03F007/30 , H01L021/335 , H01L021/8232 , H01L021/20 , H01L021/36 , H01L021/425 , H01L029/167 , H01L029/207 , H01L029/227 , H01L031/0288 , H01L023/58
CPC分类号： H01L49/006 , B82Y10/00 , G06N10/00 , H01L21/266 , H01L29/66439
摘要： A silicon substrate is coated with one or more layers of resist. First and second circuit patterns are exposed in sequence, where the second pattern crosses the first pattern. The patterned resist layers are developed to open holes which extend down to the substrate only where the patterns cross over each other. These holes provide a mask suitable for implanting single phosphorous ions in the substrate, for a solid state quantum computer. Further development of the resist layers provides a mask for the deposition of nanoelectronic circuits, such as single electron transistors, aligned to the phosphorous ions.
摘要翻译：硅衬底涂覆有一层或多层抗蚀剂。顺序地暴露第一和第二电路图案，其中第二图案与第一图案交叉。图案化的抗蚀剂层被显影以打开仅在图案彼此交叉的位置向下延伸到基底的孔。这些孔提供了适用于在固态量子计算机中将衬底中的单个磷离子注入的掩模。抗蚀剂层的进一步开发提供了用于沉积与磷离子对准的纳米电子电路（例如单电子晶体管）的掩模。

75. 发明申请

US20030170928A1 Production method for solid imaging device 失效
标题翻译：固体成像装置的生产方法
公开(公告)号：US20030170928A1
公开(公告)日：2003-09-11
申请号：US10333640
申请日：2003-05-05
发明人： Takayuki Shimozono , Ritsuo Takizawa
IPC分类号： H01L021/00 , H01L021/335 , H01L021/8232
CPC分类号： H01L27/14683 , H01L27/14698 , H01L27/14806
摘要： White defects caused by a dark-current of a solid-state imaging device is reduced by effectively bringing out gettering capability of a buried getter sink layer. A buried getter sink layer is formed by introducing to the semiconductor substrate a substance of a second element which is a congener of a first element composing a semiconductor substrate, a crystal growth layer is formed by crystal growing a substance of the first element on a surface of the semiconductor substrate, and a solid-state imaging element is formed inside and on the crystal growth layer at a lower temperature than that in the case of forming an extrinsic getter sink layer by introducing a substance of a third element of a different group from the first element on a back surface of the semiconductor substrate. Alternately, a solid-state imaging element is formed at a lower temperature than that in the case of forming an extrinsic getter sink layer on a surface of the crystal growth layer by oxidization in an atmosphere of a gas containing hydrochloric acid.
摘要翻译：通过有效地提供掩埋的吸气剂吸收层的吸气能力，降低了由固态成像装置的暗电流引起的白色缺陷。通过向半导体基板引入作为构成半导体基板的第一元素的同源物的第二元素的物质形成掩埋的吸气剂沉积层，通过在表面上晶体生长第一元素的物质形成晶体生长层的半导体衬底的固体摄像元件，并且在比通过将不同组的第三元素的物质引入外部吸收剂沉积层的情况下的温度低于晶体生长层的内部和外部形成固体摄像元件半导体衬底的背表面上的第一元件。或者，固体成像元件形成在比在含有盐酸的气体的气氛中通过氧化在晶体生长层的表面上形成外部吸气剂沉积层的情况下更低的温度。

76. 发明申请

US20030155523A1 Apparatus and a method for forming a pattern using a crystal structure of material 有权
标题翻译：使用材料的晶体结构形成图案的装置和方法
公开(公告)号：US20030155523A1
公开(公告)日：2003-08-21
申请号：US10220364
申请日：2002-08-29
发明人： Ki-Bum Kim
IPC分类号： H01L021/335 , H01L021/8232 , H01L021/26 , H01L021/324 , H01L021/42 , H01L021/477 , G21G005/00 , H01J027/00 , A61N005/00
CPC分类号： H01J37/3174 , B82Y5/00 , B82Y10/00 , B82Y30/00 , B82Y40/00 , G03F7/70408 , Y10S430/143
摘要： The present invention relates generally to an apparatus and a method for forming a pattern, and in particular, to an apparatus and a method for forming a pattern for the formation of quantum dots or wires with 1null50 nm dimension using the atomic array of a crystalline material and to the manufacture of functional devices that have such a structure. In the present invention, the functional device means an electronic, magnetic, or optical device that can be fabricated by procedures including the formation process of quantum dots or wires.
摘要翻译：本发明一般涉及一种用于形成图案的装置和方法，特别涉及一种用于形成用于形成具有1〜50nm尺寸的量子点或线的图案的装置和方法，其使用原子阵列晶体材料和具有这种结构的功能器件的制造。在本发明中，功能器件是指可以通过包括量子点或线的形成过程的工艺制造的电子，磁性或光学器件。

77. 发明申请

US20030036225A1 METHOD OF FORMING A SEMICONDUCTOR DEVICE WITH GETTERING A GROUP XV ELEMENT BY MEANS OF INFRARED LIGHT 失效
标题翻译：通过红外光照射形成第XV组元件的半导体器件的方法
公开(公告)号：US20030036225A1
公开(公告)日：2003-02-20
申请号：US09764432
申请日：2001-01-19
发明人： Setsuo Nakajima , Hisashi Ohtani
IPC分类号： H01L021/335 , H01L021/8232 , H01L021/00 , H01L021/84
CPC分类号： H01L29/66757 , G02F1/13454 , H01L29/66765
摘要： There is disclosed a method of fabricating TFTs using a silicon film crystallized with the aid of nickel. The nickel is removed from the crystallized silicon film. The method starts with maintaining nickel in contact with the surface of an amorphous silicon film. Then, a heat treatment is performed to form a crystalline silicon film. At this time, nickel promotes the crystallization greatly, and nickel diffuses into the film. A mask is formed. A silicon film heavily doped with phosphorus is formed. Thereafter, a heat treatment is performed to move the nickel from the crystalline silicon film into the phosphorus-rich silicon film. This reduces the concentration of nickel in the crystalline silicon film.
摘要翻译：公开了使用借助于镍结晶的硅膜制造TFT的方法。从结晶硅膜中除去镍。该方法开始于保持镍与非晶硅膜的表面接触。然后，进行热处理以形成结晶硅膜。此时，镍大大促进结晶，镍扩散到膜中。形成掩模。形成重掺杂磷的硅膜。此后，进行热处理，以使镍从结晶硅膜移动到富磷硅膜中。这降低了结晶硅膜中镍的浓度。

78. 发明申请

US20030034525A1 Method of increasing the conductivity of a transparent conductive layer 失效
公开(公告)号：US20030034525A1
公开(公告)日：2003-02-20
申请号：US10265877
申请日：2002-10-07
申请人： Koniklijke Philips Electronics N.V.
发明人： Ian D. French , Pieter J. Van Der Zaag , Eric A. Meulenkamp
IPC分类号： H01L021/335 , H01L031/0392 , H01L021/8232 , H01L027/12
CPC分类号： G02F1/1345 , G02F1/136286
摘要： A method of increasing the conductivity of a transparent conductive layer, in which a photoresist layer which patterns the transparent layer is given tapered edges and is partially etched. The partial etching exposing the edge regions of the underlying transparent conductor layer, which are the selectively plated. This method has a single patterning stage of the transparent layer, but uses partial etching of a tapered resist layer in order to expose a small edge region of the transparent layer for coating with a conductive layer (which can be opaque).

79. 发明申请

US20020168804A1 Electronic devices comprising thin film transistors 审中-公开
标题翻译：包括薄膜晶体管的电子器件
公开(公告)号：US20020168804A1
公开(公告)日：2002-11-14
申请号：US10142587
申请日：2002-05-09
申请人： KONINKLIJKE PHILIPS ELECTRONIC N.V.
发明人： Pieter J. Van der Zaag , Steven C. Deane , Stephen J. Battersby
IPC分类号： H01L021/335 , H01L021/8232
CPC分类号： H01L29/6675 , H01L29/78606 , H01L29/78618 , H01L29/78642 , H01L51/0512 , H01L51/057 , Y10S438/949
摘要： The invention provides a method of manufacturing an electronic device including a vertical thin film transistor. A layer (8) of semiconductor material is provided over an insulated gate electrode (2). A negative resist (14) is used to define source and drain electrodes (26,28) which extend over the insulating layer (8) up to the step formed therein adjacent an edge (16A) of the gate electrode (2).
摘要翻译：本发明提供一种制造包括垂直薄膜晶体管的电子器件的方法。半导体材料层（8）设置在绝缘栅电极（2）上。负抗蚀剂（14）用于限定在绝缘层（8）上延伸到邻近栅极（2）的边缘（16A）形成的台阶的源极和漏极（26,28）。

80. 发明申请

US20020013018A1 Driving method of an electric circuit 有权
标题翻译：电路的驱动方法
公开(公告)号：US20020013018A1
公开(公告)日：2002-01-31
申请号：US09906617
申请日：2001-07-18
发明人： Yukio Tanaka
IPC分类号： H01L021/335 , H01L021/8232
CPC分类号： G09G3/3648 , G09G3/3688 , H03K17/145 , H03K17/687 , H03K17/6872 , H03K17/693
摘要： A variation in threshold may be suppressed by structuring an analog switch by a MOS transistor and forming a signal synchronized to a clock by making the clock which is a common signal in continuity or discontinuity. An object of the present invention is to reduce the variation in the signal synchronized to the clock by the variation in threshold of the MOS transistor in a circuit which is synchronized to the clock.
摘要翻译：可以通过由MOS晶体管构造模拟开关并通过使作为公共信号的时钟连续性或不连续性而形成与时钟同步的信号来抑制阈值的变化。本发明的目的是通过与时钟同步的电路中的MOS晶体管的阈值变化来减少与时钟同步的信号的变化。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式