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1. 发明申请

US20040038461A1 Semiconductor device on silicon-on-insulator and method for manufacturing the semiconductor device 有权
标题翻译：绝缘体上的半导体器件及半导体器件的制造方法
公开(公告)号：US20040038461A1
公开(公告)日：2004-02-26
申请号：US10636415
申请日：2003-08-07
发明人： Young-Ki Lee , Heon-Jong Shin , Ji-Woon Rim
IPC分类号： H01L021/335
CPC分类号： H01L29/66772 , H01L29/78624
摘要： A semiconductor device on a SOI and a method for manufacturing the same are provided. The semiconductor device includes a semiconductor wafer having a SOI structure including an insulating layer having a predetermined thickness and a monocrystalline silicon layer formed on the insulating layer, an isolation insulating layer formed on the insulating layer on the semiconductor wafer, a gate comprised of a gate dielectric layer and a gate conductive layer, which are sequentially stacked on the monocrystalline silicon layer, insulating layer spacers formed at the sidewalls of the gate, and a source junction and a drain junction asymmetrically formed at either side of the gate between the isolation insulating layer spacers and the insulating layer. In the semiconductor device formed on a SOI, source and drain junctions are formed at either side of a gate to be asymmetrical, and thus a ground of a transistor is formed on the SOI, and thus the electrical characteristics of the semiconductor device are improved.
摘要翻译：提供SOI上的半导体器件及其制造方法。半导体器件包括具有SOI结构的半导体晶片，该SOI结构包括具有预定厚度的绝缘层和形成在绝缘层上的单晶硅层，形成在半导体晶片上的绝缘层上的隔离绝缘层，由栅极电介质层和栅极导电层，其顺序地堆叠在单晶硅层上，在栅极的侧壁处形成的绝缘层间隔物以及不对称地形成在隔离绝缘层的栅极两侧的源极结和漏极结间隔物和绝缘层。在SOI上形成的半导体器件中，在栅极的任一侧形成源极和漏极结以使其不对称，从而在SOI上形成晶体管的接地，从而提高半导体器件的电气特性。

2. 发明申请

US20030045035A1 Novel edge termination structure for semiconductor devices 失效
标题翻译：用于半导体器件的新型边缘端接结构
公开(公告)号：US20030045035A1
公开(公告)日：2003-03-06
申请号：US10104945
申请日：2002-03-22
发明人： Krishna Shenai , Malay Trivedi , Philip Neudeck
IPC分类号： H01L021/335
CPC分类号： H01L29/6606 , H01L29/0619 , H01L29/1608 , H01L29/861 , H01L29/872
摘要： A method and apparatus are provided for improving a breakdown voltage of a semiconductor device. The method includes the steps of coupling an electrode of the silicon-carbide diode to a drift layer of the semiconductor device through a charge transfer junction, said drift layer being of a first doping type and providing a junction termination layer of a relatively constant thickness in direct contact with the drift layer of the semiconductor device and in direct contact with an outside edge of the charge transfer junction, said junction termination layer extending outwards from the outside edge of the charge transfer junction, said junction termination layer also being doped with a doping material of a second doping type in sufficient concentration to provide a charge depletion region adjacent the outside edge of the charge transfer junction when the-charge transfer junction is reverse biased.
摘要翻译：提供了一种用于改善半导体器件的击穿电压的方法和装置。该方法包括以下步骤：通过电荷转移结将碳化硅二极管的电极耦合到半导体器件的漂移层，所述漂移层是第一掺杂类型，并且提供相对恒定厚度的接合端接层与半导体器件的漂移层直接接触并且与电荷转移结的外部边缘直接接触，所述连接终止层从电荷转移结的外部边缘向外延伸，所述连接终端层还掺杂有掺杂具有足够浓度的第二掺杂类型的材料，以在电荷转移结被反向偏置时提供与电荷转移结的外边缘相邻的电荷耗尽区。

3. 发明申请

US20020197775A1 Laminating method for forming integrated circuit microelectronic fabrication 有权
标题翻译：用于形成集成电路微电子制造的层压方法
公开(公告)号：US20020197775A1
公开(公告)日：2002-12-26
申请号：US09885784
申请日：2001-06-20
申请人： Taiwan Semiconductor Manufacturing Co., Ltd.
发明人： Mong-Song Liang , Syun-Ming Jang
IPC分类号： H01L021/20 , H01L021/335 , H01L021/8232
CPC分类号： H01L21/768 , H01L23/522 , H01L2924/0002 , Y10S438/977 , H01L2924/00
摘要： Within a method for fabricating a semiconductor integrated circuit microelectronic fabrication there is first provided a first semiconductor substrate. There is then formed over the first semiconductor substrate at least one microelectronic device to form from the first semiconductor substrate a partially fabricated semiconductor integrated circuit microelectronic fabrication. Within the method there is also provided a second substrate. There is also formed over the second substrate, in inverted order, a dielectric isolated metallization pattern intended to mate with the partially fabricated semiconductor integrated circuit microelectronic fabrication. Finally, there is then laminated the partially fabricated semiconductor integrated circuit microelectronic fabrication with the second substrate to mate the partially fabricated semiconductor integrated circuit microelectronic fabrication with the dielectric isolated metallization pattern to thus form a laminated completely fabricated semiconductor integrated circuit microelectronic fabrication. The method provides for enhanced efficiency when fabricating semiconductor integrated circuit microelectronic fabrications.
摘要翻译：在制造半导体集成电路微电子制造的方法中，首先提供第一半导体衬底。然后在第一半导体衬底上形成至少一个微电子器件，以从第一半导体衬底形成部分制造的半导体集成电路微电子制造。在该方法中，还提供了第二衬底。在第二衬底上还以反向顺序形成旨在与部分制造的半导体集成电路微电子制造配合的电介质隔离金属化图案。最后，然后将部分制造的半导体集成电路微电子制造与第二衬底层压，以将部分制造的半导体集成电路微电子制造与介电隔离金属化图案配合，从而形成层叠的完全制造的半导体集成电路微电子制造。该方法在制造半导体集成电路微电子制造时提供了增强的效率。

4. 发明申请

US20020102774A1 Method and apparatus for split gate source side injection flash memory cell and array with dedicated erase gates 审中-公开
标题翻译：用于具有专用擦除栅极的分离栅极源侧注入闪存单元和阵列的方法和装置
公开(公告)号：US20020102774A1
公开(公告)日：2002-08-01
申请号：US10035727
申请日：2001-10-18
发明人： Dah-Bin Kao , Loc B. Hoang , Albert T. Wu , Tung-Yi Chan
IPC分类号： H01L021/335
CPC分类号： H01L27/11521 , G11C16/0416 , H01L27/115 , H01L29/42324
摘要： A transistor structure having a dedicated erase gate where the transistor can be used as a memory cell is disclosed. The presently preferred embodiment of the transistor comprises a floating gate disposed on a substrate and having a control gate and an erase gate overlapping said floating gate, with drain and source regions doped on the substrate. By providing a dedicated erase gate, the gate oxide underneath the control gate can be made thinner and can have a thickness that is conducive to the scaling of the transistor. The overall cell size of the transistor remains the same and the program and read operation can remain the same. Both the common source and buried bitline architecture can be used, namely twin well or triple well architectures. A memory circuit using the transistors of the present invention is disclosed as well for flash memory circuit applications.
摘要翻译：公开了具有专用擦除栅极的晶体管结构，其中晶体管可用作存储单元。晶体管的当前优选实施例包括设置在衬底上的浮置栅极，并且具有与所述浮置栅极重叠的控制栅极和擦除栅极，掺杂在衬底上的漏极和源极区域。通过提供专用的擦除栅极，可以使控制栅极下方的栅极氧化物变得更薄，并且可以具有有利于晶体管结垢的厚度。晶体管的整体单元尺寸保持相同，并且程序和读取操作可以保持不变。可以使用共同的源和掩埋位线架构，即双阱或三阱架构。对于闪存电路应用也公开了使用本发明的晶体管的存储电路。

5. 发明申请

US20020094612A1 Method of manufacturing semiconductor device 失效
标题翻译：制造半导体器件的方法
公开(公告)号：US20020094612A1
公开(公告)日：2002-07-18
申请号：US10046893
申请日：2002-01-17
发明人： Osamu Nakamura , Shunpei Yamazaki , Koji Dairiki , Masayuki Kajiwara , Junichi Koezuka , Satoshi Murakami
IPC分类号： H01L021/335 , H01L021/8232 , H01L021/00
CPC分类号： H01L27/12 , H01L21/02532 , H01L21/02672 , H01L21/02675 , H01L21/3226 , H01L27/1277 , H01L29/66757 , H01L29/78621 , H01L29/78624 , H01L29/78633 , H01L29/78645 , H01L29/78675
摘要： According to the present invention, an impurity region, to which a rare gas element (also called a rare gas) and one kind or a plurality of kinds of elements selected from the group consisting of H, H2, O, O2, and P are added, are formed in a semiconductor film having a crystalline structure, using a mask, and gettering for segregating a metal element contained in the semiconductor film to the impurity region by heat treatment. Thereafter, pattering is conducted using the mask, whereby a semiconductor layer made of the semiconductor film having a crystalline structure is formed.
摘要翻译：根据本发明，稀有气体元素（也称为稀有气体）和选自H，H 2，O，O 2和P中的一种或多种元素的杂质区域是使用掩模形成具有晶体结构的半导体膜，并且通过热处理将用于将包含在半导体膜中的金属元素分离到杂质区域的吸杂剂形成。此后，使用掩模进行图案化，由此形成由具有晶体结构的半导体膜制成的半导体层。

6. 发明申请

US20020086548A1 Method for forming gate dielectric layer in NROM 有权
标题翻译：在NROM中形成栅介质层的方法
公开(公告)号：US20020086548A1
公开(公告)日：2002-07-04
申请号：US09735894
申请日：2000-12-14
发明人： Kent Kuohua Chang
IPC分类号： H01L021/335 , H01L021/8232
CPC分类号： H01L21/28185 , H01L21/28194 , H01L21/28202 , H01L21/28282 , H01L29/513 , H01L29/517 , H01L29/518
摘要： In fabricating nitride read only memory, a zirconium oxide layer has high dielectric constant and a zirconium oxide layer is replaced conventional tunnel oxide layer. Zirconium oxide layer can increase coupling ratio of gate dielectric layer and reliability for nitride read only memory type flash memory is improved. This invention, a substrate is provided and a zirconium oxide layer is formed on substrate by reactive magnetron sputtering and a silicon nitride layer is sandwiched between a zirconium oxide layer and a silicon oxide layer. Then, an ONO layer (oxide-nitride-oxide layer) is formed. The method is using zirconium oxide as gate dielectric can reduce leakage current, increase drain current, improve subthreshold characteristics, and electron and hole mobilities.
摘要翻译：在制造氮化物只读存储器中，氧化锆层具有高介电常数，氧化锆层代替传统的隧道氧化物层。氧化锆层可以增加栅极介电层的耦合比和氮化物只读存储器型闪存的可靠性。本发明提供一种衬底，并通过反应性磁控溅射在衬底上形成氧化锆层，氮化硅层夹在氧化锆层和氧化硅层之间。然后，形成ONO层（氧化物 - 氮化物 - 氧化物层）。该方法使用氧化锆作为栅极电介质可以减少泄漏电流，增加漏极电流，提高亚阈值特性，以及电子和空穴迁移率。

7. 发明申请

US20020061617A1 FABRICATION METHOD OF A DUAL-GATE CMOSFET 失效
标题翻译：双栅CMOSFET的制造方法
公开(公告)号：US20020061617A1
公开(公告)日：2002-05-23
申请号：US09524268
申请日：2000-03-13
发明人： Hideaki Matsuhashi
IPC分类号： H01L021/335
CPC分类号： H01L21/823842 , H01L21/823814 , H01L21/823864
摘要： A fabrication method for fabricating a dual-gate CMOSFET on a semiconductor substrate according to the present invention includes: implanting ions of N-type impurity for forming a deep junction source and drain in a first region on the semiconductor substrate where an NMOSFET is to be formed; performing a first annealing process for activating the N-type impurity; implanting ions of P-type impurity for forming a deep junction source and drain in a second region on the semiconductor substrate where a PMOSFET is to be formed; and performing a, second annealing process for activating the P-type impurity. By performing the above processes in that order, the N-type impurity ions in the Nnull polysilicon gate electrode of the NMOSFET are sufficiently activated, thus preventing the problem of depletion. Also, fluctuation of a threshold voltage because of penetration of the P-type impurity ions in the gate electrode of the PMOSFET can be prevented in the PMOSFET.
摘要翻译：根据本发明的用于在半导体衬底上制造双栅极CMOSFET的制造方法包括：在半导体衬底上注入用于形成深接合源和漏极的N型杂质的离子在半导体衬底上的第一区域中，其中NMOSFET将形成执行用于激活N型杂质的第一退火工艺; 在要形成PMOSFET的半导体衬底上的第二区域中注入P型杂质的离子以形成深结源和漏极; 并执行用于激活P型杂质的第二退火工艺。通过以上的顺序进行上述处理，NMOSFET的N +多晶硅栅电极中的N型杂质离子被充分地激活，从而防止了耗尽的问题。此外，PMOSFET中也可以防止由于P型杂质离子在PMOSFET的栅电极中的穿透引起的阈值电压的波动。

8. 发明申请

US20020045296A1 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US20020045296A1
公开(公告)日：2002-04-18
申请号：US10023849
申请日：2001-12-21
申请人： Kabushika Kaisha Toshiba
发明人： Atsushi Yagishita , Kouji Matsuo , Yasushi Akasaka , Kyoichi Suguro , Yoshitaka Tsunashima
IPC分类号： H01L021/335
CPC分类号： H01L29/66575 , H01L21/823418 , H01L21/823437 , H01L21/823475 , H01L21/823481 , H01L21/823814 , H01L21/823828 , H01L21/823871 , H01L21/823878 , H01L27/11 , H01L27/1104 , H01L29/1033 , H01L29/41775 , H01L29/41783 , H01L29/66545 , H01L29/78 , Y10S438/926
摘要： A method of manufacturing a semiconductor device according to this invention is characterized by including the steps of a) forming, on one major surface of a substrate, a gate structure constituted by either one of a dummy gate electrode and a gate electrode having an insulating film at least on bottom surface, and a device isolation insulating film so as to form a first groove divided by the dummy gate electrode or the gate electrode, to position the dummy gate electrode or the gate electrode in the first groove, and to form the gate structure to have an upper surface level not higher than an upper level of the device isolation insulating film, and b) forming source and drain electrodes in the first groove.
摘要翻译：根据本发明的制造半导体器件的方法的特征在于包括以下步骤：a）在衬底的一个主表面上形成由伪栅电极和具有绝缘膜的栅电极中的任一个构成的栅极结构至少在底表面上，以及器件隔离绝缘膜，以形成由伪栅电极或栅电极分隔的第一凹槽，以将伪栅电极或栅电极定位在第一凹槽中，并形成栅极结构具有不高于器件隔离绝缘膜的较高电平的上表面电平，以及b）在第一沟槽中形成源极和漏极。

9. 发明申请

US20010029068A1 Semiconductor device structure including a tantalum pentoxide layer sandwiched between silicon nitride layers 有权
标题翻译：包括夹在氮化硅层之间的五氧化二钽层的半导体器件结构
公开(公告)号：US20010029068A1
公开(公告)日：2001-10-11
申请号：US09878657
申请日：2001-06-11
发明人： Sailesh Chittipeddi , Charles Walter Pearce
IPC分类号： H01L021/335
CPC分类号： H01L28/40 , H01L21/3144 , H01L21/31604 , H01L21/3185 , H01L27/0805 , H01L27/1085
摘要： An insulating structure includes a first silicon nitride layer, a tantalum pentoxide layer formed above the first silicon nitride (SiNx) layer, and a second silicon nitride layer formed above the tantalum pentoxide (Ta2O5) layer. The SiNx cladding layers prevent diffusion of the tantalum during heating. A high dielectric constant is provided. The thermal stability of the insulating structure is improved. The insulating structure may be included in a capacitor or a shallow trench isolation structure. An exemplary capacitor is formed with a substrate, a lower electrode, the three-layer SixNy/Ta2O5/SixNy structure and an upper electrode. The lower electrode may include a TiN layer formed over an aluminum layer, or a TiN layer formed over a polysilicon layer, or a polysilicon layer having an oxide barrier layer formed on it. The upper electrode may be a TiN layer or a polysilicon layer. An exemplary shallow trench isolation structure includes the SixNy/Ta2O5/SixNy structure as a liner on the sides and bottom of a shallow trench in the surface of a substrate. The shallow trench is filled with an oxide, such as TEOS. A variety of methods may be used for fabricating devices that include the SixNy/Ta2O5/SixNy structure.
摘要翻译：绝缘结构包括第一氮化硅层，形成在第一氮化硅（SiNx）层上方的五氧化二钽层和形成在五氧化二钽（Ta2O5）上方的第二氮化硅层。 SiNx覆层在加热期间防止钽的扩散。提供高介电常数。绝缘结构的热稳定性提高。绝缘结构可以包括在电容器或浅沟槽隔离结构中。示例性电容器由基板，下电极，三层SixNy / Ta2O5 / SixNy结构和上电极形成。下电极可以包括在铝层上形成的TiN层，或者形成在多晶硅层上的TiN层，或者在其上形成有氧化物阻挡层的多晶硅层。上电极可以是TiN层或多晶硅层。示例性的浅沟槽隔离结构包括作为衬底在衬底表面的浅沟槽的侧面和底部上的SixNy / Ta2O5 / SixNy结构。浅沟槽中填充有氧化物，如TEOS。可以使用各种方法来制造包括SixNy / Ta2O5 / SixNy结构的器件。

10. 发明申请

US20010019857A1 Semiconductor device and process for producing the same 失效
公开(公告)号：US20010019857A1
公开(公告)日：2001-09-06
申请号：US09770114
申请日：2001-01-23
发明人： Takashi Yokoyama , Tatsuya Usami
IPC分类号： H01L021/335
CPC分类号： H01L21/76834 , H01L21/76801 , H01L21/76802 , H01L21/76814 , H01L21/76826 , H01L21/76828 , H01L21/76831 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： An interlayer insulation film containing a dielectric component represented by a chemical formula having a SinullH bond or a Si-CH3 bond is formed on a substrate. Next, a photoresist is formed on the interlayer insulation film. The photoresist is then formed into a form of a contact hole. Thereafter, dry-etching of the interlayer insulation film is conducted by use of the photoresist as a mask. Subsequently, the photoresist is removed, and the interlayer insulation film is exposed to nitrogen plasma and hydrogen plasma, for example.

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