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71. 发明授权

US06218258B1 Method for fabricating semiconductor device including capacitor with improved bottom electrode 有权
标题翻译：一种制造半导体器件的方法，包括具有改善的底部电极的电容器
公开(公告)号：US06218258B1
公开(公告)日：2001-04-17
申请号：US09191374
申请日：1998-11-13
申请人： Jae Hyun Joo
发明人： Jae Hyun Joo
IPC分类号： H01L2120
CPC分类号： H01L28/91 , H01L27/10852 , H01L28/84 , H01L28/86
摘要： A method for fabricating a bottom electrode structure for a semiconductor capacitor. The method according to the present invention includes providing an interlayer insulating layer having a conductive plug formed therein. A first bottom electrode layer is formed on the interlayer insulating layer. An oxygen diffusion barrier layer is formed on the first bottom electrode layer. A second bottom electrode layer is formed on the first oxygen diffusion barrier layer. Thereafter, portions of the second bottom electrode layer, first oxygen diffusion barrier layer, and first bottom electrode layer are selectively removed to form a bottom electrode pattern. A third bottom electrode is formed on sidewalls of the bottom electrode pattern.
摘要翻译：一种用于制造半导体电容器的底部电极结构的方法。根据本发明的方法包括提供其中形成有导电插塞的层间绝缘层。第一底电极层形成在层间绝缘层上。在第一底部电极层上形成氧扩散阻挡层。在第一氧扩散阻挡层上形成第二底部电极层。此后，选择性地去除第二底部电极层，第一氧扩散阻挡层和第一底部电极层的部分以形成底部电极图案。第三底部电极形成在底部电极图案的侧壁上。

72. 发明授权

US06211033B1 Integrated capacitor bottom electrode for use with conformal dielectric 失效
标题翻译：集成电容器底部电极，用于保形电介质
公开(公告)号：US06211033B1
公开(公告)日：2001-04-03
申请号：US08964946
申请日：1997-11-05
申请人： Gurtej S. Sandhu , J. Brett Rolfson
发明人： Gurtej S. Sandhu , J. Brett Rolfson
IPC分类号： H01L2170
CPC分类号： H01L27/10852 , H01L28/40 , H01L28/82 , H01L28/84 , H01L28/86 , H01L28/90
摘要： Disclosed is a capacitor construction for a more uniformly thick capacitor dielectric layer, and a method for fabricating the same. The method has special utility where the bottom electrode comprises composite layers over which the capacitor dielectric demonstrates differential growth during deposition. Exposed portions of an underlying first electrode layer, are covered either by a conductive or dielectric spacer, or by a dielectric padding. For the preferred embodiments, in which the bottom electrode comprises titanium carbonitride over rough polysilicon, a dielectric padding may be formed during a rapid thermal nitridation step, which causes silicon nitride to grow out of an exposed polysilicon sidewall. Alternatively, a sidewall spacer may be formed by deposition an additional layer of titanium nitride over the original titanim nitride strap, and performing a spacer etch.
摘要翻译：公开了一种用于更均匀地厚电容器电介质层的电容器结构及其制造方法。该方法具有特殊用途，其中底部电极包括复合层，电容器电介质在其上显示沉积期间的差异生长。下面的第一电极层的暴露部分由导电或介电间隔物或介质衬垫覆盖。对于优选的实施方案，其中底部电极在粗多晶硅上包含碳氮化钛，可以在快速热氮化步骤期间形成介电填料，这导致氮化硅从露出的多晶硅侧壁生长出来。或者，侧壁间隔物可以通过在原始钛酸盐氮化物带上沉积另外的氮化钛层而形成，并且执行间隔物蚀刻。

73. 发明授权

US06190990B1 Method for manufacturing the storage node of a capacitor on a semiconductor wafer 有权
标题翻译：用于制造半导体晶片上的电容器的存储节点的方法
公开(公告)号：US06190990B1
公开(公告)日：2001-02-20
申请号：US09231707
申请日：1999-01-13
申请人： Houng-Chi Wei
发明人： Houng-Chi Wei
IPC分类号： H01L2120
CPC分类号： H01L28/86 , H01L21/31116 , H01L21/76895
摘要： The present invention provides a new method which increases the surface area of the storage node of the capacitor, the method comprising: (1) Forming a photo resistor layer with a circular hole on the surface of the semiconductor wafer; (2) Using a wet isotropic etching method to form a bowl-like shallow concavity (pit) through the hole with a radius bigger than the hole; (3) Using a dry anisotropic etching process to etch a shallow pit through the hole in the central part of the bottom of the shallow pit down through the substrate of the semiconductor wafer; and (4) Eliminating the photo resistor layer, and then depositing a doped polysilicon layer over the shallow pit and the well resulting in a recess corresponding to the shallow pit and the well, wherein the deposition layer with a recess forms the storage node of a capacitor, the storage node having a recess with a larger surface area.
摘要翻译：本发明提供了增加电容器的存储节点的表面积的新方法，该方法包括：（1）在半导体晶片的表面上形成具有圆形孔的光电阻层; （2）使用湿均匀蚀刻法，通过孔大于孔的孔形成碗状浅凹陷（凹坑）（3）使用干燥的各向异性蚀刻工艺，通过半导体晶片的基板将浅凹坑底部的中心部分的孔蚀刻成浅凹坑; （4）消除光电阻层，然后在浅坑和阱上沉积掺杂多晶硅层，产生与浅坑和阱相对应的凹陷，其中具有凹陷的沉积层形成一个电容器，存储节点具有具有较大表面积的凹部。

74. 发明授权

US6097052A Semiconductor device and a method of manufacturing thereof 失效
公开(公告)号：US6097052A
公开(公告)日：2000-08-01
申请号：US882300
申请日：1997-06-25
申请人： Yoshinori Tanaka , Mitsuya Kinoshita , Shinya Watanabe , Tatsuo Kasaoka , Moriaki Akazawa , Toshiaki Ogawa
发明人： Yoshinori Tanaka , Mitsuya Kinoshita , Shinya Watanabe , Tatsuo Kasaoka , Moriaki Akazawa , Toshiaki Ogawa
IPC分类号： H01L21/28 , H01L21/02 , H01L21/283 , H01L21/302 , H01L21/3065 , H01L21/768 , H01L21/8242 , H01L23/522 , H01L27/10 , H01L27/108
CPC分类号： H01L27/1085 , H01L21/76802 , H01L23/5226 , H01L27/10852 , H01L28/82 , H01L28/86 , H01L28/90 , H01L2924/0002
摘要： A contact hole having an opening diameter smaller than the minimum dimension that can be formed by photolithographic technique is formed. Using an interlayer insulating film 8 formed on a semiconductor substrate as an etching mask, etching is carried out halfway to form an opening 8a. The etching mask is removed, and a TEOS film 10 is formed on the interlayer oxide film 8. The whole surface is then etched anisotropically to form a contact hole 11.

75. 发明授权

US5872697A Integrated circuit having integral decoupling capacitor 失效
标题翻译：具有积分去耦电容器的集成电路
公开(公告)号：US5872697A
公开(公告)日：1999-02-16
申请号：US600533
申请日：1996-02-13
申请人： Todd Alan Christensen , John Edward Sheets, II
发明人： Todd Alan Christensen , John Edward Sheets, II
IPC分类号： H01L27/04 , H01L21/3205 , H01L21/822 , H01L23/52 , H01L23/522 , H01G4/06
CPC分类号： H01L23/5223 , H01L28/86 , H01L2924/0002
摘要： The present invention is a decoupling capacitor for an integrated circuit. The integrated circuit has a final metal layer which includes a power bus. The decoupling capacitor includes a dielectric film disposed over the final metal layer and a conductive film disposed over the dielectric layer, whereby capacitance may be provided in the dielectric layer.
摘要翻译：本发明是用于集成电路的去耦电容器。该集成电路具有包括电源总线的最终金属层。去耦电容器包括设置在最终金属层上的电介质膜和设置在电介质层上的导电膜，由此可以在电介质层中提供电容。

76. 发明授权

US5851878A Method of forming a rugged polysilicon fin structure in DRAM 失效
标题翻译：在DRAM中形成坚固的多晶硅鳍结构的方法
公开(公告)号：US5851878A
公开(公告)日：1998-12-22
申请号：US888560
申请日：1997-07-07
申请人： Hsiu-Wen Huang
发明人： Hsiu-Wen Huang
IPC分类号： H01L21/02 , H01L21/8242 , H01L27/108
CPC分类号： H01L27/10852 , H01L27/10817 , H01L28/82 , H01L28/84 , H01L28/86
摘要： The capacitor for a DRAM is formed to have a textured bottom electrode using wet etch processes. A planarized dielectric layer is formed over the transfer FETs and bit line of a capacitor over bit line DRAM cell. A layer of silicon nitride is deposited over the planarized dielectric layer. A layer of silicon oxide is deposited over the silicon nitride layer and then a contact via is etched to expose the charge storage node of a transfer FET of the DRAM cell. A layer of polysilicon is deposited over the silicon oxide layer and into the contact via to connect the polysilicon layer to the charge storage node of the transfer FET. The polysilicon layer is patterned to define bottom capacitor plates. The silicon oxide layer is etched using hydrofluoric acid to expose the bottom surface of the polysilicon bottom capacitor plate. Next, a hydrofluoric acid dip is used to create a rugged polysilicon surface on the upper and lower surfaces of the bottom capacitor electrodes. A capacitor dielectric is provided and an upper capacitor electrode is formed to complete the DRAM cell.
摘要翻译：用于DRAM的电容器形成为具有使用湿蚀刻工艺的纹理化底部电极。在位线DRAM单元上的电容器的转移FET和位线之间形成平坦化的介电层。在平坦化介电层上沉积氮化硅层。在氮化硅层上沉积氧化硅层，然后蚀刻接触通孔以暴露DRAM单元的转移FET的电荷存储节点。多晶硅层沉积在氧化硅层上并进入接触通孔中，以将多晶硅层连接到转移FET的电荷存储节点。图案化多晶硅层以限定底部电容器板。使用氢氟酸蚀刻氧化硅层以暴露多晶硅底部电容器板的底表面。接下来，使用氢氟酸浸渍在底部电容器电极的上表面和下表面上形成坚固的多晶硅表面。提供电容器电介质，并且形成上电容器电极以完成DRAM单元。

77. 发明授权

US5759895A Method of fabricating a capacitor storage node having a rugged-fin surface 失效
标题翻译：制造具有凹凸表面的电容器存储节点的方法
公开(公告)号：US5759895A
公开(公告)日：1998-06-02
申请号：US949469
申请日：1997-10-14
申请人： Horng-Huei Tseng
发明人： Horng-Huei Tseng
IPC分类号： H01L21/02 , H01L21/8242 , H01L27/108 , H01L21/20
CPC分类号： H01L27/10852 , H01L27/10817 , H01L28/82 , H01L28/84 , H01L28/86 , H01L28/90
摘要： A method of forming a high capacitance capacitor which does not require additional integrated circuit chip surface area. A capacitor storage electrode or first capacitor plate is formed from amorphous silicon and attached to a polysilicon stud. Dielectric is removed from the under side of the first capacitor plate. The amorphous silicon is then annealed at low pressure to form hemispherical grain polysilicon on the surface of the amorphous silicon thereby increasing the surface area. In one embodiment polysilicon spacers are used to increase the first capacitor plate surface area. The first capacitor plate is then covered by a conformal dielectric layer and a polysilicon second capacitor plate is formed. The capacitor extends over the active integrated circuit chip area but is above the surface of the chip and thereby does not use additional chip area.
摘要翻译：形成不需要额外的集成电路芯片表面积的高容量电容器的方法。电容器存储电极或第一电容器板由非晶硅形成并附着于多晶硅柱。电介质从第一电容器板的下侧除去。然后将非晶硅在低压下退火以在非晶硅的表面上形成半球晶粒多晶硅，从而增加表面积。在一个实施例中，使用多晶硅间隔物来增加第一电容器板表面积。第一电容器板然后被保形介电层覆盖，并且形成多晶硅第二电容器板。电容器在有源集成电路芯片区域上延伸，但是在芯片的表面之上，因此不使用额外的芯片面积。

78. 发明授权

US5705838A Array of bit line over capacitor array of memory cells 失效
标题翻译：存储单元电容阵列上的位线阵列
公开(公告)号：US5705838A
公开(公告)日：1998-01-06
申请号：US692748
申请日：1996-08-06
申请人： Mark Jost , Charles Dennison
发明人： Mark Jost , Charles Dennison
IPC分类号： H01L21/02 , H01L21/768 , H01L21/8242 , H01L27/108 , H01L29/41
CPC分类号： H01L27/10852 , H01L21/768 , H01L21/76877 , H01L27/10808 , H01L28/40 , H01L28/60 , H01L28/82 , H01L28/84 , H01L28/86 , H01L28/90 , Y10S148/05
摘要： A semiconductor memory device includes, a) a semiconductor substrate; b) a field effect transistor gate positioned outwardly of the semiconductor substrate; c) opposing active areas formed within the semiconductor substrate on opposing sides of the gate; d) a capacitor electrically connected with one of the active areas; the capacitor comprising an inner storage node, a capacitor dielectric layer, and an outer cell node; the inner storage node electrically connecting with the one active area, the inner storage node having an upper surface at an elevation; e) a bit line; f) a dielectric insulating layer positioned intermediate the bit line and the other active area; and g) an electrically conductive bit line plug extending through the insulating layer to contact with the other active area and electrically interconnect the bit line with the other active area, the bit line plug being homogeneous in composition between the other active area and the elevation of the inner storage node upper surface. A method of producing such a construction is also disclosed.
摘要翻译：半导体存储器件包括：a）半导体衬底; b）位于半导体衬底外侧的场效应晶体管栅极; c）在栅极的相对侧上形成在半导体衬底内的相对的有源区; d）与有源区域之一电连接的电容器; 所述电容器包括内部存储节点，电容器介电层和外部单元节点; 所述内部存储节点与所述一个活动区域电连接，所述内部存储节点具有在高度处的上表面; e）有点线 f）位于位线和另一个有效区域之间的介电绝缘层; 并且g）导电位线插头，其延伸穿过所述绝缘层以与所述另一有源区域接触并且将所述位线与所述另一个有源区域电互连，所述位线插头在所述另一个有效区域和内部存储节点上表面。还公开了一种制造这种结构的方法。

79. 发明公开

US20240213132A1 THIN FILM CAPACITORS (TFCS) IN ETCHED BACK DEEP VIA 审中-公开
公开(公告)号：US20240213132A1
公开(公告)日：2024-06-27
申请号：US18089476
申请日：2022-12-27
申请人： Intel Corporation
发明人： Kristof DARMAWIKARTA , Benjamin DUONG , Darko GRUJICIC , Shayan KAVIANI , Mahdi MOHAMMADIGHALENI , Suddhasattwa NAD , Thomas L. SOUNART , Marcel WALL , Ravindranath V. MAHAJAN , Rahul N. MANEPALLI
IPC分类号： H01L23/498 , H01L27/01
CPC分类号： H01L23/49838 , H01L27/016 , H01L28/86 , H01L28/90 , H01L23/49822 , H01L23/49894 , H01L24/16
摘要： Embodiments disclosed herein include an electronic package. In an embodiment, the electronic package comprises a package substrate, where the package substrate comprises a plurality of stacked dielectric layers. In an embodiment, the electronic package further comprises an opening into the package substrate, where the opening passes through at least two of the plurality of dielectric layers. In an embodiment, a first pad is at the bottom of the opening, a capacitor is disposed in the opening, and a second pad is over the capacitor.

80. 发明公开

US20240130046A1 CAPACITOR 审中-公开
公开(公告)号：US20240130046A1
公开(公告)日：2024-04-18
申请号：US18546526
申请日：2021-02-22
申请人： Nippon Telegraph and Telephone Corporation
发明人： Teruo Jo , Munehiko Nagatani , Hideyuki Nosaka
IPC分类号： H05K1/18
CPC分类号： H05K1/185 , H01L28/86 , H05K2201/10015
摘要： A capacitor includes a pair of facing stacked electrodes connected to an electrical wiring from the outside. The stacked electrode includes a plurality of wiring layers and a via layer between the wiring layers. The stacked electrode includes combs and a comb connection portion connected to base ends of the combs. A dielectric is provided between one stacked electrode and the other stacked electrode. The comb of the other stacked electrode is disposed between the combs of the one stacked electrode.

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