专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US5754390A Integrated capacitor bottom electrode for use with conformal dielectric 失效
公开(公告)号：US5754390A
公开(公告)日：1998-05-19
申请号：US589899
申请日：1996-01-23
申请人： Gurtej S. Sandhu , J. Brett Rolfson
发明人： Gurtej S. Sandhu , J. Brett Rolfson
IPC分类号： H01L21/02 , H01L21/8242 , H01G4/06
CPC分类号： H01L27/10852 , H01L28/40 , H01L28/82 , H01L28/84 , H01L28/86 , H01L28/90
摘要： Disclosed is a capacitor construction for a more uniformly thick capacitor dielectric layer, and a method for fabricating the same. The method has special utility where the bottom electrode comprises composite layers over which the capacitor dielectric demonstrates differential growth during deposition. Exposed portions of an underlying first electrode layer, are covered either by a conductive or dielectric spacer, or by a dielectric padding. For the preferred embodiments, in which the bottom electrode comprises titanium carbonitride over rough polysilicon, a dielectric padding may be formed during a rapid thermal nitridation step, which causes silicon nitride to grow out of an exposed polysilicon sidewall. Alternatively, a sidewall spacer may be formed by deposition an additional layer of titanium nitride over the original titanim nitride strap, and performing a spacer etch.

2. 发明授权

US06838338B2 Integrated capacitor bottom electrode for use with conformal dielectric 失效
标题翻译：集成电容器底部电极，用于保形电介质
公开(公告)号：US06838338B2
公开(公告)日：2005-01-04
申请号：US10378019
申请日：2003-02-27
申请人： Gurtej S. Sandhu , J. Brett Rolfson
发明人： Gurtej S. Sandhu , J. Brett Rolfson
IPC分类号： H01L21/02 , H01L21/8242 , H01L21/20
CPC分类号： H01L27/10852 , H01L28/40 , H01L28/82 , H01L28/84 , H01L28/86 , H01L28/90
摘要： Disclosed is a capacitor construction for a more uniformly thick capacitor dielectric layer, and a method for fabricating the same. The method has special utility where the bottom electrode comprises composite layers over which the capacitor dielectric demonstrates differential growth during deposition. Exposed portions of an underlying first electrode layer, are covered either by a conductive or dielectric spacer, or by a dielectric padding. For the preferred embodiments, in which the bottom electrode comprises titanium carbonitride over rough polysilicon, a dielectric padding may be formed during a rapid thermal nitridation step, which causes silicon nitride to grow out of an exposed polysilicon sidewall. Alternatively, a sidewall spacer may be formed by deposition an additional layer of titanium nitride over the original titanim nitride strap, and performing a spacer etch.
摘要翻译：公开了一种用于更均匀地厚电容器电介质层的电容器结构及其制造方法。该方法具有特殊用途，其中底部电极包括复合层，电容器电介质在其上显示沉积期间的差异生长。下面的第一电极层的暴露部分由导电或介电间隔物或介质衬垫覆盖。对于优选的实施方案，其中底部电极在粗多晶硅上包含碳氮化钛，可以在快速热氮化步骤期间形成介电填料，这导致氮化硅从露出的多晶硅侧壁生长出来。或者，侧壁间隔物可以通过在原始钛酸盐氮化物带上沉积另外的氮化钛层而形成，并且执行间隔物蚀刻。

3. 发明授权

US06211033B1 Integrated capacitor bottom electrode for use with conformal dielectric 失效
标题翻译：集成电容器底部电极，用于保形电介质
公开(公告)号：US06211033B1
公开(公告)日：2001-04-03
申请号：US08964946
申请日：1997-11-05
申请人： Gurtej S. Sandhu , J. Brett Rolfson
发明人： Gurtej S. Sandhu , J. Brett Rolfson
IPC分类号： H01L2170
CPC分类号： H01L27/10852 , H01L28/40 , H01L28/82 , H01L28/84 , H01L28/86 , H01L28/90
摘要： Disclosed is a capacitor construction for a more uniformly thick capacitor dielectric layer, and a method for fabricating the same. The method has special utility where the bottom electrode comprises composite layers over which the capacitor dielectric demonstrates differential growth during deposition. Exposed portions of an underlying first electrode layer, are covered either by a conductive or dielectric spacer, or by a dielectric padding. For the preferred embodiments, in which the bottom electrode comprises titanium carbonitride over rough polysilicon, a dielectric padding may be formed during a rapid thermal nitridation step, which causes silicon nitride to grow out of an exposed polysilicon sidewall. Alternatively, a sidewall spacer may be formed by deposition an additional layer of titanium nitride over the original titanim nitride strap, and performing a spacer etch.
摘要翻译：公开了一种用于更均匀地厚电容器电介质层的电容器结构及其制造方法。该方法具有特殊用途，其中底部电极包括复合层，电容器电介质在其上显示沉积期间的差异生长。下面的第一电极层的暴露部分由导电或介电间隔物或介质衬垫覆盖。对于优选的实施方案，其中底部电极在粗多晶硅上包含碳氮化钛，可以在快速热氮化步骤期间形成介电填料，这导致氮化硅从露出的多晶硅侧壁生长出来。或者，侧壁间隔物可以通过在原始钛酸盐氮化物带上沉积另外的氮化钛层而形成，并且执行间隔物蚀刻。

4. 发明授权

US06555432B2 Integrated capacitor bottom electrode for use with conformal dielectric 失效
公开(公告)号：US06555432B2
公开(公告)日：2003-04-29
申请号：US09733820
申请日：2000-12-08
申请人： Gurtej S. Sandhu , J. Brett Rolfson
发明人： Gurtej S. Sandhu , J. Brett Rolfson
IPC分类号： H01L218242
CPC分类号： H01L27/10852 , H01L28/40 , H01L28/82 , H01L28/84 , H01L28/86 , H01L28/90
摘要： Disclosed is a capacitor construction for a more uniformly thick capacitor dielectric layer, and a method for fabricating the same. The method has special utility where the bottom electrode comprises composite layers over which the capacitor dielectric demonstrates differential growth during deposition. Exposed portions of an underlying first electrode layer, are covered either by a conductive or dielectric spacer, or by a dielectric padding. For the preferred embodiments, in which the bottom electrode comprises titanium carbonitride over rough polysilicon, a dielectric padding may be formed during a rapid thermal nitridation step, which causes silicon nitride to grow out of an exposed polysilicon sidewall. Alternatively, a sidewall spacer may be formed by deposition an additional layer of titanium nitride over the original titanim nitride strap, and performing a spacer etch.

5. 发明授权

US09099314B2 Pitch multiplication spacers and methods of forming the same 有权
标题翻译：间距倍增器及其形成方法
公开(公告)号：US09099314B2
公开(公告)日：2015-08-04
申请号：US12827506
申请日：2010-06-30
申请人： Gurtej S. Sandhu , Kirk D. Prall
发明人： Gurtej S. Sandhu , Kirk D. Prall
IPC分类号： H01L21/3213 , H01L21/033 , H01L21/308 , H01L21/3205
CPC分类号： H01L21/67063 , H01L21/0337 , H01L21/0338 , H01L21/3086 , H01L21/3088 , H01L21/32053 , H01L21/32134
摘要： Spacers in a pitch multiplication process are formed without performing a spacer etch. Rather, the mandrels are formed over a substrate and then the sides of the mandrels are reacted, e.g., in an oxidization, nitridation, or silicidation step, to form a material that can be selectively removed relative to the unreacted portions of the mandrel. The unreacted portions are selectively removed to leave a pattern of free-standing spacers. The free-standing spacers can serve as a mask for subsequent processing steps, such as etching the substrate.
摘要翻译：在不执行间隔物蚀刻的情况下形成间距倍增过程中的间隔物。相反，心轴形成在衬底上，然后心轴的侧面例如在氧化，氮化或硅化步骤中反应，以形成相对于心轴的未反应部分可以选择性去除的材料。选择性地去除未反应部分以留下独立间隔物的图案。独立的间隔物可以用作后续处理步骤的掩模，例如蚀刻基底。

6. 发明授权

US08999492B2 Method to produce nanometer-sized features with directed assembly of block copolymers 有权
标题翻译：通过嵌段共聚物的定向组装制备纳米尺寸特征的方法
公开(公告)号：US08999492B2
公开(公告)日：2015-04-07
申请号：US12026214
申请日：2008-02-05
申请人： Dan B. Millward , Gurtej S. Sandhu
发明人： Dan B. Millward , Gurtej S. Sandhu
IPC分类号： G03G7/00 , B05D5/02 , C08F2/46 , C03C25/68 , G03F7/00 , B81C99/00 , B82Y10/00 , B05D1/28 , B82Y30/00 , B82Y40/00
CPC分类号： B41N1/08 , B05D1/283 , B41N3/036 , B81C99/009 , B81C2201/0149 , B82Y10/00 , B82Y30/00 , B82Y40/00 , G03F7/0002 , G03F7/0017 , Y02C20/30 , Y10T428/24802
摘要： Methods for fabricating stamps and systems for patterning a substrate, and devices resulting from those methods are provided.
摘要翻译：提供用于制造用于图案化衬底的印记和系统的方法以及由这些方法产生的器件。

7. 发明授权

US08946903B2 Electrically conductive laminate structure containing graphene region 有权
标题翻译：导电层压结构
公开(公告)号：US08946903B2
公开(公告)日：2015-02-03
申请号：US12833074
申请日：2010-07-09
申请人： Gurtej S. Sandhu
发明人： Gurtej S. Sandhu
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40 , H01B13/00 , H01L21/768 , H01L23/532
CPC分类号： H01L23/53276 , H01L21/76805 , H01L21/76843 , H01L21/76847 , H01L21/76865 , H01L21/76877 , H01L23/53209 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： Some embodiments include electrical interconnects. The interconnects may contain laminate structures having a graphene region sandwiched between non-graphene regions. In some embodiments the graphene and non-graphene regions may be nested within one another. In some embodiments an electrically insulative material may be over an upper surface of the laminate structure, and an opening may extend through the insulative material to a portion of the laminate structure. Electrically conductive material may be within the opening and in electrical contact with at least one of the non-graphene regions of the laminate structure. Some embodiments include methods of forming electrical interconnects in which non-graphene material and graphene are alternately formed within a trench to form nested non-graphene and graphene regions.
摘要翻译：一些实施例包括电互连。互连可以包含层压结构，其具有夹在非石墨烯区域之间的石墨烯区域。在一些实施例中，石墨烯和非石墨烯区域可以彼此嵌套。在一些实施例中，电绝缘材料可以在层压结构的上表面之上，并且开口可以延伸穿过绝缘材料到层压结构的一部分。导电材料可以在开口内并且与层压结构的非石墨烯区域中的至少一个电接触。一些实施例包括形成电互连的方法，其中在沟槽内交替形成非石墨烯材料和石墨烯以形成嵌套的非石墨烯和石墨烯区域。

8. 发明授权

US08923038B2 Memory cells, semiconductor device structures, memory systems, and methods of fabrication 有权
标题翻译：存储单元，半导体器件结构，存储器系统和制造方法
公开(公告)号：US08923038B2
公开(公告)日：2014-12-30
申请号：US13527173
申请日：2012-06-19
申请人： Witold Kula , Gurtej S. Sandhu , Stephen J. Kramer
发明人： Witold Kula , Gurtej S. Sandhu , Stephen J. Kramer
IPC分类号： G11C11/15 , G11C11/00 , H01L29/82
CPC分类号： H01L43/08 , G11C11/161 , H01L27/228 , H01L43/02 , H01L43/12
摘要： Methods of forming magnetic memory cells are disclosed. Magnetic and non-magnetic materials are formed into a primal precursor structure in an initial stress state of essentially no strain, compressive strain, or tensile strain. A stress-compensating material, e.g., a non-sacrificial, conductive material, is formed to be disposed on the primal precursor structure to form a stress-compensated precursor structure in a net beneficial stress state. Thereafter, the stress-compensated precursor structure may be patterned to form a cell core of a memory cell. The net beneficial stress state of the stress-compensated precursor structure lends to formation of one or more magnetic regions, in the cell core, exhibiting a vertical magnetic orientation without deteriorating a magnetic strength of the one or more magnetic regions. Also disclosed are memory cells, memory cell structures, semiconductor device structures, and spin torque transfer magnetic random access memory (STT-MRAM) systems.
摘要翻译：公开了形成磁存储器单元的方法。磁性和非磁性材料在基本上没有应变，压缩应变或拉伸应变的初始应力状态下形成原始前体结构。形成应力补偿材料，例如非牺牲导电材料，以设置在原始前体结构上以在净有益应力状态下形成应力补偿前体结构。此后，应力补偿前体结构可以被图案化以形成存储单元的单元芯。应力补偿前体结构的净有益应力状态有助于在电池芯中形成一个或多个磁性区域，呈现垂直磁性取向而不会使一个或多个磁性区域的磁强度恶化。还公开了存储器单元，存储单元结构，半导体器件结构和自旋转矩传递磁随机存取存储器（STT-MRAM）系统。

9. 发明授权

US08772841B2 Reactive metal implated oxide based memory 有权
标题翻译：反应性金属注入氧化物基记忆
公开(公告)号：US08772841B2
公开(公告)日：2014-07-08
申请号：US13616307
申请日：2012-09-14
申请人： D.V. Nirmal Ramaswamy , Gurtej S. Sandhu
发明人： D.V. Nirmal Ramaswamy , Gurtej S. Sandhu
IPC分类号： H01L29/66 , H01L29/94 , H01L21/70 , H01L27/108
CPC分类号： H01L45/08 , G11C13/0007 , H01L45/145 , H01L45/165
摘要： Methods, devices, and systems associated with oxide based memory can include a method of forming an oxide based memory cell. Forming an oxide based memory cell can include forming a first conductive element, forming an oxide over the first conductive element, implanting a reactive metal into the oxide, and forming a second conductive element over the oxide.
摘要翻译：与基于氧化物的存储器相关联的方法，装置和系统可以包括形成基于氧化物的存储器单元的方法。形成基于氧化物的存储单元可以包括形成第一导电元件，在第一导电元件上形成氧化物，将活性金属注入到氧化物中，以及在氧化物上形成第二导电元件。

10. 发明授权

US08686535B2 Trench isolation implantation 有权
标题翻译：沟槽隔离植入
公开(公告)号：US08686535B2
公开(公告)日：2014-04-01
申请号：US12758488
申请日：2010-04-12
申请人： Gurtej S. Sandhu , John A. Smythe, III
发明人： Gurtej S. Sandhu , John A. Smythe, III
IPC分类号： H01L21/70
CPC分类号： H01L21/76237 , G11C11/401 , H01L27/10844 , H01L27/11517
摘要： Embodiments of the disclosure include a shallow trench isolation structure having a dielectric material with energetic species implanted to a predetermined depth of the dielectric material. Embodiments further include methods of fabricating the trench structures with the implant of energetic species to the predetermined depth. In various embodiments the implant of energetic species is used to densify the dielectric material to provide a uniform wet etch rate across the surface of the dielectric material. Embodiments also include memory devices, integrated circuits, and electronic systems that include shallow trench isolation structures having the dielectric material with the high flux of energetic species implanted to the predetermined depth of the dielectric material.
摘要翻译：本公开的实施例包括浅沟槽隔离结构，其具有将能量物质注入电介质材料的预定深度的电介质材料。实施例还包括使能量物质的植入物到预定深度制造沟槽结构的方法。在各种实施例中，能量物质的注入用于致密化电介质材料，以提供穿过电介质材料表面的均匀的湿蚀刻速率。实施例还包括存储器件，集成电路和电子系统，其包括浅沟槽隔离结构，其具有植入到介电材料的预定深度的高能量物质的高通量的电介质材料。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式