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71. 发明授权

US08767441B2 Switching device having a non-linear element 有权
标题翻译：具有非线性元件的开关装置
公开(公告)号：US08767441B2
公开(公告)日：2014-07-01
申请号：US13921157
申请日：2013-06-18
申请人： Crossbar, Inc.
发明人： Wei Lu , Sung Hyun Jo , Hagop Nazarian
IPC分类号： G11C11/00 , H01L45/00
CPC分类号： G11C13/004 , G11C13/0004 , G11C13/0007 , G11C13/003 , G11C13/0069 , G11C13/0097 , G11C2213/15 , G11C2213/56 , G11C2213/73 , G11C2213/76 , H01L27/101 , H01L27/2409 , H01L27/2463 , H01L45/085 , H01L45/1233 , H01L45/145 , H01L45/148
摘要： Method for a memory including a first, second, third and fourth cells include applying a read, program, or erase voltage, the first and second cells coupled to a first top interconnect, the third and fourth cells coupled to a second top interconnect, the first and third cells coupled to a first bottom interconnect, the second and fourth cells are to a second bottom interconnect, each cell includes a switching material overlying a non-linear element (NLE), the resistive switching material is associated with a first conductive threshold voltage, the NLE is associated with a lower, second conductive threshold voltage, comprising applying the read voltage between the first top and the first bottom electrode to switch the NLE of the first cell to conductive, while the NLEs of the second, third, and the fourth cells remain non-conductive, and detecting a read current across the first cell in response to the read voltage.
摘要翻译：包括第一，第二，第三和第四单元的存储器的方法包括施加读取，编程或擦除电压，耦合到第一顶部互连的第一和第二单元，耦合到第二顶部互连的第三和第四单元，第一和第三单元耦合到第一底部互连，第二和第四单元到第二底部互连，每个单元包括覆盖非线性元件（NLE）的开关材料，所述电阻开关材料与第一导电阈值相关联电压，NLE与较低的第二导电阈值电压相关联，包括在第一顶部和第一底部电极之间施加读取电压以将第一个电池的NLE切换到导电，而第二个，第三个和第三个电极的NLE 第四单元保持不导通，并且响应于读取电压检测穿过第一单元的读取电流。

72. 发明申请

US20140146594A1 DESIGNING METHOD OF NON-VOLATILE MEMORY DEVICE, MANUFACTURING METHOD OF NON-VOLATILE MEMORY DEVICE, AND NON-VOLATILE MEMORY DEVICE 有权
标题翻译：非易失性存储器件的设计方法，非易失性存储器件的制造方法和非易失性存储器件
公开(公告)号：US20140146594A1
公开(公告)日：2014-05-29
申请号：US14123458
申请日：2013-04-03
申请人： PANASONIC CORPORATION
发明人： Yukio Hayakawa , Kiyotaka Tsuji , Shinichi Yoneda , Akifumi Kawahara
IPC分类号： G11C13/00 , G06F17/50 , H01L45/00 , G11C5/06
CPC分类号： G11C13/0002 , G06F17/5068 , G11C5/063 , G11C13/0007 , G11C13/0069 , G11C2013/0073 , G11C2013/0078 , G11C2213/15 , H01L27/2409 , H01L27/2463 , H01L45/04 , H01L45/146 , H01L45/16 , H01L45/1666
摘要： A method of designing a cross-point non-volatile memory device including memory elements arranged in (N×M) matrix, each of the memory elements including a variable resistance element and a bidirectional current steering element connected in series with the variable resistance element, the method comprises the step of: when an absolute value of a low-resistance state writing voltage is VR and an absolute value of a current flowing through the variable resistance element having changed to a low-resistance state by application of the low-resistance state writing voltage to both ends of the variable resistance element in a high-resistance state is Ion, and a relationship between a voltage V0 applied to both ends of the bidirectional current steering element and a current I flowing through the bidirectional current steering element is approximated as |V0|=a×Log(I)+b, deciding N, M, VR, Ion, a, and b such that b−VR/2>a×[Log {(N−1)×(M−1)}−Log(Ion)] is satisfied (S101).
摘要翻译：一种设计包括以（N×M）矩阵排列的存储元件的交叉点非易失性存储器件的方法，每个存储元件包括与可变电阻元件串联连接的可变电阻元件和双向电流操舵元件，该方法包括以下步骤：当低电阻状态写入电压的绝对值为VR并且流过可变电阻元件的电流的绝对值已经通过施加低电阻状态而变为低电阻状态在高电阻状态下向可变电阻元件的两端写入电压为Ion，并且施加到双向电流操舵元件的两端的电压V0与流过双向电流导向元件的电流I之间的关系近似为 | V0 | = a×Log（I）+ b，决定N，M，VR，Ion，a和b，使得b-VR / 2> a×[Log {（N-1）×（M-1） } -Log（Ion）]（S101）。

73. 发明申请

US20140146593A1 Method And Structure For Resistive Switching Random Access Memory With High Reliable And High Density 有权
标题翻译：高可靠，高密度电阻式开关随机存取存储器的方法与结构
公开(公告)号：US20140146593A1
公开(公告)日：2014-05-29
申请号：US13688968
申请日：2012-11-29
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, L
发明人： Chun-Yang Tsai , Yu-Wei Ting , Kuo-Ching Huang
IPC分类号： H01L45/00 , G11C11/21
CPC分类号： G11C13/0069 , G11C11/21 , G11C13/0007 , G11C13/0097 , G11C2013/0083 , G11C2213/15 , G11C2213/79 , H01L27/2436 , H01L27/2463 , H01L45/08 , H01L45/1233 , H01L45/1253 , H01L45/145 , H01L45/146 , H01L45/1625 , H01L45/1641
摘要： The present disclosure provides a resistive random access memory (RRAM) structure. The RRAM structure includes a bottom electrode on a substrate; a resistive material layer on the bottom electrode, the resistive material layer having filament features with a filament ratio greater than about 0.5; and a top electrode on the resistive material layer.
摘要翻译：本公开提供了一种电阻随机存取存储器（RRAM）结构。 RRAM结构包括在基板上的底部电极; 底部电极上的电阻材料层，电阻材料层具有长丝特征，细丝比率大于约0.5; 和电阻材料层上的顶部电极。

74. 发明申请

US20140097395A1 RESISTIVE MEMORY DEVICE FABRICATED FROM SINGLE POLYMER MATERIAL 审中-公开
标题翻译：由单一聚合物材料制成的电阻式存储器件
公开(公告)号：US20140097395A1
公开(公告)日：2014-04-10
申请号：US14048318
申请日：2013-10-08
申请人： SAUDI BASIC INDUSTRIES CORPORATION
发明人： Mohd Adnan Khan , Unnat S. Bhansali , Mahmoud N. Almadhoun , Husam N. Alshareef
IPC分类号： H01L45/00
CPC分类号： H01L45/1253 , G11C13/0016 , G11C2213/15 , H01L27/281 , H01L45/16 , H01L51/0037 , H01L51/0575 , H01L51/0591 , H01L51/102
摘要： A polymer-based device comprising a substrate; a first electrode disposed on the substrate; an active polymer layer disposed on and in contact with the first electrode; and a second electrode disposed on and in contact with the active polymer layer, wherein the first and the second electrodes are organic electrodes comprising a doped electroconductive organic polymer, the active polymer layer comprises the electroconductive organic polymer of the first and the second electrodes, and the first and the second electrodes have conductivity at least three orders of magnitude higher than the conductivity of the active polymer layer.
摘要翻译：一种基于聚合物的装置，包括基底; 设置在所述基板上的第一电极; 设置在第一电极上并与第一电极接触的活性聚合物层; 以及设置在所述活性聚合物层上并与所述活性聚合物层接触的第二电极，其中所述第一和第二电极是包含掺杂的导电有机聚合物的有机电极，所述活性聚合物层包含所述第一和第二电极的导电有机聚合物，以及第一和第二电极具有比活性聚合物层的电导率高至少三个数量级的导电性。

75. 发明授权

US08687402B2 Silicon-based nanoscale resistive device with adjustable resistance 有权
标题翻译：基于硅的纳米级电阻器件，具有可调电阻
公开(公告)号：US08687402B2
公开(公告)日：2014-04-01
申请号：US12575921
申请日：2009-10-08
申请人： Wei Lu , Sung Hyun Jo , Kuk-Hwan Kim
发明人： Wei Lu , Sung Hyun Jo , Kuk-Hwan Kim
IPC分类号： G11C11/21
CPC分类号： G11C13/0069 , G11C11/56 , G11C13/0002 , G11C13/003 , G11C2213/11 , G11C2213/15 , G11C2213/33 , G11C2213/72 , G11C2213/76 , H01L27/2409 , H01L27/2436 , H01L27/2463 , H01L45/085 , H01L45/1233 , H01L45/1253 , H01L45/148
摘要： A non-volatile solid state resistive device that includes a first electrode, a p-type poly-silicon second electrode, and a non-crystalline silicon nanostructure electrically connected between the electrodes. The nanostructure has a resistance that is adjustable in response to a voltage being applied to the nanostructure via the electrodes. The nanostructure can be formed as a nanopillar embedded in an insulating layer located between the electrodes. The first electrode can be a silver or other electrically conductive metal electrode. A third (metal) electrode can be connected to the p-type poly-silicon second electrode at a location adjacent the nanostructure to permit connection of the two metal electrodes to other circuitry. The resistive device can be used as a unit memory cell of a digital non-volatile memory device to store one or more bits of digital data by varying its resistance between two or more values.
摘要翻译：一种非挥发性固态电阻器件，其包括电连接在电极之间的第一电极，p型多晶硅第二电极和非晶硅纳米结构。纳米结构具有响应于通过电极施加到纳米结构的电压而可调节的电阻。纳米结构可以形成为嵌入位于电极之间的绝缘层中的纳米柱。第一电极可以是银或其它导电金属电极。第三（金属）电极可以在邻近纳米结构的位置处连接到p型多晶硅第二电极，以允许将两个金属电极连接到其它电路。电阻器件可以用作数字非易失性存储器件的单元存储单元，以通过改变其两个或多个值之间的电阻来存储一位或多位数字数据。

76. 发明申请

US20140061579A1 NONVOLATILE MEMORY ELEMENT AND NONVOLATILE MEMORY DEVICE 有权
标题翻译：非易失性存储元件和非易失性存储器件
公开(公告)号：US20140061579A1
公开(公告)日：2014-03-06
申请号：US13995383
申请日：2012-10-22
申请人： Zhiqiang Wei , Takeshi Takagi , Koji Katayama
发明人： Zhiqiang Wei , Takeshi Takagi , Koji Katayama
IPC分类号： H01L45/00 , H01L27/24
CPC分类号： H01L45/145 , G11C11/5685 , G11C13/0007 , G11C13/004 , G11C13/0069 , G11C2013/0073 , G11C2013/0083 , G11C2213/15 , H01L27/101 , H01L27/2463 , H01L45/08 , H01L45/146 , H01L45/1625
摘要： A variable resistance nonvolatile memory element includes a first electrode, a second electrode, and a variable resistance layer including: a first oxide layer including a metal oxide having non-stoichiometric composition and including p-type carriers; a second oxide layer located between and in contact with the first oxide layer and a second electrode and including a metal oxide having non-stoichiometric composition and including n-type carriers; an oxygen reservoir region located in the first oxide layer, having no contact with the first electrode, and having an oxygen content atomic percentage higher than that of the first oxide layer; and a local region located in the second oxide layer, having contact with the oxygen reservoir region, and having an oxygen content atomic percentage lower than that of the second oxide layer.
摘要翻译：可变电阻非易失性存储元件包括第一电极，第二电极和可变电阻层，包括：包含具有非化学计量组成的金属氧化物并包括p型载流子的第一氧化物层; 位于第一氧化物层之间并与第一氧化物层接触的第二氧化物层和第二电极，并且包括具有非化学计量组成并包括n型载体的金属氧化物; 位于所述第一氧化物层中的与第一电极没有接触并且氧含量原子百分比高于第一氧化物层的氧储存区; 以及位于所述第二氧化物层中的与氧储存区接触并且氧含量原子百分比低于第二氧化物层的原子百分比的局部区域。

77. 发明授权

US08654560B2 Variable resistance memory with a select device 有权
标题翻译：具有选择装置的可变电阻存储器
公开(公告)号：US08654560B2
公开(公告)日：2014-02-18
申请号：US13252827
申请日：2011-10-04
申请人： Wim Deweerd , Yun Wang , Prashant Phatak , Tony Chiang
发明人： Wim Deweerd , Yun Wang , Prashant Phatak , Tony Chiang
IPC分类号： G11C11/00
CPC分类号： G11C13/0004 , G11C13/0007 , G11C13/0011 , G11C13/003 , G11C13/0069 , G11C2013/0073 , G11C2213/15 , G11C2213/56 , G11C2213/71 , G11C2213/76
摘要： According to various embodiments, a variable resistance memory element and memory element array that uses variable resistance changes includes a select device, such as an ovonic threshold switch. The memory elements are able to switch during the very brief period when a transient pulse voltage is visible to the memory element.
摘要翻译：根据各种实施例，使用可变电阻变化的可变电阻存储器元件和存储元件阵列包括选择器件，诸如椭圆形阈值开关。存储器元件能够在瞬态脉冲电压对存储元件可见时的非常短的时间段内切换。

78. 发明申请

US20140003139A1 MEMORY DEVICES WITH IN-BIT CURRENT LIMITERS 有权
标题翻译：带有电流限制的存储器件
公开(公告)号：US20140003139A1
公开(公告)日：2014-01-02
申请号：US13536602
申请日：2012-06-28
申请人： Matthew D. Pickett , Gilberto Medeiros Ribeiro
发明人： Matthew D. Pickett , Gilberto Medeiros Ribeiro
IPC分类号： G11C11/00
CPC分类号： G11C11/39 , G11C13/0007 , G11C13/003 , G11C13/0069 , G11C2213/15 , G11C2213/55 , G11C2213/56
摘要： A memory device includes a first conductive layer, a second conductive layer, an in-bit current limiter including a voltage controlled negative differential resistance (VC-NDR) layer in electrical contact with the first conductive layer and a memristor element in electrical contact with the VC-NDR layer and the second conductive layer. A method for programming a memory device that comprises a VC-NDR device is also provided.
摘要翻译：存储器件包括第一导电层，第二导电层，包含与第一导电层电接触的电压控制负差动电阻（VC-NDR）层的位内限流器和与该第一导电层电接触的阻尼器元件 VC-NDR层和第二导电层。还提供了一种用于编程包括VC-NDR设备的存储设备的方法。

79. 发明授权

US08587988B2 Memory element, stacking, memory matrix and method for operation 有权
标题翻译：存储元件，堆叠，存储矩阵和操作方法
公开(公告)号：US08587988B2
公开(公告)日：2013-11-19
申请号：US13261044
申请日：2010-05-08
申请人： Eike Linn , Carsten Kuegeler , Roland Daniel Rosezin , Rainer Waser
发明人： Eike Linn , Carsten Kuegeler , Roland Daniel Rosezin , Rainer Waser
IPC分类号： G11C11/00 , G11C11/34 , G11C7/00
CPC分类号： G11C13/0002 , G11C13/00 , G11C13/004 , G11C13/0069 , G11C13/02 , G11C2013/0073 , G11C2213/15 , G11C2213/71 , G11C2213/77 , H03K19/177
摘要： Disclosed is a memory element, a stack, and a memory matrix in which the memory element can be used. Also disclosed is a method for operating the memory matrix, and to a method for determining the true value of a logic operation in an array comprising memory elements. The memory element has at least a first stable state 0 and a second stable state 1. By applying a first write voltage V0, this memory element can be transferred into the high-impedance state 0 and by applying a second write voltage V1, it can be transferred into the likewise high-impedance state 1. By applying a read voltage VR, the magnitude of which is smaller than the write voltages V0 and V1, the memory element exhibits different electrical resistance values. In the parasitic current paths occurring in a memory matrix, the memory element acts as a high-impedance resistor, without in principle being limited to unipolar switching. A method has been disclosed, using an array comprising the memory elements which can be turned into a gate for arbitrary logic operations.
摘要翻译：公开了存储元件，堆叠和存储器矩阵，其中可以使用存储元件。还公开了一种用于操作存储器矩阵的方法，以及用于确定包括存储器元件的阵列中的逻辑运算的真实值的方法。存储元件具有至少第一稳定状态0和第二稳定状态1.通过施加第一写入电压V0，该存储元件可以被转移到高阻抗状态0并且通过施加第二写入电压V1，它可以被转移到同样的高阻抗状态1.通过施加其电压值大于写入电压V0和V1的读取电压VR，存储元件表现出不同的电阻值。在存储矩阵中发生的寄生电流路径中，存储元件充当高阻抗电阻，原则上不限于单极开关。已经公开了一种使用包括可以变成用于任意逻辑运算的门的存储器元件的阵列的方法。

80. 发明授权

US08569728B2 Nonvolatile memory with variable resistance change layers 有权
标题翻译：具有可变电阻变化层的非易失性存储器
公开(公告)号：US08569728B2
公开(公告)日：2013-10-29
申请号：US12728579
申请日：2010-03-22
申请人： Kensuke Takano , Yoshio Ozawa , Katsuyuki Sekine , Junichi Wada
发明人： Kensuke Takano , Yoshio Ozawa , Katsuyuki Sekine , Junichi Wada
IPC分类号： H01L29/02
CPC分类号： H01L45/08 , G11C11/5685 , G11C13/0007 , G11C2213/15 , G11C2213/32 , G11C2213/34 , G11C2213/71 , H01L27/2436 , H01L27/2463 , H01L27/2481 , H01L45/12 , H01L45/1233 , H01L45/1253 , H01L45/145 , H01L45/146 , H01L45/1608 , H01L45/1666
摘要： A nonvolatile memory device includes: a first conductive layer; a second conductive layer; a first resistance change layer provided between the first conductive layer and the second conductive layer and having an electrical resistance changing with at least one of an applied electric field and a passed current; and a first lateral layer provided on a lateral surface of the first resistance change layer and having an oxygen concentration higher than an oxygen concentration in the first resistance change layer.
摘要翻译：非易失性存储器件包括：第一导电层; 第二导电层; 第一电阻变化层，设置在所述第一导电层和所述第二导电层之间，并且具有通过施加电场和通过电流中的至少一个而改变的电阻; 以及设置在所述第一电阻变化层的侧表面上并且具有高于所述第一电阻变化层中的氧浓度的氧浓度的第一横向层。

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